Abstract: A scalable highest available voltage selector circuit determines the highest of n input voltages and connects the highest voltage to an output. The circuit has at least n circuit branches, each of which comprises n?1 “comparator” FETs connected between an input voltage and an output node, and a diode-connected FET connected between the output node and a current source. The junction of the diode-connected transistor and current source provides a control signal used by the other branches. Each of a branch's comparator FETs have their gates connected to a respective one of the other branches' control signals, such that they are driven on regeneratively when the applied input voltage is the highest of the n input voltages. Each branch also includes n?1 “shorting” FETs connected across the diode-connected transistor, arranged to be driven off when the applied input voltage is the highest, but which are otherwise driven on.

Abstract: A voltage sensing device with which high-precision voltage sensing is possible without the need to obtain a unique correction constant for each device. A pair of voltage input nodes NCk and NCk-1 is selected from voltage input nodes NC0-NCn in switch part 10, and they are connected to sensing input nodes NA and NB in two types of patterns with different polarity (forward connection, reverse connection). Sensing input nodes NA and NB are held at reference potential Vm by voltage sensing part 20, and current Ina and Inb corresponding to the voltage at voltage input nodes NCk and NCk-1 flows to input resistors RIk and RIk-1. Currents Ina and Inb are synthesized at different ratios in voltage sensing part 20, and sensed voltage signal S20 is generated according to the synthesized current Ic. Sensed voltage data S40 with low error is generated according to the difference between the two sensed voltage signals S20 generated in the two connection patterns.

Abstract: A thermal sensor providing simultaneous measurement of two diodes. A first diode and a second diode are coupled to a first current source and a second current source, respectively. The ratio of the currents provided by the two sources is accurately know The voltage across each of the two diodes may be coupled to the input of a differential amplifier for determination of temperature. Alternatively, the first diode may be coupled to a first current source by a resistor with a known voltage drop, the second diode may be coupled to an adjustable second current source. The current in the second diode is equal to the sum of voltage drop across the first diode and the known voltage drop across the resistor. Under the established conditions, the Diode Equation may be used to calculate a temperature.

Abstract: A differential-to-single ended converter circuit can include a latching circuit having first and second latch field effect transistors (FETs) with drains and gates cross-coupled between a first latch node and a second latch node. The source-drain paths of the first and second latch FETs are coupled to a first reference potential node via separate current paths. A sense circuit can include a first sense FET having a source-drain path coupled between the first sense node and the first reference potential node, and a gate coupled to a first input node. A second sense FET has a source-drain path coupled between the second sense node and the first reference potential node, and a gate coupled to a second input node.

Abstract: A differential amplifier includes an amplification unit and a feedback unit. The amplification unit amplifies a voltage difference between a first input signal and a second input signal and outputs a first output signal and a second output signal. The feedback unit amplifies a voltage difference between a first feedback signal based on the first output signal and a second feedback signal based on the second output signal.

Abstract: An input buffer includes a driving signal generation unit, a comparison signal generation unit, and a driving unit. The driving signal generation unit is configured to generate first and second driving signals which are selectively enabled in response to a control signal generated depending on a level of an input signal. The comparison signal generation unit is configured to compare the level of the input signal with the level of a reference voltage and generate a comparison signal. The driving unit is configured to buffer the comparison signal and drive an output signal with a drivability determined by the first and second driving signals.

Abstract: A comparator circuit can achieve a reduction in current consumption with a simple configuration, and can suppress an increase in current consumption accompanying a rise in power source voltage. A current mirror circuit is connected to a power source, and gates of MOSFETs of the circuit are interconnected. An input signal is applied to a gate of an NMOSFET of the circuit. By determining the value of the signal with a constant voltage device, the voltage across a tail resistor is constant, even in the event that the power source voltage and the input signal change.

Abstract: A metering system can include a pull up circuit to be selectively coupled between a voltage node and a metering line that communicates a signal indicative of status of a flow line through which a metered substance flows. An impedance of the pull up circuit is set to reduce power consumption based on a calibration, and the pull up circuit can be disabled between sampling of the signal to reduce power consumption.

Abstract: An envelope detecting circuit is provided. The envelope detecting circuit comprises a source degeneration circuit that amplifies an input differential signal, a differential gain stage that supplies a voltage proportional to the amplified signal, a potential hold circuit that holds the voltage supplied from the gain stage, a comparator circuit that compares the voltage held by the potential holding circuit with a reference potential to output a detect signal, and envelope level adjustment and selection unit that responds to the detect signal and outputs a control signal to the source degeneration circuit.

Abstract: A voltage comparator, comprises: a first branch comprising a first transistor, a first resistor (R1), and a first current dependent voltage source (VA), wherein a first voltage (V1) is applied across the first branch to generate a first current and wherein the first transistor is a diode-connected transistor; a second branch comprising a second resistor (R2), a second current dependent voltage source (VB), and a second transistor having a control voltage (V3), wherein a second voltage (V2) is applied on an end of the second branch to generate a second current; and a third branch for generating a comparator output, wherein a trip point of the comparator output is set to when the first current and the second current are equal and wherein the trip point is a function of the transistors, the resistors, and the current dependent voltage sources of the first branch and the second branch.

Abstract: A digital noise filter circuit includes a gating clock generating circuit and a noise filter circuit. The gating clock generating circuit compares logic levels of an input signal and an output signal of the noise filter circuit. The gating clock generating circuit supplies a gating clock as an operating clock to the noise filter circuit when the logic levels of both signals do not coincide, and halts supply of the gating clock when the logic levels of both signals do coincide. The noise filter circuit removes noise from the input signal and outputting the resultant signal as the output signal.

Abstract: A MOS integrated circuit includes: a voltage-to-current conversion circuit configured to convert first and second voltages to a first current having a current value corresponding to the first voltage and a second current having a current value corresponding to the second voltage; and a current comparison circuit configured to compare the respective current values of the first and second currents and to output a voltage showing the comparison result. Oxide films of MOS transistors of the current comparison circuit are thinner than oxide films of MOS transistors of the voltage-to-current conversion circuit.

Abstract: Disclosed is a decoder, receiving the first and the second reference voltage groups and selecting a reference voltage in accordance with a received digital signal, including a first sub-decoder receiving the first reference voltage group, a second sub-decoder receiving the second reference voltage group 20B, and a third sub-decoder receiving a reference voltage selected by the second sub-decoder and outputting the selected reference voltage to the first sub-decoder or an output terminal of the decoder. The first sub-decoder includes a transistor of a first conductivity type having a back gate supplied with a first power supply voltage, the second sub-decoder includes a transistor of the first conductivity type having a back gate supplied with a second power supply voltage, and the third sub-decoder includes a transistor of the first conductivity type having a back gate supplied with a first power supply voltage.

Abstract: An abnormality detection circuit monitors the sink current Irnf of a H-bridge circuit and determines the presence of an abnormal state if the sink current is not detected for a predetermined time. The abnormality detection circuit includes a clock pulse generator, a counter and a NMOS transistor. The abnormality detection circuit includes a clock pulse generator arranged to generate a clock pulse of a predetermined frequency, and a counter arranged so that a count value is incremented every time the clock pulse is provided to the counter and arranged so that the count value is reset when the sink current is detected. The counter generates a first abnormality detection signal that changes from a normal logic level to an abnormal logic level when the count value reaches a predetermined value without being reset.

Abstract: One of differential signals is inputted to a first input terminal. The other of the differential signals is inputted to a second input terminal. A first sample hold circuit samples the signal inputted to the first input terminal and hold it thereafter. A second sample hold circuit samples the signal inputted to the second input terminal and holds it thereafter. A comparison unit compares a signal corresponding to a difference between respective output signals from the first and the second sample hold circuits, with a predetermined threshold value. A latch circuit latches an output from the comparison unit. Sample timings of the first and the second sample hold circuits and a latch timing of the latch circuit can be adjusted independently.

Abstract: In today's environment class-D amplifiers are used to provide an integrated solution for applications such as powered audio devices due to their advantages in power consumption and size over more traditional analog amplifiers. Due to power output requirements, the output stages of power drivers such as class-D amplifiers require a supply voltage in excess of the technologically allowed voltage for the switches in the output stage. A level shifter is used to ensure voltages supplied to the output switches do not exceed the technological limits. An ideal level shifter should provide the optimal voltage swing to output switches under all process, supply voltage and temperature (PVT) variations. The ideal level shifter should also provide fast transitions when the control signal changes from high to low and low to high.

Abstract: A high-speed multi-stage voltage comparator is provided. The multi-stage voltage comparator is configured to eliminate offset from outputs of preamplifiers through respective offset-cancellation switches, and to reset the outputs of the preamplifiers through respective reset switches to reduce an output recovery time. Thus, the multi-stage voltage comparator operates with high accuracy and at a high speed, so that it can be usefully applied to an analog-to-digital converter (ADC), and particularly, a high-speed successive approximation register ADC (SAR ADC).

Abstract: A mixer having high linearity and an associated transconductor combining programmable gain amplifier and mixer functions are provided. The transconductor includes first and second resistors, a differential amplifier, first and second feedback circuits, and first and second transistors. A differential voltage signal is inputted to first and second input ends of the differential amplifier via the first and second resistors. The first and second feedback circuits are provided between a first output end and the first input end, and a second output end and the second input end of the differential amplifier, respectively. The first output end outputs a first output signal for controlling a first current passing through the first transistor. The second output end outputs a second output signal for controlling a second current passing through the second transistor. The first current and the second current determine a differential current.

Abstract: A threshold comparator with hysteresis includes a comparator circuit, having a first input, for receiving an input voltage, a second input, and an output, which supplies an output voltage having a first value and a second value. A current generator, controlled by the output voltage, supplies a current to the first input in the presence selectively of one between the first value and second value of the output voltage. A selector circuit connects the second input of the comparator circuit to a first reference voltage source, which supplies a first reference voltage, in response to first edges of the output voltage, and to a second reference voltage source, which supplies a second reference voltage, in response to second edges of the output voltage, opposite to the first edges.

Abstract: A full-wave rectifier circuit receives complementary signals and produces a current corresponding to an added value of differential signals at different levels. A voltage comparator performs a comparison between output signals produced and subjected to current addition and voltage conversion by the full-wave rectifier circuit. A timer detects whether an output signal of the voltage comparator is kept in the same state for a predetermined time or more, and produces a signal indicating a result of the detection. A signal detecting circuit that can accurately identify a state of digital signals of a minute amplitude transferred through a pair of complementary signal lines is achieved without complicating manufacturing steps.

Abstract: The invention discloses a method for tuning nano-scale analog-circuit designs in order to reduce random-device mismatches and optimize said design, where nano-scale devices potentially have large-scale process variations. The method includes providing a tunable circuit topology, wherein each nano-scale device comprises a single component or comprises multiple parallel components. Each component is decomposed into multiple discrete sub-components, wherein each said sub-component either operates in parallel with other like components to effectively operate like one bigger component. The sub-components are subjected to a dynamic-programming process to adaptively select the sub-components to be kept operational, while configuring the nonselected sub-components to be nonoperational, based on the measurement of at least one operational parameter.

Abstract: Embodiments of the invention relate to an input-powered comparator. Embodiments of the invention also pertain to an active diode that includes an input-powered comparator and a switch. In a specific embodiment, the input-powered comparator only consumes power when an input source provides sufficiently high voltage. Embodiments of the active diode can be used in an energy harvesting system. The comparator can be powered by the input and the system can be configured such that the comparator only consumes power when the input is ready to provide power to the load or energy storage element. In a specific embodiment, when there is no input, or the input is too low for harvesting, the comparator does not draw any power from the energy storage element (e.g., battery or capacitor) of the system.

Abstract: A comparator circuit for providing hysteresis comprises first and second differentially coupled transistors. The first of the differentially coupled transistors provides drain current to first and second load transistors. The second of the differentially coupled transistors provides drain current to third and fourth load transistors. In one example embodiment, the drain of the first of the differentially coupled transistors also drives the gate of the first and third load transistors, while the drain of the second of the differentially coupled transistors drives the gate of the second and fourth transistors.

Abstract: A MOS integrated circuit includes: a voltage-to-current conversion circuit configured to convert first and second voltages to a first current having a current value corresponding to the first voltage and a second current having a current value corresponding to the second voltage; and a current comparison circuit configured to compare the respective current values of the first and second currents and to output a voltage showing the comparison result. Oxide films of MOS transistors of the current comparison circuit are thinner than oxide films of MOS transistors of the voltage-to-current conversion circuit.

Abstract: A comparator comprises a differential amplifier (T1, T2, T8, T9) having differential inputs (IN1, IN2) forming the comparator inputs, and a first and a second amplifier output (f1, f2) forming the comparator outputs of a first comparator stage, wherein the differential amplifier has first (T1, T8) and second (T2, T9) parallel branches. The comparator has a first current source circuit (32) defines a current to be driven through the differential amplifier, a second current source circuit (34) comprising a load driven by the first branch and a third current source circuit (36), comprising a load driven by the second branch. Circuitry (T6,T7) is provided for defining the voltage difference between the first and second amplifier outputs when the differential amplifier is in a stable state providing a differential output. This arrangement drives current through the two branches independently, so that the main transistors in each branch can be kept on to enable rapid response times.

Abstract: A clock signal generating circuit includes a main clock buffering unit and a sub clock buffering unit. The main clock buffering unit is capable of generating both a differential clock signal pair and a single clock signal. The main clock buffering unit selectively outputs either the differential clock signal pair or the single clock signal depending upon the frequency of an external clock signal. The sub clock buffering unit receives the output of the main clock buffering unit and generates first and second clock signals. The operation of the sub clock buffering unit depends upon whether the differential clock signal pair or the single clock signal is output by the main clock buffering unit.

Abstract: The present invention provides a thermostatic biasing controller for use with an integrated circuit. In one embodiment, the thermostatic biasing controller includes a temperature sensing unit configured to determine an operating temperature of the integrated circuit. Additionally, the thermostatic biasing controller also includes a voltage controlling unit coupled to the temperature sensing unit and configured to provide a back-bias voltage corresponding to the operating temperature based on reducing a quiescent current of the integrated circuit.

Abstract: This disclosure relates to permuting transistors to compensate for offsets generated by transient variations of the transistors' parameters.

Abstract: A digital compensation of an input stage of a comparator may be achieved by providing switched load elements, which may be appropriately connected to the differential input pair of the comparator in order to match transistor characteristics of the input pair and also match the load value of the input stage. Thus, enhanced offset behavior may be accomplished without providing an external signal and/or without requiring complex reference voltages/currents.

Abstract: A compare cycle of a comparator includes a precharge phase and a compare phase. During the precharge phase, a node of the comparator is precharged to a defined voltage. In addition, during the precharge phase an input transistor of the comparator is decoupled from the node. During the compare phase, an input voltage is coupled to the node via the input transistor. The input transistor is maintained in saturation during both the precharge phase and the compare phase, reducing switching noise.

Abstract: A MOS integrated circuit includes: a voltage-to-current conversion circuit configured to convert first and second voltages to a first current having a current value corresponding to the first voltage and a second current having a current value corresponding to the second voltage; and a current comparison circuit configured to compare the respective current values of the first and second currents and to output a voltage showing the comparison result. Oxide films of MOS transistors of the current comparison circuit are thinner than oxide films of MOS transistors of the voltage-to-current conversion circuit.

Abstract: A semiconductor device includes a reference voltage generating unit configured to produce a reference voltage by dividing a voltage difference between a positive clock terminal and a negative clock terminal, and a logic determination unit configured to determine a logic level of an external signal based on the reference voltage.

Abstract: A monitoring and control circuit comprises a sense block, a first and a second comparators, and a control module. The current sense block is coupled to a switch for generating a monitoring signal indicative of a current flowing through the switch. The first comparator coupled to the sense block is operable for comparing the monitoring signal to a first threshold and for providing a first signal according to a first comparison result between the monitoring signal and the first threshold. The second comparator coupled to the sense block is operable for comparing the monitoring signal to a second threshold and for providing a second signal according to a second comparison result between the monitoring signal and the second threshold. The control module coupled to the first comparator and the second comparator provides a control signal for controlling the switch according to the first signal and the second signal so as to adjust the current.

Abstract: A comparison amplification unit compares a level of a signal in a positive line with that of a signal in a negative line and latches a comparison result. An input terminal of a first inverter is connected to the positive line and an output terminal thereof is connected to the negative line. An input terminal of a second inverter is connected to the negative line and an output terminal thereof is connected to the positive line. An activation switch selectively switches between a state where the activation switch outputs a power supply voltage to the other power supply terminals of the inverters that are connected in common, such that the comparison amplification unit is inactivated, and a state where the activation switch outputs the ground voltage such that the comparison amplification is activated. The comparator outputs a signal corresponding to at least one of the signal in the positive line and the signal in the negative line at a timing after the comparison amplification unit is activated.

Abstract: A comparator circuit for providing hysteresis comprises first and second differentially coupled transistors. The first of the differentially coupled transistors provides drain current to first and second load transistors. The second of the differentially coupled transistors provides drain current to third and fourth load transistors. In one example embodiment, the drain of the first of the differentially coupled transistors also drives the gate of the first and third load transistors, while the drain of the second of the differentially coupled transistors drives the gate of the second and fourth transistors.

Abstract: A temperature-compensated voltage comparator (301) that compares first and second input voltages includes first and second bipolar junction transistors (BJTs) (221 and 222) that convert the first and second input voltages to first and second input currents, respectively. The first and second BJTs share a same thermal environment and their currents are dependent upon temperature. A temperature-compensating circuit (350), which includes a zero thermal coefficient reference (419), generates a logarithmic temperature-compensating factor that compensates for temperature dependency of the first and second BJTs. The temperature-compensating circuit receives one of the input currents, and outputs a temperature-compensated current that is said input current multiplied by the logarithmic temperature-compensating factor. The temperature-compensating circuit shares a thermal environment with the first and second BJTs.

Abstract: [Object] To discriminate whether a cable in conformity with a conventional standard or a cable in conformity with a new standard is connected. [Solving Means] An HPD signal line (902) has, on an expanded HDMI sink apparatus (402) side circuit, a pull-up resistor (911) between the HPD signal line (902) and a voltage supply and a pull-down resistor (913) between the HPD signal line (902) and the ground, and a reserved line (903) has, on the expanded HDMI sink apparatus (402) side circuit, a pull-down resistor (914) between the reserved line (903) and a ground, and within a new HDMI cable (901), a pull-up resistor (912) between the reserved line (903) and a voltage supply of an expanded HDMI source apparatus (401). The expanded HDMI sink apparatus compares a voltage at a test point (19) on the reserved line (903) on the expanded HDMI sink apparatus (402) side with a reference voltage by using a voltage comparator (916).

Abstract: A signal conversion circuit 2 comprises a differential amplifier portion 10 and a source follower portion 20. When differential voltage signals INp and INn are input to a first input terminal 5 and second input terminal 6 respectively, operations occurs either in a mode in which only the differential amplifier portion 10 operates, or a mode in which both the differential amplifier portion 10 and the source follower portion 20 operate, or a mode in which only the source follower portion 20 operates, according to the levels of the differential voltage signals INp and INn. The differential amplifier portion 10 and source follower portion 20 have fewer components compared with a circuit comprising two differential amplifier circuits. By this means, the circuit area can be reduced, and in addition current consumption can be reduced. Also, because the source follower portion 20 performs non-inverting amplification of the differential voltage signals INp and INn, high-speed operation is possible.

Abstract: Power-down mode is activated when equal voltages are detected on a pair of differential inputs. The voltage difference across the differential inputs is equalized by an equalizer and then applied to a multiplier and smoothed and filtered by a low-pass filter to produce an average signal. The average signal is compared to a reference voltage to detect when the voltage difference across the differential inputs is too small. A power-down signal is activated when the average signal is too small. The reference voltage compared can be generated by an equalizer, multiplier, and low-pass filter to match process, temperature, and supply-voltage variations in the primary signal path. The multipliers can be implemented with Gilbert cells. The equalizers can receive control signals to control attenuation of different frequency components.

Abstract: A method and a device for canceling an offset voltage in an output of a comparator circuit include sampling a set of offset voltages; applying a set of correction voltages equal in magnitude and opposite in polarity to the set of offset voltages, the set of correction voltages being applied to an output generating arrangement of the comparator circuit; and enabling output of the output generating arrangement after the set of correction voltages is applied.

Abstract: A digital bit-level repeater for joining two wired-AND buses such as the I2C bus is described. A protocol detector is used for tracking clock and data signals to determine the direction of the transfer. A state machine reads and regenerates the clock lines of both buses and provides the clock-stretching protocol feature on both buses. The repeater is designed to pass data bits from one bus to the other transparently when possible, and to latch and hold each data bit until the receiving bus can be clocked when clock-stretching occurs or when the bus is turned around.

Abstract: A CMOS comparator having a high-speed reduced-output-swing is provided. The high-speed reduced-output-swing comparator may have a fully complementary CMOS design, be self-biased, and have a rail-to-rail input common-mode range. The self-biasing scheme yields a robust comparator with a low sensitivity to temperature, processing variations, supply-voltage variations, and common-mode input voltages. The fully-complementary design leads to a physically small device with low power consumption. The rail-to-rail input common-mode range leads to a versatile comparator which may take a wide range of inputs. The high-speed reduced-output-swing allows for a quick output response to changes in the input.

Abstract: A semiconductor device includes a reference voltage generating unit configured to produce a reference voltage by dividing a voltage difference between a positive clock terminal and a negative clock terminal, and a logic determination unit configured to determine a logic level of an external signal based on the reference voltage.

Abstract: A comparator module applied to a voltage level clamping circuit which can be implemented in an integrated circuit (IC) is provided. The IC includes a parasitic diode coupled between a first voltage source and a second voltage source. The voltage level clamping circuit includes a switch module and a comparator module. The comparator module has an output terminal, a first input terminal coupled to a first voltage source, and a second input terminal coupled to a second voltage source. The comparator module includes a current source module, a first voltage level adjusting circuit module, a second voltage level adjusting circuit module, and a comparing circuit module.

Abstract: A leakage current measurement circuit measuring a substrate leakage current and a gate leakage current in response to a variation in the size of an MOS transistor and a leakage current comparison circuit judging which one of the substrate leakage current and the gate leakage current is dominant. The leakage current measurement circuit includes a charge supply, a leakage current generator and a detection signal generator. The leakage current comparison circuit includes a charge supply, a leakage current comparator and a detection signal generator.

Abstract: A semiconductor device is capable of stably maintaining a voltage level of a shield line, even when a voltage level of an adjacent line is varied. The semiconductor device includes normal lines arranged for transfer of signals, a shield line arranged adjacently to the normal lines, a level shifting circuit for receiving an input signal swinging between a power supply voltage level and a ground voltage level, and shifting the input signal to an output signal swing between the power supply voltage level and a low voltage level lower than the ground voltage level by a predetermined level to output a shifted signal via the shield line, and a signal input unit for transferring the signal provided via the shield line to an output node.

Abstract: A semiconductor device minimizes generation of an output signal skew of an input buffer and thus stabilizes the operation of the semiconductor device. The semiconductor integrated circuit includes an input potential detection unit outputting a detection signal in response to a level of an input signal, an input buffer buffering the input signal, and an output path control unit that receives the output signal of the input buffer and the detection signal of the input potential detection unit and outputs an output driving signal in response to the level of the detection signal.

Abstract: A first auxiliary switch circuit is connected to one terminal and a first terminal of a main switch circuit and generates a first auxiliary detection current. A second auxiliary switch circuit is connected to the other terminal and a second terminal of the main switch circuit and generates a second auxiliary detection current. A current adjustment detection circuit adjusts the first auxiliary detection current so that the potentials of the other terminal and the first terminal are equal and passes the first auxiliary detection current in a direction of receiving the current from the first auxiliary switch circuit and adjusts the second auxiliary detection current so that the potentials of the one terminal and the second terminal are equal and passes the second auxiliary detection current in a direction of outputting the current to the second auxiliary switch circuit, thereby generating a detection current being proportional to the output current.

Abstract: A data receiver and a data receiving method in which the data receiver generates two comparison signals based on amplitude modulated differential input signals, amplifies the comparison signals, compares amplified signals, and outputs logic operation results based on the amplitude modulated differential input signals and the comparison signals, thereby detecting data bits. Accordingly, the number of necessary amplifiers and comparators is reduced and a separate reference voltage generator is not needed, so that chip size reduction and low-power operation is accomplished.

Abstract: A logarithmic linear variable gain CMOS amplifier includes first and second differential pairs of transistors forming a differential input, with each differential pair of transistors including a common source node. A pair of diode-connected load transistors is connected to the first and second differential pairs of transistors, and a third differential pair of transistors is connected to the pair of diode-connected load transistors. The third differential pair of transistors include respective gates connected together and in parallel to gates of the first and second differential pairs of transistors. First and second current mirrors are respectively connected to the common source nodes of the first and second differential pairs of transistors for programmably injecting respective bias currents thereto, with a sum of the respective bias currents remaining constant.