Abstract: Output currents from differentially connected transistors (t1, t2) in a voltage comparator are subtracted from each other and the current difference is converted into voltage, which is amplified and conducted to a gate terminal (gtst) of a switching transistor (t7) at the input of an output stage. A source of a limiting transistor (t8?), whose gate is connected to a terminal (vsn) of the low supply voltage through two series-connected and diode-connected transistors (t8?, t8??) is connected to the gate terminal (gtst). The voltage at the gate terminal (gtst) when the switching transistor (t7) is quiescent is equal to a value between eight and nine tenths of the switching voltage Vsw at the gate of said transistor, at which voltage said transistor triggers a switching in the output stage. Said transistors are of the same type with a similar geometry and they operate in similar current conditions.

Abstract: A semiconductor integrated circuit includes a first power source having a power supply voltage that operates the semiconductor integrated circuit, a voltage comparator that compares the power supply voltage with a reference voltage, and a comparison result recording unit that records a comparison result of the voltage comparator, wherein the comparison result recording unit records a length of a period based on a clock signal for which the power supply voltage exceeds the reference voltage.

Abstract: Box switches are stacked sharing a common current from power sources. The power sources may be current, voltage or a combination of such sources. In preferred embodiments, the transistor switches in the box switches may be paralleled by different polarity transistors that will act to better balance and make symmetrical the output signals. Capacitors may be used to smooth out residual noise voltage signals.

Abstract: Described is a switched-capacitor network and method for performing an analog circuit function. The circuit includes a switched-capacitor network, a comparator, and a voltage-offset network. The switched-capacitor network includes multiple switches, each having a respective threshold voltage and connected to one of a high-limit voltage, a low-limit voltage, and electrical ground. A first comparator input terminal in communication with the switched-capacitor network is configured to receive a node voltage therefrom during a first phase. The second input terminal is configured to receive one of the high-limit voltage and the low-limit voltage. The voltage-offset network provides a voltage shift at the first input terminal setting an input reference level at a mid-level voltage with respect to the high-limit voltage and the low-limit voltage.

Abstract: A versatile, programmable, low-cost transmit line driver is provided. The line driver includes a digital-to-analog converter that receives a digital input and provides an analog output. The line driver is reconfigurable between the voltage mode of operation.

Abstract: A signal amplification device which uses inexpensive standard CMOS and yet is capable of high-accuracy threshold setting. An offset voltage generator detects the direct-current level of an input signal, and generates a positive or negative offset voltage signal. A peak detector outputs, as a peak value, the positive offset voltage signal if the level thereof is higher than the maximum level of the input signal, or the maximum level of the input signal if the maximum level is higher than the positive offset voltage signal. A bottom detector outputs, as a bottom value, the negative offset voltage signal if the level thereof is lower than the minimum level of the input signal, or the minimum level of the input signal if the minimum level is lower than the negative offset voltage signal. A voltage divider subjects the peak and bottom values to voltage division, to generate a threshold level.

Abstract: An object of the present invention is to provide a chattering preventing circuit, a waveform shaping circuit, and a motor drive control circuit including the chattering preventing circuit or the waveform shaping circuit, to provide an FG signal free from noise caused by chattering, without using a hysteresis comparator.

Abstract: A comparator circuit for reducing current consumption in a low consumption mode while suppressing the generation of glitches during a transitional period. The comparator circuit includes a comparison core circuit unit, a monitor circuit unit formed by a first transistor, and a nonlinear amplification circuit. The comparison core circuit includes second and third transistors connected to a constant current source. The source terminal and gate terminal of the first transistor have the same connection as the source terminal and gate terminal of the third transistor. The current flowing to the first transistor is supplied to the nonlinear amplification circuit. The nonlinear amplification circuit amplifies the supplied current with an incorporated constant current source and supplies the amplified current to the source terminals of the second and third transistors of the comparison core circuit.

Abstract: An internal voltage generator is highly tolerant of electrical parameter changes of transistors occurring due to process deviation. The generator can produce an internal voltage within a short setup time when there is a significant difference between a voltage level of an internal voltage when power is initially supplied to the internal voltage generator and a voltage level of an internal voltage to be produced. In one embodiment, the internal voltage generator of the present invention includes a comparator block and an output driving block to produce an internal voltage. The internal voltage generator further includes a reference voltage generation block, which generates at least two reference voltages to be supplied to the comparator block, and an offset section control block, which supplies a control signal for optimizing an offset section, that is, a voltage difference between the reference voltages, to the reference voltage generation block.

Abstract: Signal magnitude comparison apparatus and methods are disclosed. A first input circuit receives a differential input signal and provides a first output signal based on a magnitude of the differential input signal. A second input circuit is operatively coupled to the first input circuit and is operable to receive a second input signal, which may also be a differential signal, and to provide a second output signal based on a magnitude of the second input signal. The operative coupling between the first and second input circuits results in the first output signal and the second output signal forming a differential output signal that is indicative of a difference between the magnitude of the first differential input signal and the magnitude of the second input signal.

Abstract: According to one exemplary embodiment, an amplitude compensation circuit includes a first composite programmable buffer for receiving a first input signal with a first input amplitude. The amplitude compensation circuit further includes a second composite programmable buffer for receiving a second input signal with a second input amplitude. The amplitude compensation circuit also includes a feedback circuit coupled to respective outputs of the first and second composite programmable buffers. According to this embodiment, the feedback circuit compares a first output amplitude of the first composite programmable buffer with a reference voltage and a second output amplitude of the second composite programmable buffer with the reference voltage and provides first and second control signals for adjusting the respective gains of the first and second composite programmable buffers so as to reduce respective differences between the first and second output amplitudes and the reference voltage.

Abstract: A method for operating a threshold circuit arrangement and a threshold circuit arrangement is disclosed. In one embodiment, the invention provides a threshold circuit arrangement, wherein a comparator circuit is configured to compare an input signal is compared with a predetermined threshold, and wherein, depending on the result of the comparison, an output signal is adapted to change its state. A circuit is provided for preventing the change of state of the output signal in the case of predetermined forms of the input signal.

Abstract: A single ended pseudo differential signaling method may add a 1-bit signal to n-bit data if transmitting the n-bit data. Neighboring two signals among the 1-bit signal and data signals are compared to each other to generate detection signals.

Abstract: This invention provides a comparator circuit which outputs a stable waveform without oscillation even if a gradient of a change of a comparison input signal is small and determines a magnitude of the comparison input signal within a predetermined threshold value regardless of the increase/decrease direction of the comparison input signal.

Abstract: A power supply monitoring circuit that monitors and delivers the highest voltage power supply to an IC system includes a voltage comparator that receives two different power supply voltages, and outputs a first signal to the gate of a first switching transistor connected between a first power supply and an system power supply output node. The comparator output is also input to an inverter, the output of which comprises a second signal connected to the gate of a second switching transistor connected between a second power supply and the system power supply output node. When the first supply voltage exceeds the second supply voltage, the first transistor is switched on to connect the first supply to the system output node, and the second transistor is switched off; and vice versa. The comparator includes designed-in hysteresis to prevent simultaneous switching of the two transistors.

Abstract: A circuit and a method are provided to produce a novel comparator with Schmitt trigger hysteresis character. The circuit includes a current source which controls the magnitude of current flow through this comparator circuit. It has a first logic device which is turned ON by a reference voltage, and a second logic device is turned ON by a comparator input voltage. A first feedback device is turned ON by a negative comparator output. A first parallel resistor is connected in parallel to the first feedback device. A second feedback device is turned ON by a positive comparator output. A second parallel resistor is connected in parallel to the second feedback device. The first and second parallel resistors are used to provide the differential comparator with switching voltage offsets which result in the Schmitt trigger hysteresis character.

Abstract: A transition detect circuit includes: a first input port referenced to a first supply voltage node and a second input port referenced to a second supply voltage node. The circuit simultaneously monitors both ports for transitions, and once a transition occurs, directly generates the translated control signals at its output. Once a transition occurs at the inputs, the translated control signal is generated at the output within at most two gate delays. The circuit has very low quiescent current.

Abstract: It is intended to provide a comparator circuit which uses a switched capacitor and has a small circuit size. An input INA is supplied to positive input terminals of comparators Com1 and Com2 through a capacitor Ca by means of a switch SW1. An input INB is supplied to a negative input terminal of the comparator Com1 through a capacitor Cb1 by means of a switch SW2, and in addition, is supplied to a negative input terminal of the comparator Com2 after being inverted through the use of a capacitor Cb2 by means of switches SW3 and SW4. Outputs from the comparators Com1 and Com2 are input to an exclusive OR circuit EXOR, which outputs a result of judgment as to whether or not the input INA is within the range extending between the positive input INB and the negative input INB.

Abstract: An improved comparator circuit and associated methods are disclosed. In one embodiment, the comparator circuit comprises two voltage-to-time converter circuits, one for each input voltage to be compared, and an arbiter circuit for receiving the time-converted output of each converter. Each converter assesses the magnitude of its input voltage, and outputs a signal that is asserted at a time in inverse proportion to the magnitude of the input voltage. In one embodiment, producing the output signal at the asserted time comprises using the input voltage to gate a transistor whose discharge rate dictates the timing of the output signal. The two output signals arrive at an arbiter circuit whose function is to determine which output arrived at the arbiter first, as is indicative of the higher magnitude input voltage, and to set the output of the comparator accordingly.

Abstract: A device and system for controlling current from plural parallel power sources having inrush current hot-swapping capabilities to a load are disclosed. The current controlling device includes a load line for delivering currents from the outputs of the power sources; a current sensor for measuring the load current; and a common sense element for adjusting the load current levels.

Abstract: A differential input comparator circuit comprises an input stage comprising dual polarity input voltages and an output stage adapted to output a differential voltage based on the input voltages, wherein the differential voltage is adapted to be transmitted to a comparator and wherein the circuit has high input impedance and works with high input voltage swings.

Abstract: First, second and third current generators, and first and second switching devices are provided. Current values of the first and second current generators are equal to each other and a current value of the third current generator is twice as large as the current value of the first and second current generators. The first current generator and the third current generator are connected to each other through the first switching device, and the second current generator and the third current generator are connected to each other through the second switching device. A first output is taken out from a node between the first switching device and the first current generator, and a second output is taken out from a node between the second switching device and the second current generator.

Abstract: An operation switching circuit switches over two comparators, which receives communication data, in accordance with a normal mode and a standby mode of a microcomputer. A delay circuit delays a mode switching signal. The mode switching signal and the delayed signal are combined by an OR gate and an AND gate to two comparator control signals, which have different high level periods. The comparators are driven by the comparator control signals, while a multiplexer is driven by the delayed signal. When one comparator is switched from the inoperative state to the operative state, the other comparator is continued to be held operative for the delay period before being switched to the inoperative state.

Abstract: A below-ground sensor interface amplifier is powered by no negative supply voltage, but the amplifier nevertheless senses an input voltage signal below ground potential. The amplifier outputs an output voltage signal that varies proportionately to the input voltage. For an input voltage beginning below ground potential and increasing past ground potential, the amplifier outputs an output voltage that remains between ground potential and a supply voltage. The output voltage increases proportionately to the increase of the input voltage. As the input voltage increases, a gate voltage on a first transistor begins to increase starting at the input voltage at which a second transistor is forced to turn on. The amplifier senses input voltages more than one threshold voltage below ground potential without using a below-ground supply voltage. The gain of the amplifier, as well as the lower limit and the size of the amplifier's voltage operating range are programmable.

Abstract: A differential comparator with reduced offset. The differential comparator includes a first transistor coupled to a first input current and a second transistor coupled to a second input current. The first and second transistors are biased as diodes during a reset phase to store an offset voltage on parasitic capacitances of the first and second transistors. The first and second transistors are connected together as a latch to provide an output during a latch phase. Drain currents of the first and the second transistors substantially equal the first and the second input currents, respectively, during the reset phase and at the beginning of the latch phase. During the latch phase, currents approximately twice as large as differential-mode signal currents provided by the first and the second input currents are provided to the first and the second transistors, respectively.

Abstract: Comparator systems are provided that include cross-coupled transistors which respond to a differential network that receives an input signal. The systems further include a control transistor connected across the cross-coupled transistors and a bias network configured to apply a bias voltage to the control transistor that is substantially the voltage across two transistors which are each biased into saturation. It has been found that this bias during the systems' acquire phase substantially stabilizes the systems' gain over variations in their total environment and that this stabilization enhances the systems' performance.

Abstract: In a comparing circuit, an input signal switching circuit has a first input terminal, a second input terminal, a first output terminal and a second output terminal. The input signal switching circuit is configured to receive a first input signal inputted to the first input terminal and a second input signal inputted to the second input terminal. The input signal switching circuit is also configured to output the first input signal to switchably one of the first and second output terminals and the second input signal to other thereof in accordance with a switching signal. A comparator has a reverse input terminal and a non-reverse input terminal and configured to receive through the reverse input terminal a first signal outputted from the first output terminal, and receive through the non-reverse input terminal a second signal outputted from the second output terminal.

Abstract: An input voltage is applied to an inverting input terminal of a comparator having no hysteresis. A first constant voltage is divided by resistors to create a reference voltage. The reference voltage is applied to a non-inverting input terminal of the comparator through a resistor. Only while an output voltage of the comparator is a low level, a predetermined constant current is supplied to a supply point of the reference voltage and a constant current of the same magnitude is absorbed from the non-inverting input terminal of the comparator.

Abstract: In some embodiments, a receiver includes a first conductor to carry a magnitude encoded controlled frequency signal (CFS) and a second conductor to carry a complementary magnitude encoded controlled frequency signal (CCFS). The receiver further includes circuitry to receive the CFS and CCFS from the first and second conductors and to decode them to produce an output signal. Other embodiments are described and claimed.

Abstract: A programmable, equalizing buffer is provided having feedback transistors used to vary the transfer function of the equalizing buffer, such that a low pass response of a transmission channel is substantially equalized. A zero in the buffer's transfer function is established by a conductive state of transistors caused by signal feedback. Multiple transistors establish increased flexibility for establishing the location of the zero, while a cascade of buffer stages provides a second order transfer function effective to cancel second order channel effects.

Abstract: A comparator circuit that operates over a wide range of input voltage from Vss to Vdd is offered. This comparator circuit includes a first comparator receiving a pair of differential input signals from input terminals, a second comparator to which a pair of differential outputs of the first comparator is inputted, a current source that provides the pair of differential outputs of the first comparator with a very low current that flows to a ground and a third comparator that receives the pair of differential input signals from the input terminals. A differential output of the second comparator and a differential output of the third comparator are combined to make an output signal. The output signal is received by to an inverter. The first comparator is a P-type comparator while the second and the third comparators are N-type comparators.

Abstract: A comparator is provided that compares one or more input signals in a regenerative circuit. One or more switched isolate the signal inputs after regeneration has started but before regeneration has reached such an extent that large voltage swings in the regeneration circuit are transmitted back to the signal source and corrupt the signal source or neighboring circuits. Furthermore, as controlled by a control circuit, the instant of isolating the signal source can be dependent on the degree of regeneration such as being dependent on a predetermined degree of regeneration. The comparator may be incorporated in an electronic device such as an analog-to-digital converter or a wireless receiver or transceiver.

Abstract: Disclosed herewith is a semiconductor integrated circuit provided with a differential input circuit that can transmit data signals fast to an internal circuit free from distortion of their waveforms without increasing the subject chip in size. The differential input circuit is provided with a pair of first differential input transistors used to amplify mainly the low frequency components of those input signals and having gate terminals connected to a pair of input terminals that receive inputs of differential signals respectively, as well as a pair of second differential input transistors used mainly to amplify high frequency components of those input signals and having control terminals connected to a pair of input terminals that receive inputs of differential signals respectively through capacitance elements. The pairs of first and second differential transistors are connected to each other through a differential connection point (common source).

Abstract: A method and structure for comparing an input signal to a reference signal using a comparator comprises a circuit for setting a trip point of a rising edge of an input signal according to a value of an external voltage reference; and at least two transistors, in the circuit, for setting a trip point of a falling edge of an input signal, according to a width-to-length ratio of the at least two transistors. Moreover, the at least two transistors comprises a first transistor of length (Lx) and a width of (Wx); and a second transistor of length (Ly) and a width of (Wy), wherein the width-to-length ratio equals (WxLy)/(WyLx). The trip point of a falling edge of an input signal increases (decreases) by increasing (decreasing) the width-to-length ratio.

Abstract: A voltage detection circuit for detecting the voltage level of a first power source. A first transistor includes a first gate, a first source, and a first drain coupled to the first gate. A second transistor includes a second gate, a second source, and a second drain coupled to the second gate. A comparator includes a first input terminal, a second input terminal coupled to the second drain, and an output terminal. A first resistor is coupled between the first input terminal and the first drain. A second resistor is coupled to the first power source. A third resistor is coupled between the second resistor and the first input terminal. A fourth resistor is coupled between the second resistor and input terminal. A fifth resistor is coupled between the first source, and a second power source. A resistive device is coupled between the first source, and the first power source.

Abstract: The invention provides a method and apparatus for performing a voltage to current conversion. In particular, the invention provides a voltage to current converter configured to vary its transconductance (Gm). Such a converter is configured to receive a voltage input signal combined with a reference voltage signal to be converted to a current output. Optionally, the reference voltage signal may be provided by a parabolic impedance network that includes a bank of resistors and a plurality of corresponding current sources. Each current source corresponds to each node between two resistors, and may be varied in order to program changes in the comparator's Gm. Each resistor and corresponding current source is configured to create an individual reference voltage reference having a value that occurs in a parabolic manner in relation to other voltage references occurring across the impedance network. The converter further includes a plurality of comparators corresponding to the plurality of voltage reference signals.

Abstract: The differential comparator circuit for receiving an input voltage within a pre-determined range, amplifying the input voltage, and outputting an output voltage is provided. The circuit includes: a first differential comparator for receiving the input voltage within a first range portion of the range, amplifying the input voltage within the first range portion, and outputting the output voltage, a detecting circuit electrically connected to the first differential comparator, wherein a trigger signal is produced by the detecting circuit when the first differential comparator is shut down and is detected by the detecting circuit, and a second differential comparator electrically connected to the detecting circuit for receiving the input voltage within a second range portion of the range, amplifying the input voltage within the second range portion, and outputting the output voltage in response to the trigger signal.

Abstract: A sensor for a switching circuit detects the logical state of the switching circuit by monitoring the current flow through the switching circuit. The current flow is conditioned by one or more current limiters and a voltage regulator, coupled in series with the switching circuit. The sensor also includes a current limit control circuit coupled to each of the current limiters. The sensor is effectively shielded from the effect of parasitic capacitance in the switching device because the current flow through the switching circuit reacts immediately and without regard to the level of parasitic capacitance whenever the switching circuit makes a state change.

Abstract: The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a reference output voltage in response to a plurality of reference voltages. The second circuit may be configured to generate an output voltage in response to the reference output voltage and an unknown voltage. The output voltage may comprise accurately controlled hysteresis.

Abstract: A non-complementary comparator includes an evaluation element such as a memory cell, a differential amplifier, or another type of circuit capable adapted to perform an evaluation function, and at least first and second input legs each coupled to a corresponding one of a first and second node of the evaluation element. The first and second input legs have non-complementary structures relative to one another, with each of the non-complementary structures having associated therewith a variable parameter, e.g., a variable resistance, variable current or variable voltage, having a value that is a function of a corresponding input signal. The evaluation element performs a comparison of at least first and second inputs applied to the respective first and second input legs. The input legs may each be implemented as a weighted array of transistors, with each of the transistors in the weighted array associated with a given leg corresponding to a particular bit or other portion of an input signal applied to that leg.

Abstract: A CMOS circuit including a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN) includes a first feedback circuit (6) producing a first delayed signal (V7) on the gate of the pull-down transistor (MN) to turn on the pull-down transistor (MN) a first predetermined amount of time after the pull-up transistor (MP) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN) and a second feedback circuit (4) producing a second delayed signal (V5) on the gate of the pull-up transistor (MP) to turn on the pull-up transistor (MP) a second predetermined amount of time after the pull-down transistor (MN) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN).

Abstract: In a comparing circuit, an input signal switching circuit has a first input terminal, a second input terminal, a first output terminal and a second output terminal. The input signal switching circuit is configured to receive a first input signal inputted to the first input terminal and a second input signal inputted to the second input terminal. The input signal switching circuit is also configured to output the first input signal to switchably one of the first and second output terminals and the second input signal to other thereof in accordance with a switching signal. A comparator has a reverse input terminal and a non-reverse input terminal and configured to receive through the reverse input terminal a first signal outputted from the first output terminal, and receive through the non-reverse input terminal a second signal outputted from the second output terminal.

Abstract: A comparator circuit includes at least one transconductance stage that receives two test voltages and two reference voltages. The transconductance stage produces two test currents that are proportional to the test voltages and two reference currents. A switching circuit is coupled to the transconductance stage. The switching circuit has two output terminals that are coupled to a conventional comparator stage. The switching circuit can combine the test currents with the reference currents to realize a differential swing comparison mode and a common-mode comparison mode as required for testing differential signals. Moreover, by disabling appropriate output signals from the at least one transconductance stage, a single-ended comparison mode is realized. By using two identical transconductance amplifiers, the non-linearity of the transconductance stage is advantageously canceled out.

Abstract: A current sorter has an input section, a comparing section, and a control section. The input section includes a first input unit and a second input unit and generate a first output signal that is indicative of the first input signal and a second output signal that is indicative of a level of the second input signal. The comparing section is coupled with the input section and compares the first output signal and the second output signal to responsively generate a result. The comparing section includes a first comparing unit and a second comparing unit. The control section is coupled with the input section and the comparing section. Furthermore, the control section activates, when receiving an initial load signal, the first input unit, the second input unit, the first comparing unit, and the second comparing unit.

Abstract: Presence or absence of a differential clock is detected. The voltage of each differential clock line is compared to the common-mode voltage and integrated over time by a capacitor. The capacitor is discharged during the portions of the clock cycle that the differential line is over the common-mode voltage. If the clock stops pulsing the capacitor is charged by a current source to activate a clock-loss signal. The clock-loss detector is ideal for high-frequency operation since each differential clock line is applied to only one transistor gate. The common-mode voltage generates a bias voltage for a differential amplifier that receives the true and complement differential clock lines. Diodes prevent capacitor charging by reverse current flow from the differential amplifier when the clock is inactive. The averaged peak voltage or envelope of the differential input signals is detected.

Abstract: A power-down mode is activated when equal voltages are detected on a pair of differential inputs. The voltage difference across the differential inputs is applied to a multiplier, which generates a squared difference. The squared difference is smoothed and filtered by a low-pass filter to produce an average signal. The average signal is compared to a reference voltage, either explicitly or implicitly, to detect when the voltage difference across the differential inputs is too small. A power-down signal is activated when the average signal is too small. The multiplier can be implemented with a Gilbert cell, while a filter-comparator converts the differential Gilbert-cell output to a single-ended signal and filters the signal. The reference voltage compared can be set by the switching threshold of the filter comparator or other logic gates. A complementary Gilbert cell and filter-comparator can be used to increase the operating range.

Abstract: A test circuit receives a plurality of internal test signals and delivers a group of the plurality of internal test signals onto a bus during an idle state of the bus. The bus is coupled to output pins so that the group of internal test signals can be used in debugging operations. The test circuit may include a multiplexing circuit that receives the plurality of internal test signals as inputs and that delivers a selected group of the internal test signals as outputs. The test circuit may also include a switch that couples the selected group of the internal test signals onto the bus during an idle state.

Abstract: A technique for determining performance characteristics of electronic systems is disclosed. In one exemplary embodiment, the technique may be realized as a method for determining performance characteristics of electronic systems. The method includes the steps of measuring a first response on a transmission medium from a falling edge transmitted on the transmission medium, and measuring a second response on the transmission medium from a rising edge transmitted on the transmission medium. The method also includes the step of determining worst case bit patterns for transmission on the transmission medium based upon the first response and the second response.

Abstract: A sensor for a switching circuit detects the logical state of the switching circuit by monitoring the current flow through the switching circuit. The current flow is conditioned by one or more current limiters and a voltage regulator, coupled in series with the switching circuit. The sensor also includes a current limit control circuit coupled to each of the current limiters. The sensor is effectively shielded from the effect of parasitic capacitance in the switching device because the current flow through the switching circuit reacts immediately and without regard to the level of parasitic capacitance whenever the switching circuit makes a state change.

Abstract: The invention relates to a method for operating a comparator (10) and a pre-amplifier (20) of an integrated circuit, which pre-amplifier is connected in series to the comparator, wherein the comparator (10) is operated with clock pulses in order to compare comparator input signals at periodical decision points (t2), wherein the pre-amplifier (20) is operated with clock pulses so as, in amplification phases (t1 to t2) which precede the decision points (t2), to amplify a signal (IN) which has been input to the pre-amplifier, and to provide the amplified signal (OUT) as a comparator input signal, and so as, in reset phases (t0 to t1) which precede the amplification phases (t1 to t2), to reset the amplification (G) to a minimum value. According to the invention, the pre-amplifier (20) is operated such that its amplification (G) during a rise phase within the amplification phase (t1 to t2) rises gradually and uniformly from the minimum value to a maximum value.