Abstract: An oscillator circuit (300) disclosed herein includes an improved capacitor discharge circuit. The oscillator includes at least one capacitor coupled to a charging circuit portion (202, 210) and a discharging circuit portion (208) through a switching network (204, 216, 218, 220 and 222). In the alternative, an oscillator including more than one capacitor includes respective charging and discharging circuit portions connected to respective switching networks. Each charging circuit portion (202, 210) provides sufficient charge to charge the coupled capacitor (206) to a high threshold voltage (VtH). Each discharging circuit portion (208) discharges each coupled capacitor (206) to a low threshold voltage (VtL). The switching network alternately connects each coupled capacitor (206) to the charging circuit portion (202, 210) and the discharging circuit portion (208) to thereby alternately charge and discharge for each coupled capacitor (206) alternately.

Abstract: The invention creates an oscillator circuit, in particular for a refresh timer device of a dynamic semiconductor memory, having a capacitor device (C; C′) which is connected between a first node (6) and a first supply potential (P2); a current mirror circuit (T1; T2) for supplying a charging current for the capacitor device (C; C′) which is connected via a first transistor device (T4) to the first node (6) and which has a current source (SQ) for supplying a substantially temperature-independent reference current (Iref); a second transistor device (T5), which is connected between the first node (6) and the first supply potential (P2); the first and second transistor devices (T4; T5) and a control signal being configured in such a way that the capacitor device (C; C′) can be charged via the first node (6) when a potential (Vcomp) at the first node (6) is lower than the reference potential (Vref), and can be discharged via the first node (6) when the potential (Vcomp) at the first node (6) is h

Abstract: An integrated circuit chip includes an RC oscillator circuit. The frequency of the output signal generated by the oscillator output signal is set as a function of a value of an included internal resistor integrated on the chip. An external resistor may be connected to the chip to allow a user to manipulate the oscillator output signal frequency. A detection circuit on the chip detects the presence of the connected external resistor. Responsive to that detection, a substitution circuit operates to substitute the connected external resistor for the internal resistor in the RC oscillator circuit. This effectuates a change of the frequency of the oscillator output signal to instead be set as a function of a value of that connected external resistor.

Abstract: The present invention relates to a trimmable oscillator circuit which comprises a comparator circuit operable to compare an output voltage of the oscillator circuit to a reference voltage and output a control signal in response thereto. The oscillator circuit further comprises an output capacitor, wherein a voltage at a node of the capacitor comprises the output voltage of the oscillator circuit, and the oscillator circuit also comprises a selectively trimmable charge/discharge circuit coupled between the comparator circuit and the output capacitor. The charge/discharge circuit is operable to charge or discharge the output capacitor based on the control signal, wherein a rate of charge or discharge is dictated by one or more user selectable control signals. Thus an oscillation frequency of the oscillator circuit may be trimmed.

Abstract: A voltage-controlled variable duty-cycle oscillator includes a current generator whose current Iref mirrored in three one-shots that each include two pair of series-coupled MOS transistors and a timing capacitor. The timing capacitor is precharged to Vcc in the first two one-shots, and to a lesser voltage Vcon in the third one-shot. The oscillator also includes pre and a post-NOR-gate logic. Output signals from the two one-shots are coupled to the pre NOR-gate logic to generate an intermediate oscillator signal whose duty cycle is determined by Iref and by the first two timing capacitors. The intermediate oscillator signal and output from the third one-shot are combined in the post NOR-gate logic to yield a VCO output signal whose duty cycle is determined by the ratio of the timing capacitor in the third one-shot compared to the sum of the timing capacitors in the first and second one-shots. VCO output signal duty cycle is a fairly linear function of Vcon.

Abstract: An oscillator circuit for efficiently generating a triangular wave signal having multiple phases. The oscillator circuit includes capacitors, each having two terminals and having a voltage between the two terminals. The capacitors include a first capacitor. A plurality of charge/discharge switching circuits are connected to the first capacitor. Each of the charge/discharge switching circuits generates a switching signal for an associated one of the switches to control the charging and discharging of the associated capacitor. The switching signals of the charge/discharge switching circuits have different phases. Each of the charge/discharge switching circuits receives a first capacitor voltage between the terminals of the first capacitor and compares the first capacitor voltage with a first reference voltage and a second reference voltage to generate the switching signal that has a predetermined phase. A triangular wave signal is generated at one of the two terminals of each of the capacitors.

Abstract: An improved relaxation oscillator circuit is provided using conventional CMOS device shunted with a current source (101 and 103) at each load of two cross-coupled gain stages. The improved oscillator uses a clamp voltage reference (134), to control the voltage swing across the charging/discharging capacitor (118). The improvements provide improved speed to power ratio, increased frequency tuning range, and less process and temperature variation effects. A transistor (130) and current source (138) replicate output transistors (110, 114) and current sources (101, 103).

Abstract: An oscillator includes a first sawtooth waveform generator for generating a first sawtooth waveform having a selectively started ramp portion and a second sawtooth waveform generator for generating a second sawtooth waveform having a selectively started ramp portion. A controller is also included for alternatingly controlling the first and second sawtooth waveform generators so that a transition to the ramp portion of one sawtooth waveform is based upon determining the ramp portion of the other sawtooth waveform reaching a trip point. The controller also sets the trip point substantially independent of a supply voltage so that the oscillator has reduced sensitivity to supply voltage changes.

Abstract: A RC oscillator circuit with a stable output frequency, having an oscillating integrated circuit working under an operation voltage, the resistor, a first capacitor, a second capacitor, and a transistor. The first and second capacitors construct a RC circuit. The resistor has first and second terminals coupled to output and input terminals of the oscillating integrated device, respectively. The first capacitor has first and second terminals coupled to the input terminal of the oscillating integrated device and the second terminal of the resistor, respectively. The second capacitor has first and second terminals coupled to the second terminal of the first capacitor and ground, respectively. The transistor has a gate coupled to the operation voltage, a drain coupled to the first terminal of the second capacitor, and a grounded source. The RC oscillator circuit with a modulable frequency can work under difference operation voltages and output the same frequency.

Abstract: The present invention relates to a trimmable oscillator circuit which comprises a comparator circuit operable to compare an output voltage of the oscillator circuit to a reference voltage and output a control signal in response thereto. The oscillator circuit further comprises an output capacitor, wherein a voltage at a node of the capacitor comprises the output voltage of the oscillator circuit, and the oscillator circuit also comprises a selectively trimmable charge/discharge circuit coupled between the comparator circuit and the output capacitor. The charge/discharge circuit is operable to charge or discharge the output capacitor based on the control signal, wherein a rate of charge or discharge is dictated by one or more user selectable control signals. Thus an oscillation frequency of the oscillator circuit may be trimmed.

Abstract: An oscillator circuit configured to generate an output signal having a frequency comprising a current source, a trim circuit, and one or more capacitors. The current source may be configured to generate a temperature independent current in response to a first adjustment signal. The trim circuit may be configured to generate the first adjustment signal. The one or more capacitors may be configured to charge to a controlled voltage using the temperature independent current. The controlled voltage may regulate a variation of the frequency of the output signal.

Abstract: Integrated oscillator circuit of the relaxation type, wherein the circuit comprises a controllable current source I(&bgr;) and a gate oxide capacitor (Cox) which both have a dependency on a common transconductance &bgr;.

Abstract: A VCO includes a non-inverting output and an inverting output coupled to symmetrical circuitry configured to produce an oscillating output at the outputs. The symmetrical circuitry can include, for example, matched devices such as voltage-controlled resistors (VCRs) and capacitors. The symmetrical circuitry coupled to the non-inverting output and inverting output results in a stable output that operates close to the optimal 50% duty cycle independent of frequency and across a wide range of frequencies. In an alternative embodiment, the VCO further includes an output differential amplifier having its non-inverting input coupled to the non-inverting output and its inverting input coupled to the inverting output. The VCO according to this embodiment exhibits higher gain and a stable output that operates close to the optimal 50% duty cycle independent of frequency and across a wide range of frequencies.

Abstract: An adjustable voltage controlled oscillator has an input for receiving a voltage signal and an integrator coupled to the input for generating a ramp signal. The circuit also includes an adjustable current supply coupled to an output of the integrator for supplying an adjustable amount of current. A comparator compares the ramp signal with a predetermined voltage. The circuit further includes an output for generating a frequency output as a function of the comparison, wherein the circuit is calibratible by adjusting current generated by the adjustable current supply.

Abstract: The inverter functioning as a comparator, dummy inverter having the same electric characteristics as the inverter, and control circuit are provided. Vth detecting input voltage output from the control circuit is input into the dummy inverter, Vth detecting output voltage output from the dummy inverter is input into the control circuit, and the threshold voltage of the dummy inverter is detected. The threshold voltage of the inverter is controlled by controlling the back gate voltages of the MOS transistors of the dummy inverter and the inverter in such a manner that the threshold voltage of the dummy inverter coincide with an external reference voltage.

Abstract: A linear voltage-to-duty cycle converter is disclosed in which an input voltage to be converted is transformed to a triangle wave signal which has up and down ramps whose slopes are variable with the input voltage. A hysteresis comparator receives the triangle wave signal and produces a resulting output signal that has either a high value or a low value depending on the triangle wave signal condition. The time the resultant output signal is high or low compared to the overall time constitutes a duty cycle that is linear with respect to changes in the input voltage.

Abstract: A VCO includes a non-inverting output and an inverting output coupled to symmetrical circuitry configured to produce an oscillating output at the outputs. The symmetrical circuitry can include, for example, matched devices such as voltage-controlled resistors (VCRs) and capacitors. The symmetrical circuitry coupled to the non-inverting output and inverting output results in a stable output that operates close to the optimal 50% duty cycle independent of frequency and across a wide range of frequencies. In an alternative embodiment, the VCO further includes an output differential amplifier having its non-inverting input coupled to the non-inverting output and its inverting input coupled to the inverting output. The VCO according to this embodiment exhibits higher gain and a stable output that operates close to the optimal 50% duty cycle independent of frequency and across a wide range of frequencies.

Abstract: An oscillator circuit includes an oscillation circuit producing a RAMP signal and at least two control signals STATE2 and STATE3, and a comparator comparing an externally produced error signal ERR with the RAMP signal. When the ERR signal is between minimum and maximum levels of the RAMP signal, the duty cycle of a PWMOUT signal of the oscillator circuit varies as a function of the difference between the ERR and RAMP signals, and preferably accounts for approximately 85% of the total period. When the ERR signal is less than or equal to the minimum level of the RAMP signal, the duty cycle of the PWMOUT signal is fixed at a first value which is preferably approximately 5% of the total duty cycle. When the ERR signal is greater than or equal to the maximum level of the RAMP signal, the duty cycle of the PWMOUT signal is fixed at a second value which is preferably approximately 90% of the total period.

Abstract: An adjustable oscillating frequency function generator. The oscillating frequency of the function generator can be adjusted externally. The oscillation frequency is independent of the magnitude of the voltage source. Therefore, a pulse signal that withstands the voltage source signal can be provided.

Abstract: An oscillator has a slope-fixing circuit that generates a control signal and fixes the slope of the control signal, a swing-fixing circuit that fixes the swing of the control signal, and a switching block that generates an output signal having a frequency derived from the swing and the slope of the control signal. The slope-fixing circuit comprises a fixed timing capacitor C1 in parallel with a plurality of switchable timing capacitors C2 . . . CN to provide an effective capacitance C. The slope of the control signal is determined by the ratio of a control current I to the effective capacitance C. The swing-fixing circuit comprises a replica cell that accepts a programmable reference voltage VREF and provides a fixed voltage swing VSW=VDD−VREF across a pair of load transistors. The switching block comprises a pair of switching transistors that alternate between “on” and “off” states depending on the value of the control signal to produce an oscillating output signal.

Abstract: An integrated circuit (10) is disclosed comprising a fundamental frequency oscillator comprising a reference node (32) whose voltage varies between a high threshold and a low threshold. The fundamental frequency oscillator is operable to generate a first output at the fundamental frequency on a first output node (36). The integrated circuit (10) also comprises a circuit (C2) coupled to the reference node. The circuit (C2) is operable to sense the voltage at the reference node (32), to determine when the voltage exceeds an intermediate threshold between the high threshold and the low threshold, and to generate a second output in response to the determination. The integrated circuit (10) also comprises logic (40) coupled to the circuit (C2) and load circuitry (50) coupled to the logic (40). The logic (40) is operable to generate an output signal at an output frequency greater than the fundamental frequency in response to the second output and the first output.

Abstract: An oscillator circuit that adjusts the oscillation voltage such that the voltage oscillates in a uniform manner independent of changes to frequency. Slope compensation is derived from the oscillation voltage. The adjustment is implemented by using a window comparator to establish a range of operation of the oscillation voltage. When the oscillation voltage is outside the range of operation, the window comparator instructs a counter circuit to either count up or count down, depending on the value of the oscillation voltage relative to the range. This counting then is used to adjust the amount of current which charges the capacitor. Thus, when the peak voltage is too low, the amount of current is adjusted upward. When the peak voltage is too high, the amount of current is adjusted downward. In this fashion, the oscillation voltage is maintained at a substantially uniform value, while the frequency is synchronized to an external clock signal.

Abstract: Presented is a low supply voltage oscillator circuit having at least one capacitor to be controlled, connected between first and second voltage references, and a circuit for charging and discharging the capacitor to be controlled. The oscillator circuit also includes at least first and second stages having symmetrical structures in a mirror-image configuration and being connected between the first voltage reference and the second voltage reference and connected together through a memory element. The oscillator circuit also includes respective primary switches for alternately charging the capacitors in a controlled fashion.

Abstract: Several calibration techniques for a precision relaxation oscillator with temperature compensation produces a stable clock frequency over wide variations of ambient temperature. The calibration techniques provide for different methods of determining CTAT current, PTAT current or the ratio of PTAT current to CTAT current. The calibration techniques provide different methods for determining CTAT and PTAT calibration values and for setting CTAT and PTAT calibration select switches.

Abstract: An apparatus and method for achieving accurate temperature-invariant sampling frequencies in a device, such as, a multiple message non-volatile multilevel analog signal recording and playback system is described. An oscillator is used to generate an oscillation frequency. A bandgap voltage generator generates a zero temperature coefficient voltage reference (V(OTC)) that is independent of temperature. This V(OTC) is applied to the oscillator. A variable temperature coefficient voltage (V(TC)) that compensates for temperature coefficient variations of a resistor to which V(TC) is applied produces a stable oscillator current Iosc. Therefore, the stable oscillator current Iosc is likewise independent of the temperature coefficient variations of the resistor. The stable oscillator current Iosc is applied to the oscillator such that the oscillator generates a stable temperature-invariant oscillation frequency.

Abstract: A digitally-controlled oscillator (DCO) (60), such as may be used in clock generator or clock recovery circuitry in an integrated circuit, is disclosed. The disclosed DCO (60) is a single-stage oscillator including a variable load implemented as a binary-weighted array of switched capacitors (40). Each of capacitors (40) has a plate connected to a common node (X), and a plate that receives a signal corresponding to one bit of a digital control word (DCOCW). The common capacitor node (X) is also connected to the input of a Schmitt trigger (42) that produces the output clock signal (OUTCLK) and a feedback signal that is applied to logic (38, 39) that inverts the common node of the capacitors (40). The switching time at the input of Schmitt trigger (42) depends upon the variable load presented by the array of switched capacitors (40), which is controlled by the digital control word (DCOCW). As a result, the clock signal (OUTCLK) is digitally synthesized by a single stage of the DCO (60).

Abstract: The present invention concerns an oscillator (20) intended to supply a periodic electric voltage (Vo) at a predetermined frequency (f). This oscillator includes: a reference source (23) able to provide a reference voltage (Vref), this reference source including a resistor (R) linked to said voltage; and supply means (24) able to receive the reference voltage and to supply said periodic voltage at said predetermined frequency, the supply means having a first temperature coefficient (&agr;24) so this frequency can vary under the influence of the temperature. This oscillator is characterised in that the resistor is formed to give the reference source a second temperature coefficient (&agr;23) equal to the first temperature coefficient, so that the temperature has the same influence on the reference voltage and on the supply means, which allows the periodic voltage to be supplied independently of the temperature.

Abstract: A micropower RC oscillator having stable frequency characteristics with varying temperature includes a number of inverting circuits which are driven by an external driving voltage and connected in series with each other and an RC circuit having a resistor disposed in between a head-inverter and a tail inverter to form a closed loop and a capacitor disposed between the tail-inverter and the head-inverter. The resistor comprises a plurality of unit resistors constituting of a P+ diffusion resistor and a polysilicon resistor having opposing characteristics with respect to temperature variation at a predetermined ratio. A resistance regulator controls the resistance of the resistor by decoding an external resistance setting data to select a unit resistor that determines the oscillation frequency effectively.

Abstract: An exemplary embodiment of the invention is a method of characterizing capacitances of a plurality of integrated circuit interconnects. The method includes coupling a first oscillator to a first integrated circuit interconnect and coupling a second oscillator to a second integrated circuit interconnect. The first oscillator is activated to characterize the sum of (i) coupling capacitance between the first integrated-circuit interconnect and the second integrated-circuit interconnect and (ii) ground capacitance between the first integrated-circuit interconnect and a ground. In addition, both of the first oscillator and the second oscillator are activated to characterize the ground capacitance between the first integrated-circuit interconnect and the ground.

Abstract: A timing device for keeping time by marking the time boundaries between contiguous time periods. Time is measured by measuring charging voltage on a pair of capacitances where each capacitance is charged and discharge in successive cycles. Detection of a preset value of potential on each one of the capacitances is used to initiate commencement of charge on the other capacitance and detection of another preset value on the other capacitor is used to record measurement of potential at a full scale potentail point on the one capacitor. By this means “dynamic” measurements of potential are made by which is meant that the potentials are measured while the potential is changing and rather than when the potential has reached a target end point. This technique eliminates errors arising from unstable conditions at the capacitor due to, for example, dielectric hysteresis, a requirement to measure a charging or discharging step simultaneous with a measuring step, etc.

Abstract: An oscillator circuit includes a current generator which supplies current to input terminals of capacitors in a trimmable capacitor array. The input terminals of the capacitors are held at a relatively constant voltage, and thus all of the current from the current generator passes through the desired capacitors of the capacitor array, thus minimizing the effect of parasitic capacitance.

Abstract: A frequency comparator includes a circuit comparing, independently of a phase relationship between first and second clocks, frequencies of the first and second clocks and outputting first and second detection signals when the first clock has frequencies higher and lower than those of the second clock, respectively. The first and second detection signals are output for respective times based on a difference between the frequencies of the first and second clocks.

Abstract: A circuit arrangement includes a self-oscillating oscillator circuit electrically connected with a series arrangement of a resistor arranged in series with a capacitor. The series arrangement determines the oscillation frequency of the oscillator circuit. The oscillator circuit serves to supply an oscillating supply voltage to an electronic device that exhibits a resonant frequency. A control signal output of the electronic device has a resistive coupling to the series arrangement. The control signal output serves to supply a control signal representative of the oscillation mode of the electronic device.

Abstract: An oscillation circuit for outputting an oscillation signal includes a comparison circuit and a reference signal generation circuit. The comparison circuit compares two voltage levels and outputs a comparison result as the oscillation signal. The reference signal generation circuit provides a signal input to the comparison circuit. The reference signal generation circuit includes at least two resistance means coupled with each other in series, where one resistance means is given a smaller regulation of the resistance value relative to the temperature as compared with other resistance means.

Abstract: A controller oscillator provides a periodic output signal having first and second output level states. The oscillator is responsive to an applied saw tooth signal that varies between first and second voltages (Vlow,Vhigh). The oscillator is comprised of a comparator (82) the non-inverting input of which receives the saw tooth signal applied thereto to produce the periodic output signal at its output (86). A first voltage reference circuit (88, 90, and 92) generates the second voltage (Vhigh) that is applied to the inverting input of the comparator while the periodic output signal is at the first output level state and the input signal charges from the first voltage (Vlow) towards the second voltage. As the input signal becomes equal to the second voltage the output of the comparator switches to the second output level state and a second voltage reference (92,94, 96) provides the first voltage at the inverting input of the comparator.

Abstract: An electronic delay circuit (10) useful for the delayed initiation of detonators illustrates several novel features that may be combined, including a novel oscillator (34), a programmable timer circuit (32) and a run control circuit (46). The oscillator (34) generates a clock signal determined by the rate of discharge of a capacitor (34a) relative to a reference voltage REF. A second capacitor (34b) is charged to a voltage that exceeds REF, and when the first capacitor (34a) falls below REF, an internal signal is generated and the capacitors are switched, so that the first capacitor gets charged while the second is discharged. A latch (34f) produces clock pulses in response to the internal signals. The programmable timer circuit (32) includes a ripple counter (38) and a program bank (40) that loads a count in the counter upon initialization.

Abstract: A voltage controlled oscillator has first and second complementary output terminals. A first edge delay circuit has an input terminal, an output terminal, and a control input terminal. The input terminal is coupled to the first complementary output terminal. A first comparator has a first, second and third input terminal, an output terminal, and a control input terminal. The first input terminal is coupled to the output terminal of the first edge delay circuit. The second input terminal is coupled to the first complementary output terminal. The first comparator output terminal is coupled to the second complementary output terminal. A second edge delay circuit has an input terminal, an output terminal, and a control input terminal. The input terminal is coupled to the second complementary output terminal. A second comparator has a first, second and third input terminal, an output terminal, and a control input terminal. The first input terminal is coupled to the output terminal of the second edge delay circuit.

Abstract: A resonator includes a resonating device and a selection circuit for selecting a resonance mode. The selection circuit is formed by a first-order oscillator which is provided with a synchronization input and whose output is connected to the excitation input of a resonator, the output of the resonator being connected to the synchronization input of the first-order oscillator in order to synchronize the oscillator and the output signal of the resonator being derived from the oscillator.

Abstract: Disclosed are an integration circuit capable of substantially raising the ratio of a current to a capacitance, I/C, and voltage-controlled oscillator and frequency-voltage converter which employ the integration circuit. The integration circuit comprises an integrating capacitor, a current source, a switch, a detection circuit, and a control circuit. The current source supplies a current to the integrating capacitor. The switch is installed on a path along which a current is supplied from the current source to the integrating capacitor. The detection circuit detects a voltage developed at the integrating capacitor. The control circuit controls the switch so that a current will be supplied from the current source to the integrating capacitor during an integration period. The integration period falls into a current supply period and a stop period.

Abstract: An oscillator having compensation for the response delays of a Schmitt trigger has a first current source that provides a charging current to a capacitor and a second current source for providing a discharging current to the capacitor. The oscillator includes a Schmitt trigger circuit that receives a charge/discharge voltage from the capacitor and generates a square wave oscillator output signal therefrom. The oscillator further includes charge and discharge current control units that compare the charge/discharge voltage from the capacitor to respective charge and discharge threshold voltages. Based on the comparison, the control units divert the flow of charging and discharging current from the capacitor during the response delays of the Schmitt trigger circuit.

Abstract: A method for generating a positive temperature correlated clock frequency is described. The method comprises conducting current through a resistor to charge a capacitor. When the capacitor is charged to a trip point of the inverter at the input of the inverter chain, a transition in an output signal of an inverter chain is triggered. The capacitor is discharged through a grounding device when the output signal activates said grounding device.

Abstract: A programmable multi-scheme clocking circuit supports multiple applications. In one implementation, the clocking circuit includes multiple clock sources such as a crystal oscillator, a RC oscillator, an internal oscillator, and an external clock. Each of the clock sources can be enabled by a respective control signal. A multiplexer couples to the clock sources and provides a clock signal from one of the clock sources as the output clock signal. External support circuitry (e.g., external tank circuits) for some of the clock sources (e.g., the crystal oscillator and the RC oscillator) can be coupled to the clocking circuit through one or more device pins. The pins to support the crystal oscillator, the RC oscillator, and the external clock signal are shared so that no additional device pins are required.

Abstract: An oscillator circuit generates an output frequency that is substantially independent of power supply and temperature variations. The oscillator circuit can be implemented using conventional complementary metal-oxide-semiconductor technology. The oscillator circuit is suitable for use as an internal oscillator for generating a stable reference frequency in telecommunication receiver modules.

Abstract: An oscillator circuit produces first and second oscillating logic signals that are of a same frequency and are non-overlapping in a first logic state. This oscillator includes a flip-flop circuit to produce third and fourth oscillating logic signals of opposite polarities, this flip-flop circuit being driven by first and second driving logic signals. First and second logic gates receive the third and fourth logic signals and produce the first and second logic signals, the logic state transitions in the first and second logic signals being produced as a function of the logic state transitions of the third and fourth logic signals. The first and second logic gates are organized so as to introduce a delay into the transitions from a second logic state to the first logic state, in the first and second logic signals, with respect to transitions in the third and fourth logic signals.

Abstract: A method for calibrating a frequency device by monitoring its output cycles over a first plurality of monitoring windows is disclosed. An accumulation of these monitored cycles is used to determine a correction for the device over a second plurality of monitoring windows. A method for obtaining fractional correction values to be applied for controlling the frequency device is also disclosed.

Abstract: A circuit, such as a phase-lock loop (PLL), has an oscillator having a plurality of operating curves. During circuit auto-trim operations, the oscillator is automatically trimmed to an appropriate oscillator operating curve for use during normal circuit operations. In particular PLL embodiments, the PLL is a charge-pump PLL having a phase/frequency detector (PFD) that generates error signals based on comparing an input signal and a PLL feedback signal; a charge pump that generates amounts of charge corresponding to the error signals; a loop filter that accumulates the amounts of charge to generate a loop-filter voltage; and a voltage-controlled oscillator (VCO), where the VCO output signal is used to generate the PLL feedback signal. During normal PLL operations, the loop-filter voltage is applied to the voltage input of the VCO.

Abstract: Relaxation oscillator comprising a chain of coupled sawtooth generator stages. Each stage has a capacitor which is charged and discharged. The charging of a capacitor begins when the voltage (C.sub.C1) of a previous stage reaches a threshold voltage (V.sub.H). To avoid sampling of noise on the threshold voltage (V.sub.H) each new voltage ramp is started gradually.

Abstract: An oscillator circuit contains a switching circuit which periodically charges and discharges a capacitive node. The capacitive node is coupled to the input of the switching circuit via a loop circuit, so that signal transitions at the capacitive node travel through the loop circuit and cause new transitions. The oscillator contains a power supply current source and a mode breaker circuit which function to stabilize the oscillating frequency and to suppress spurious modes of operation, respectively. The mode breaker circuit contains a conduction path which is used to frustrate charging of the capacitive nodes in certain spurious signal configurations. To prevent the mode breaking function from interference between the stabilizing function, the mode breaker circuit is arranged so that it blocks the conduction path during the critical time-intervals when the loop operates in a desired mode.

Abstract: A current-controlled oscillator includes a capacitor, and at least one current source for providing at least one charge current for charging the capacitor. A discharge circuit sequentially discharges the capacitor with a discharge current. A control circuit maintains a mean charge voltage of the capacitor at a preset value by controlling the discharge current. The control circuit includes a current control source forming a current mirror with the at least one current source. The current control source is connected to the discharge circuit for setting the discharge current substantially equal to a sum of the charge currents. The oscillator further includes a correction circuit for correcting the discharge current corresponding to a mean charge of the capacitor.

Abstract: An oscillation device includes a buffer device, a feedback device for feeding back an output of the buffer device to an input thereof and a charging device and a discharging device connected to the input of the buffer device. The charging device includes a first switching device that is turned on and off based on the output of the buffer device and a first current control device that controls the current flowing into the input of the buffer device through the first switching device. The discharging device includes a second switching device that is turned on or off based on the output of the buffer device and a second current control device that controls the current flowing out of the input of the buffer device through the second switching device. The first and second switching devices include first and second transistors and the first and second current sources that include third and fourth transistors.