Abstract: A particular apparatus for generating a local oscillator (LO) signal includes a phase-locked loop (PLL) configured to output a signal having a frequency that is a sub-harmonic of a LO frequency. The apparatus also includes a mixer block having a frequency upconverter configured to upconvert the signal to generate a LO signal having the LO frequency. For example, the PLL may be integrated into a multiple-input multiple-output (MIMO) device and may generate the sub-harmonic signal. The sub-harmonic signal may be routed to each of a plurality of mixer blocks of the MIMO device. Each of the mixer blocks may upconvert the sub-harmonic signal to generate the LO signal.

Abstract: A system includes a first clock module, a global positioning system (GPS) module, a phase-locked loop (PLL) module, a cellular transceiver, and a baseband module. The first clock module generates a first clock reference. The GPS module operates in response to the first clock reference. The WLAN module operates in response to the first clock reference. The PLL module generates a second clock reference by performing automatic frequency correction (AFC) on the first clock reference in response to an AFC signal. The cellular transceiver receives radio frequency signals from a wireless medium and generates baseband signals in response to the received radio frequency signals. The baseband module receives the baseband signals, operates in response to a selected one of the first clock reference and the second clock reference, and generates the AFC signal in response to the baseband signals.

Abstract: The present invention discloses a frequency synthesizer which includes: a PLL including an oscillator for generating an oscillator signal and a first frequency divider for dividing a frequency of the oscillator signal to generate a first frequency-divided signal; a switching unit for switching the PLL to either an open loop status or a closed loop status; a second frequency divider, for dividing a frequency of a reference clock to generate a second frequency-divided signal; a counter, for counting according to the first frequency-divided signal and the second frequency-divided signal to generate a counter value when the PLL is in the open loop status; a comparator, for comparing the counter value with a predetermined value to generate a comparing result; and a determining unit, for adjusting an oscillator frequency of the oscillator according to the comparing result.

Abstract: Capacitive adjustment in an RCL resonant circuit is typically performed by adjusting a DC voltage being applied to one side of the capacitor. One side of the capacitor is usually connected to either the output node or the gate of a regenerative circuit in an RCL resonant circuit. The capacitance loading the resonant circuit becomes a function of the DC voltage and the AC sinusoidal signal generated by the resonant circuit. By capacitively coupling both nodes of the capacitor, a DC voltage can control the value of the capacitor over the full swing of the output waveform. In addition, instead of the RCL resonant circuit driving a single differential function loading the outputs, each output drives an independent single ended function; thereby providing two simultaneous operations being determined in place of the one differential function.

Abstract: A method and device for managing a reference oscillator within a wireless device is presented. The method includes selecting reference oscillator parameters associated with the lowest reference oscillator error, where the selection is based upon reference oscillator parameters derived using different technologies within a wireless device, acquiring a satellite based upon the selected reference parameters, determining the quality of the satellite-based position fix, and updating the reference oscillator parameters based upon the quality of the satellite-based position fix.

Abstract: According to one embodiment, a register outputs a first control code in first and second operation modes, saves the first control code as a third control code at an end of the first operation mode, and outputs the third control code at a beginning of a third operation mode. In the first operation mode, a digital-to-analog converter supplies a control signal with a control voltage to a voltage controlled oscillator. In the second operation mode, the control signal is supplied to a buffer amplifier, the amplifier drives a bandlimiting filter, and the filter generates the control voltage. In the third operation mode, the control signal is supplied to the filter, and the filter generates the control voltage.

Abstract: A precise, low-consumption low-frequency oscillator includes a low-consumption low-frequency oscillator, operating at a frequency FA, a temperature-compensated oscillator B used as frequency standard, operating at a frequency FB, and a circuit for supplying a stable frequency Fcorr.

Abstract: A transmitting apparatus operative at a plurality of different bands includes at least a modulator, an intermediate frequency (IF) filter, and an offset phase-locked-loop (OPLL). Regardless at which one of the frequency bands the transmitting apparatus operates, a divisor of at least one frequency divider included within the OPLL is fixed, and a signal, which is outputted by a controllable oscillator and received by an offset mixer included within the OPLL, corresponds to a substantially fixed frequency.

Abstract: A circuit is constituted by a plurality of n-channel-type transistors, the circuit including: among the plurality of transistors, a transistor including a drain terminal for receiving a voltage of VDD, a source terminal, and a gate terminal for receiving an input signal; among the plurality of transistors, a transistor including a drain terminal for receiving the voltage of VDD, a source terminal connected to an output terminal, and a gate terminal connected to the source terminal of the transistor; and a capacitor provided between a node and a clock terminal for receiving a clock signal. In at least one embodiment, the clock signal inputted into the clock terminal has a frequency higher than that of an output signal outputted from the output terminal.

Abstract: A VCO oscillates at a frequency that corresponds to a control voltage. A frequency mixer performs frequency mixing of the output signal of the VCO and a local signal having a local frequency. A first filter extracts a difference frequency signal obtained by the mixing operation of the mixer. A phase difference detection unit makes a comparison between the phase of the difference frequency signal extracted by the first filter and the phase of a reference signal having a reference frequency, and generates a phase difference signal that corresponds to the phase difference. A loop filter performs filtering of the phase difference signal so as to generate the control signal. A second filter extracts a summation frequency signal obtained by the mixing operation of the mixer, and outputs the summation frequency signal via an output terminal thereof.

Abstract: An electronic device may include a voltage controlled oscillator (VCO) and a temperature sensor. The electronic device may also include a controller configured to cooperate with the VCO and the temperature sensor to determine both a temperature and a frequency error of the VCO for each of a plurality of most recent samples. Each of the most recent samples may have a given age associated therewith. The controller may also be configured to align the temperature, the frequency error, and the given age for each of most recent samples in a three-dimensional (3D) coordinate system having respective temperature, frequency error and age axes. The controller may also be configured to estimate a predicted frequency error of the VCO based upon the aligned temperature, frequency error, and given age of the most recent samples.

Abstract: An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency, calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency at a first calibration frequency when at a steady state temperature and at a second calibration frequency when at a transient temperature, and circuitry configured to generate an output frequency from the oscillator frequency.

Abstract: In one embodiment, the present invention includes a method of correcting the frequency of a crystal oscillator. The method includes establishing an operating baseline for the crystal oscillator using a frequency reference, storing information in memory, and adjusting the frequency according to the information. The information corresponds to the operating baseline. Adjusting the frequency occurs in response to a power-on event and the absence of the frequency reference.

Abstract: An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency source. When a primary power source is unavailable, an output frequency is generated from the oscillator frequency, and the reference frequency source is powered-on only during calibration cycles.

Abstract: A system comprises a first clock module configured to generate a first clock reference that is not corrected using automatic frequency correction (AFC). A global position system (GPS) module is configured to receive the first clock reference. An integrated circuit for a cellular transceiver includes a system phase lock loop configured to receive the first clock reference, to perform AFC, and to generate a second clock reference that is AFC corrected.

Abstract: A circuit arrangement for generation of radio frequency output signals which form a broadband frequency ramp, with a reference oscillator, a phase detector, a loop filter, a VC oscillator for generating the output signals, a frequency divider, a step-down mixer and a local oscillator for generating a local oscillator signal. The reference oscillator, the phase detector, the loop filter, the VC oscillator, the frequency divider and the step-down mixer belong to a phase-locking loop. The frequency divider and the step-down mixer are in the feedback path of the phase-locking loop. The step-down mixer mixes the output signals and the local oscillator signal. The frequency of the output signal is adjustable by varying the division ratio of the frequency divider. Characteristics of the output signal are improved using the adjustable frequency of the local oscillator signal.

Abstract: A single side band mixer is composed of standard digital logic elements and field effect transistors, forming a pair of quadrature generators coupled with a mixer-splitter circuit. This design results in a single side band mixer with a bandwidth from DC to at least 100 MHz when realized with CMOS digital logic circuitry. This design allows the single side band mixer to bring particular improvement to circuits including frequency synthesizers, quadrature demodulators and up-converters.

Abstract: An oscillation frequency control circuit configured to control a frequency of a second clock signal of an oscillation circuit generating and outputting the second clock signal having a frequency in response to an input control signal is disclosed. The oscillation frequency control circuit includes a frequency difference detection circuit unit configured to detect a difference between a frequency of a predetermined first clock signal input externally and the frequency of the second clock signal, and generate and output a signal indicating a result of the detection; and a frequency control circuit unit configured to control the frequency of the second clock signal so that the frequency of the second clock signal continually changes back and forth between a predetermined lower limit value and a predetermined upper limit value in response to the output signal from the frequency difference detection circuit.

Abstract: A system and method is disclosed that provides a technique for generating an accurate time base for MEMS sensors and actuators which has a vibrating MEMS structure. The accurate clock is generated from the MEMS oscillations and converted to the usable range by means of a frequency translation circuit.

Abstract: A device is provided having a local oscillator (LO) configured to generate a first signal comprising at least one of timing information, frequency information, phase information and combinations thereof. The device also has a LO error corrector comprising an input, the input configured to receive a second signal comprising at least one of timing information, frequency information, phase information and combinations thereof. The second signal is used for disciplining the LO. The LO error corrector is capable of disciplining the LO using a source that is less accurate than a preferred second signal, if the preferred second signal is unavailable to discipline the LO.

Abstract: A device is provided having a local oscillator (LO) configured to generate a first signal having timing information, frequency information, phase information or combinations thereof. The device also includes a prioritizer comprising at least two inputs, each input configured to receive a respective second signal having timing information, frequency information, phase information or combinations thereof. The prioritizer is configured to determine an accuracy of at least one second signal of the at least two second signals in relation to a second signal assigned to be a most accurate of the at least two second signals. The prioritizer is also configured to order the at least two second signals from most accurate to least accurate. The LO is disciplined to correct an offset error of the LO relative to a most accurate second signal that is available to the device, based on the order of the at least two second signals.

Abstract: An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency source. When a primary power source is unavailable, an output frequency is generated from the oscillator frequency, and the reference frequency source is periodically pulse powered-on to calibrate the electronic oscillator.

Abstract: A method and system for modulating logic clock oscillator frequency based on voltage supply. The system comprises a logic unit having a logic operation and a device to produce self-adjusting clocks to match the logic operation. The device is configured to use supply voltage as an independent variable to optimize device parameters for voltage variations. The invention is also directed to a design structure on which a circuit resides.

Abstract: In an ADPLL circuit, on the basis of a gain of a digitally controlled oscillator estimated when a loop gain of a certain value is set in the loop filter and on the basis of a device parameter of the digitally controlled oscillator, the DCO gain estimation unit estimates a gain of the digitally controlled oscillator when a loop gain of another value is set in the loop filter.

Abstract: A method and apparatus controlling the output phase of a VCO (Voltage Controlled Oscillator). The apparatus has a phase locked loop 20 having a first input 21 for receiving a reference signal and a second input 22 for receiving a feedback signal and the output for controlling of a VCO. A phase shifter 50 is provided on the feedback path between the VCO and the second input of the phase locked loop. The phase shifter is arranged for shifting the phase for feedback signal by controlled amount. The phase shifter may be a variable phase shifter for controlling and varying the amount by which the phase feedback signal is shifted.

Abstract: A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.

Abstract: A semiconductor integrated circuit device includes a DCO and a storing unit that stores a temperature coefficient of an oscillation frequency and an absolute value of the oscillation frequency, which should be set in the DCO, corresponding to potential obtained from a voltage source that changes with a monotonic characteristic with respect to temperature.

Abstract: In an ADPLL frequency synthesizer where a frequency control word is changed from FCW0 to FCW2, a control sensitivity estimation section firstly measures oscillatory frequencies f1L and f1H obtained, respectively, when frequency control words FCW1L and FCW1H being used as dummies are set, and then measures an oscillatory frequency f2 obtained when a frequency control word FCW2 is set. Thereafter, based on values of the oscillatory frequencies f1L, f1H and f2, the control sensitivity estimation section calculates a control sensitivity KDCO2 obtained when the frequency control word FCW2 is set. Based on a value of the control sensitivity KDCO2, the loop filter determines values of filter coefficients ?2 and ?2 so as to be equal to a natural frequency ?n and a damping factor ?, respectively, both of which have been previously designed.

Abstract: A device is provided having a local oscillator (LO) configured to generate a first signal comprising at least one of: timing information; frequency information; phase information; and combinations thereof. The device also has a LO error corrector comprising an input, the input configured to receive a second signal comprising at least one of: timing information; frequency information; phase information and combinations thereof, wherein the second signal is used for disciplining the LO. The LO error corrector is configured to: if the second signal is unavailable to discipline the LO, discipline the LO using a source that is less accurate than the second signal. Upon the second signal becoming at least temporarily available, the LO corrector determines an offset error of the LO relative to the second signal.

Abstract: In some embodiments, a feedback loop circuit includes a phase detector, first and second charge pumps that are each coupled to receive an output signal of the phase detector, a first low pass filter, a second low pass filter coupled to an output of the second charge pump, a clock signal generation circuit having first and second control inputs, a first switch circuit coupled between the first low pass filter and the second low pass filter, and a second switch circuit coupled to the first low pass filter and the first control input of the clock signal generation circuit.

Abstract: A circuit is provided for use with a clock having an input divider portion, a feedback divider portion, a phase detector portion, a loop compensation filter portion and a voltage controlled oscillator portion. The input divider portion receives a reference signal and outputs a divided reference signal. The feedback divider portion receives an output signal from the circuit and outputs a divided feedback signal. The phase detector portion outputs a phase detector signal based on the divided reference signal and the divided feedback signal. The loop compensation filter portion outputs a tuning signal based on the phase detector signal. The voltage controlled oscillator portion output the outputs a signal based on the tuning signal. The phase detector portion changes the phase detector signal based on the input divider portion receiving the control signal and the feedback divider portion receiving the control signal.

Abstract: Provided are a multi-output oscillator using a single oscillator, and a method of generating multiple outputs. The multi-output oscillator includes: an oscillator outputting the single frequency; a multiplier multiplying the single frequency to output a first frequency; a first frequency divider dividing the single frequency by a first division factor; a first mixer outputting a second frequency by mixing an output of the first frequency divider and an output of the multiplier; a second frequency divider dividing the single frequency by a second division factor; a second mixer mixing the output of the second frequency divider and the output of the first mixer to output a third frequency; and a third mixer mixing the output of the second frequency divider and the output of the multiplier to output a fourth frequency.

Abstract: A device is provided having a local oscillator (LO) configured to generate a first signal having timing information, frequency information, phase information or combinations thereof. The device also includes a prioritizer comprising at least two inputs, each input configured to receive a respective second signal having timing information, frequency information, phase information or combinations thereof. The prioritizer is configured to determine an accuracy of at least one second signal of the at least two second signals in relation to a second signal assigned to be a most accurate of the at least two second signals. The prioritizer is also configured to order the at least two second signals from most accurate to least accurate. The LO is disciplined to correct an offset error of the LO relative to a most accurate second signal that is available to the device, based on the order of the at least two second signals.

Abstract: A frequency plan is provided for particular use in a transceiver. Advantageously, a single oscillator may be used to generate desired frequency signals. One or more power splitters receive the signal and equally divide the signal into first and second signals having a frequency substantially equal to the original. Multipliers on each arm of the transceiver receive a signal and increase the frequency of the signal. In one exemplary embodiment, multiple signals having different frequencies may be transmitted over the same cable due in part to the generated frequency separation between the signals. In another exemplary embodiment, multiple signals may be transmitted over multiple cables. In another exemplary embodiment, the frequency plan may self correct a transmit signal based on a reference signal, such as the receive signal. Additionally, multiple signals over one or more cables may be transmitted at or below 3 GHz.

Abstract: A frequency plan is provided for particular use in a transceiver. Advantageously, a single oscillator may be used to generate desired frequency signals. One or more power splitters receive the signal and equally divide the signal into first and second signals having a frequency substantially equal to the original. Multipliers on each arm of the transceiver receive a signal and increase the frequency of the signal. In one exemplary embodiment, multiple signals having different frequencies may be transmitted over the same cable due in part to the generated frequency separation between the signals. In another exemplary embodiment, multiple signals may be transmitted over multiple cables. Additionally, multiple signals over one or more cables may be transmitted at or below 3 GHz.

Abstract: A phase synchronization circuit comprising: a charging/discharging-circuit to charge/discharge a capacitor in accordance with a drive-signal, charging and/or discharging current-values of the capacitor being settable; an oscillation-circuit to output an oscillation-signal having a frequency corresponding to a charging-voltage; a drive-circuit to output as the drive-signal a first drive-signal for matching charging and discharging periods when a phase-difference and the oscillation-signal is smaller than a predetermined phase-difference and reducing the phase-difference when the phase-difference is greater than the predetermined phase-difference; and a setting-circuit to receive setting-data for setting the charging and/or discharging current-values, hold the setting-data, and set the charging and/or discharging current-values, based on the setting-data, the drive-circuit outputting as the drive-signal a second drive-signal for matching charging and discharging periods, when receiving an adjustment-instruction

Abstract: An apparatus for on-demand power management including a system controller, a clock domain manager coupled to the system controller and a power distribution manager coupled to the system controller. The system controller monitors a processing demand in a processing system. The clock domain manager provides one or more clock frequencies and, in response to the processing demand, switches between a first set of clock frequencies and a second set of clock frequencies without halting the processing system. The power distribution manager provides one or more operating voltages and, in response to the processing demand, switches between a first set of voltages and a second set of voltages without halting the processing system.

Abstract: A system replaces the current “Genlock” reference signals and distribution architectures used in media and broadcasting use an IP network and distributed timekeeping service, such as ISO/IEC 61588 or IEEE1588. In such a system, a master and multiple slave devices are used to distribute precision time and phase information to synchronize equipment and systems. The method described herein allows the generation of a signal standard and format with a single distribution system. In addition, the method allows this distribution to be accomplished over an IP network despite the non-deterministic performance of such networks. The method also allows the deterministic generation of signals at slave devices.

Abstract: Apparatuses, methods, systems, algorithms, and circuits for reference clock frequency determination are disclosed. In one embodiment, a circuit for detecting a reference clock frequency can include a clock counter configured to count a number of cycles of the reference clock over a predetermined portion of a sleep clock to provide a reference clock cycle count, where the sleep clock has a known frequency and a predetermined accuracy; a frequency estimator configured to estimate the reference clock frequency from the reference clock cycle count and the known frequency of the sleep clock; and a frequency selector configured to select a closest frequency to the estimated reference clock frequency from a plurality of allowed frequencies.

Abstract: In an embodiment, a circuit comprising an oscillator is provided. The oscillator is controlled based on a feedback value and an input reference value. The feedback value or the reference value or both are generated using noise shaping.

Abstract: A local oscillator includes a phase-locked loop. The phase-locked loop includes voltage controlled oscillator (VCO) and a novel VCO control circuit. The VCO control circuit may be programmable and configurable. In one example, an instruction is received onto the VCO control circuit to change the power state of the VCO. The instruction is issued by other circuitry in response to a detected change in RF channel conditions (for example, a change in a signal-to-noise determination) in a cellular telephone. In response, the VCO control circuit outputs control signals that gradually widen the loop bandwidth of the PLL, then gradually change the VCO bias current to change the VCO power state, and then narrow the loop bandwidth of the PLL back to its original bandwidth. The entire process of widening the PLL bandwidth, changing the VCO power state, and narrowing the PLL bandwidth occurs while the PLL remains locked.

Abstract: Disclosed herein are techniques, systems, and methods relating to compensation of phase disturbances of a phase lock-loop during power ramp up or down of a power amplifier. More specifically, a phase lock-loop is described that is able to switch between type I and type II PLL modes depending on the power state of the power amplifier without introducing additional disturbances.

Abstract: A phase-locked loop has a stable high frequency reference oscillator to provide a stable high frequency reference signal that has reference frequency that is a small submultiple of a generated frequency of a voltage controlled oscillator within the phase-locked loop. An adjustable output frequency feedback circuit has with a feedback divide ratio that is approximately the small submultiple and adjusts the feedback ratio such that the generated frequency of the voltage controlled oscillator is locked to a stable low frequency reference input signal. The feedback divide ratio is adjusted as a function of a required ratio change value that is a function of a current phase error of the generated frequency of a voltage controlled oscillator and the stable low frequency reference input signal and a phase error derivative. The phase error derivative is a difference of the current phase error and a previous phase error.

Abstract: To provide a highly stable oscillation frequency control circuit wherein the frequency thereof is corrected, an adequate range of the input levels of external reference signals is determined in accordance with temperature characteristics in detecting the external reference signal, and the control voltage to a VCO is controlled within and outside the adequate range. An oscillation frequency control circuit includes a selection switch that connects the phase comparator to the loop filter in an external reference synchronization mode and that connects the fixed voltage supplying circuit to the loop filter in a fixed voltage mode, and a CPU that switches the selection switch to the external reference synchronization mode or to the fixed voltage mode based on whether the detected voltage of an external reference signal level is within or outside of the adequate range.

Abstract: A frequency synthesizer is built using a phase locked loop incorporating a single side band mixer in the input. The single side band mixer is preferably realized with digital logic and FETs, and the resulting frequency synthesizer simultaneously improves control over the frequency resolution, noise floor and operating frequency range.

Abstract: An oscillation tuning circuit is provided and includes a first circuit. The first circuit receives an input data stream with a known time interval, producing a first output signal having a first period, determines a first error signal representing a difference between the known time interval and a measured duration of the known time interval, determines a reference error signal according to a predetermined multiple of the first period, and adjusts the first period according to the first error signal and the reference error signal, wherein the known time interval is associated with a period between a first occurrence of and a second occurrence of a predetermined bit pattern in the input data stream.

Abstract: A rubidium oscillator or a cesium oscillator is used as a high stability oscillator, and an OCXO being a metastable oscillator which is inferior in a long-term frequency stability compared with the above oscillators but has a high short-term frequency stability is used as a backup. There is prepared a table in which an elapsed time since an occurrence of an abnormality in the high stability oscillator and weighting (use ratio) of use of the both oscillators is corresponded, and by using this table, after the high stability oscillator recovers, an oscillation frequency of the metastable oscillator is used by 100% initially, but thereafter the weighting (use ratio) of use of the metastable oscillator is made smaller and the use ratio of the high stability oscillator is made larger in stages.

Abstract: A technique and corresponding circuitry are presented for a process independent, self-calibrating relaxation based clock source. The technique and circuitry presented here can reduce the time and cost needed for calibration significantly. The relaxation based clock source produces a clock signal whose frequency is dependent upon a trim value. Starting from an initial trim value, the clock signal is generated, its frequency is compared with a reference clock frequency value, and the trim value is correspondingly adjusted up or down a bit at a time. After this process has continued for a while, min-max logic is used to determine the maximum and minimum trim values and, based on these, the final trim value for the clock is set. This calibration process can also be used to extract whether, and by how much, the implementation on silicon of a particular chip lies in the fast or slow process corners.

Abstract: An oscillator circuit including a charge/discharge unit, a capacitance amplifier, and a level detection circuit is provided. The charge/discharge unit is used to receive a control signal, and perform a charge or discharge operation on a charge/discharge terminal according to the control signal. The capacitance amplifier, including a first impedance, a second impedance, a voltage follower, and a capacitor, is capable of providing an equivalent capacitance with amplifying characteristics. An input terminal of the level detection circuit is electrically connected to the charge/discharge terminal of the charge/discharge unit, and the level detection circuit generates the control signal to the charge/discharge unit according to the charge/discharge terminal of the charge/discharge unit. The oscillator circuit of the present invention may use a capacitance with a smaller level to provide an equivalent capacitance with amplifying characteristics, and thus achieve an oscillator function.

Abstract: A synchronizing apparatus, which controls, by a PLL circuit, a sampling clock to be used to sample input data and synchronizes a phase of the sampling clock with a target phase that is desirable for sampling the input data, includes: phase error detection means for detecting a phase error from sampling data and the sampling clock, the sampling data being sampled from the input data at timing of the sampling clock; frequency error detection means for detecting, based on a differential coefficient obtained as a result of detecting the phase error, a frequency error; and frequency correction means for correcting a frequency of the sampling clock such that the detected frequency error becomes close to zero by adding a frequency correction value to an integral term of a loop filter of the PLL circuit, the frequency correction value being calculated based on the frequency error.