Plural Channel Systems Patents (Class 333/1)
  • Publication number: 20030132812
    Abstract: What is described here is an arrangement for broadband signal or energy transmission between at least two units mobile relative to each other along an optional trajectory, consisting of a first unit comprising a symmetric open conductor structure consisting of a plurality of dummy elements that are terminated in a reflection-free manner on both ends, as well as at least one second unit that includes a coupling unit for coupling or decoupling electrical signals.
    Type: Application
    Filed: November 4, 2002
    Publication date: July 17, 2003
    Inventor: Georg Lohr
  • Patent number: 6590466
    Abstract: A flexible circuit board with specific shielding planes is used for low voltage differential transmission mode circuits. Both the impedance and the transmission time for the transmission line in the circuit board are controlled by shielding planes with varied void opening patterns. Capacitance and slow wave effects related to the combination of void opening patterns and the location configuration related to locations of void opening patterns are used to improve the impedance and transmission timing for the transmission line in the circuit board.
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: July 8, 2003
    Assignee: Advanced Flexible Circuit Co., Ltd.
    Inventors: Gwun-Jin Lin, Chi-Kuang Hwang, Ching-Cheng Tien
  • Publication number: 20030112091
    Abstract: A novel backplane interconnection system that is useful in the telecommunication and data process industries for ultra high speed backplane systems. It is capable of transmitting digital signals with bandwidths of 10 GHz and beyond. The invention provides high performance at a low cost of manufacture. It is suitable for use in a wide variety of system applications.
    Type: Application
    Filed: October 17, 2002
    Publication date: June 19, 2003
    Inventors: Timothy A. Lemke, Richard A. Elco
  • Publication number: 20030112087
    Abstract: A low cross talk compensation circuit comprising a first signal pair having a first conductor and a second conductor parallel to the first conductor, and a second signal pair having a third conductor and a fourth conductor parallel to the third conductor, wherein each conductor is attached to a corresponding input signal. A first compensation line attached to the first input signal and a second compensation line attached to the third input signal are intertwined forming a first compensation line assembly with capacitive and inductive coupling parallel to and flanked by the second and third conductors. A third compensation line attached to the fourth input signal and a fourth compensation line attached to the second input signal are intertwined forming a second compensation line assembly with capacitive and inductive coupling parallel to and adjacent to the second conductor.
    Type: Application
    Filed: December 14, 2001
    Publication date: June 19, 2003
    Inventor: Hung Thai Nguyen
  • Patent number: 6566974
    Abstract: A noise reduction impedance element connection structure includes first and second noise-reduction impedance elements which are electrically connected to a transmission path. A noise frequency that exceeds a predetermined limit when the first noise-reduction impedance element is connected is measured or calculated by simulation to find the current peak. The second noise-reduction impedance element is connected at a location corresponding to the current peak. Therefore, this structure provides high noise suppression performance.
    Type: Grant
    Filed: September 17, 2001
    Date of Patent: May 20, 2003
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Toshiro Tsubouchi
  • Patent number: 6559377
    Abstract: A flexible printed circuitry member includes an elongated flexible insulating substrate with a plurality of signal conductors extending longitudinally along one side of the substrate. A grounding grid having a substantially random geometric pattern is disposed on the opposite side of the substrate.
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: May 6, 2003
    Assignee: Molex Incorporated
    Inventors: Atsuhito Noda, Shigeyuki Hoshikawa, Shigeru Ando
  • Patent number: 6522214
    Abstract: The invention relates to an electrical transmission arrangement comprising a first strip-line conductor which has its main extension in a first direction in a first plane in the transmission arrangement and comprises a conductor, an upper ground plane which is situated at an upper distance from the conductor and a lower ground plane which is situated at a lower distance from the conductor, and a second strip-line conductor which has its main extension in a second direction in a second plane in the transmission arrangement and comprises a conductor, an upper ground plane which is situated at an upper distance from the conductor and a lower ground plane which is situated at a lower distance from the conductor, where the ground planes are separated from their respective conductors and from one another by a dielectric material, in which transmission arrangement the lower ground plane of the first strip-line conductors coincides with the upper ground plane of the second strip-line conductors at at least one point.
    Type: Grant
    Filed: June 19, 2000
    Date of Patent: February 18, 2003
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Thomas Harju, Björn Albinsson
  • Patent number: 6522173
    Abstract: An electronic device includes a wiring board, and at least one pair of signal lines that is provided on the wiring board in parallel and has an equal length. A chip is mounted on the wiring board and includes at least one differential driver which outputs complementary digital transmit signals to said at least one of lines. A pair of power system lines is provided to supply first and second power supply voltages to the above-mentioned at least one differential driver. The power system lines are parallel to each other and have an equal length.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: February 18, 2003
    Assignees: Fujitsu Limited, Oki Electric Industry Co., Ltd., Sanyo Electric Co., Ltd., Sharp Kabushiki Kaisha, Sony Corporation, Kabushiki Kaisha Toshiba, NEC Corporation, Hitachi, Ltd., Matsushita Electronics Corporation, Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kanji Otsuka
  • Patent number: 6512423
    Abstract: A printed board having a structure for equalizing propagation times on transmission lines connecting the same pair of circuit elements at several terminals. The structure controls each propagation delay by connecting each transmission line partially in different dielectric layers having different dielectric constants in a multi-layered printed board regardless of a distance between the terminals to be connected.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: January 28, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yuichi Koga
  • Publication number: 20030007221
    Abstract: A device, system and method for measuring the one-way velocity of light using selective transmission technology to provide a superluminal energy flow is provided. The superluminal transmitter comprises a transmission source, a receiver, and a selective-transmission device for receiving the transmission wavepacket from the transmission source and selectively transmitting the high-energy or wavefront component of the transmission wavepacket through a barrier such that the energy transmission tunnels through the barrier at superluminal velocities. The measured daily oscillation of the tunnel time can then be utilized to measure the one way light velocity. A system and method for measuring the vector velocity of light using the superluminal transmitter system of the invention is also provided as well as a method of calibrating temporal data and a device which can be utilized as a speedometer, a compass, a calender and/or a clock.
    Type: Application
    Filed: May 23, 2001
    Publication date: January 9, 2003
    Inventor: George A. Soli
  • Publication number: 20020175775
    Abstract: A microwave circuit utilizes a spiral-like coupler configuration to achieve the functionality of a traditional coupler with higher density and lower volume. A plurality of substrate layers having metal layers disposed on them are bonded to form the package. A plurality of groundplanes may be used to isolate the spiral-like shape from lines extending out to contact pads or other circuitry.
    Type: Application
    Filed: April 1, 2002
    Publication date: November 28, 2002
    Inventors: Rocco A. De Lillo, Joseph McAndrew
  • Publication number: 20020171505
    Abstract: The present invention is related to the modular plug housing insert device that makes electrical contact to a telecommunication plug to complete an interface media connection. The positional relationship of the conductors in the modular plug housing insert device are arranged to from capacitance, such that the Near-end Crosstalk (NEXT) and Far End Crosstalk (FEXT) is reduced without compromising impedance.
    Type: Application
    Filed: October 17, 2001
    Publication date: November 21, 2002
    Inventors: Robert A. Aekins, George M. Kessler, Jay Venditti, Joseph E. Dupuis
  • Publication number: 20020130728
    Abstract: An electrical connector includes a first connector having first contacts; and a second connector having second contacts which are brought into contact with the first contacts when the second connector is fitted to the first connector, wherein an outer conductor, which is formed to nearly entirely surround all the first contacts and the second contacts when the first connector and the second connector are fitted to each other, is held in at lease either of the first connector and the second connector; and wherein one or more shielding conductors, which cooperate with the outer conductor to nearly entirely surround each of the first and second contacts and are held equal in potential to the outer conductor, when the first connector and the second connector are fitted to each other, are held in at least either of the first connector and the second connector.
    Type: Application
    Filed: February 28, 2002
    Publication date: September 19, 2002
    Inventors: Hiroaki Kukita, Hirofumi Yamagata
  • Publication number: 20020125967
    Abstract: An air dielectric backplane interconnection system is disclosed. The interconnection system disclosed is a high speed backplane interconnection system having a plurality of conductor matched impedance transmission line elements and an air dielectric surrounding the plurality of transmission line elements. An interconnection system also having spacers disposed between the transmission line elements and a ground plate is disclosed.
    Type: Application
    Filed: November 2, 2001
    Publication date: September 12, 2002
    Inventors: Richard H. Garrett, Richard A. Elco, Timothy A. Lemke
  • Patent number: 6448640
    Abstract: The present invention relates to chip assembly with a ball array capacitance minimizing layout that includes a ball array disposed upon a substrate with trace routing laid out between each ball pad and a respective bond wire pad. After routing of both signal and ground traces between the ball pads and their respective bond wire pads, at least one buffer trace is also disposed upon the substrate as a closed loop. The buffer trace may or may not be connected to ground. Preferably, buffer traces are configured to reduce the capacitance of the highest capacitance ball pads. This is accomplished by placing more of a give buffer trace around the perimeter of a higher capacitance ball pad, than around the perimeter of a lower capacitance ball pad. Accordingly, a capacitance difference between a higher capacitance ball pad and signal trace and a lower capacitance ball pad and signal trace can be minimized according to the present invention.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: September 10, 2002
    Assignee: Micron Technology, Inc.
    Inventor: David J. Corisis
  • Patent number: 6433648
    Abstract: A structure and a method for reducing the mutual inductance between two adjacent transmission lines according to the invention. In the invention, an inverse U-shaped transmission line is located on one side of a transmission line. The corner of a first side of the inverse U-shaped transmission line is bond finger for signal input; the corner of a second side of the inverse U-shaped transmission line is connected to via for signal output. To prevent antenna effect, corners of the inverse U-shaped transmission line are mitered. Furthermore, using computer simulation software, the lengths of the first and second sides of the inverse U-shaped transmission line and the pitches between the first and second sides and the selected transmission line can be adjusted to effectively reduce the mutual inductance therebetween. As a result, cross-talk caused by the mutual inductance can also be eliminated.
    Type: Grant
    Filed: April 4, 2000
    Date of Patent: August 13, 2002
    Assignee: Via Technologies, Inc.
    Inventor: Chun-Ho Daniel Lee
  • Patent number: 6429749
    Abstract: The invention is a cancellation circuit that suppresses electromagnetic interference in a high speed circuit, which achieves the objects of canceling the magnetic field and coupling the electric field through a differential signal under the premise of not affecting the signal quality. The differential signal is generated from the original high speed circuit using a phase shifter. Suitable phase shifters include a same-layer type, a meander type and a different-layer stacking type.
    Type: Grant
    Filed: November 8, 2000
    Date of Patent: August 6, 2002
    Assignee: Mitac International Corp.
    Inventor: Yu-Chiang Cheng
  • Publication number: 20020084876
    Abstract: A circuit in a printed circuit board includes a trace and a ground plane coupled to the trace that includes slots in the vicinity of the trace. The slots are dimensioned and arrayed such that the trace has a controlled impedance. An array of slots progressing in a direction parallel to the trace preferably includes repeating subarrays displaced by a repeat distance in a direction parallel to the trace that is less than a characteristic wavelength of a signal propagated on the trace, coupling distributively with the trace. The slots may be polygonal, arcuate, or a combination of both in shape. The printed circuit board may include a second trace coupled to the first. Further, the printed circuit board may include a second ground plane that includes slots that couple to the trace.
    Type: Application
    Filed: December 29, 2000
    Publication date: July 4, 2002
    Inventors: Mitchel E. Wright, Joseph Stoddard
  • Publication number: 20020050870
    Abstract: A printed board having a structure for equalizing propagation times on transmission lines connecting the same pair of circuit elements at several terminals. The structure controls each propagation delay by connecting each transmission line partially in different dielectric layers having different dielectric constants in a multi-layered printed board regardless of a distance between the terminals to be connected.
    Type: Application
    Filed: September 27, 2001
    Publication date: May 2, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yuichi Koga
  • Patent number: 6380818
    Abstract: A structure for reducing the mutual inductance between two adjacent transmission lines on a substrate according to the invention includes a loop-shaped transmission line, at least one transmission line located on each side of the loop-shaped transmission line. One end of the loop-shaped transmission line is connected to bond wire and a diagonal end is connected to a signal output on the substrate. The loop-shaped transmission line has a short side equal to ½ of the wavelength of an input signal. With such structure, even though the clock frequency of a used CPU is several hundred MHz, the mutual inductance and cross-talk caused by the mutual inductance can be effectively reduced.
    Type: Grant
    Filed: April 4, 2000
    Date of Patent: April 30, 2002
    Assignee: Via Technologies, Inc.
    Inventor: Chun-Ho Daniel Lee
  • Publication number: 20020047751
    Abstract: Electrodes are formed on both top and bottom surfaces of a dielectric plate and grounded coplanar lines, as transmission lines, are formed on the top surface of the dielectric plate. A plurality of micro-strip lines, each composed of high-impedance lines and low-impedance lines alternately connected in series, is arranged at a pitch shorter than the wavelength of a wave traveling along the grounded coplanar lines. A spurious mode propagation blocking circuit thus constructed prevents a spurious mode wave, such as a parallel-plate mode, from traveling.
    Type: Application
    Filed: September 26, 2001
    Publication date: April 25, 2002
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yohei Ishikawa, Kenichi Iio, Takatoshi Kato, Koichi Sakamoto
  • Publication number: 20020017963
    Abstract: Transmission line structure is composed of a pair of signal conductors which are embedded in one wiring region of a dielectric layer and a thickness in height of the signal conductor is larger than a width, and is constituted so that a coupling impedance between the adjacent signal conductors is lower than a coupling impedance between the signal conductor and another conductor formed in another wiring region, and thus to provide a multi-layer wiring board having a transmission line structure of high wiring density and excellent transmission characteristic.
    Type: Application
    Filed: July 3, 2001
    Publication date: February 14, 2002
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., Ltd.
    Inventors: Takeshi Shimamoto, Kazufumi Yamaguchi, Masahide Tsukamoto, Fumikazu Tateishii, Yutaka Taguchi
  • Patent number: 6342823
    Abstract: A method and system for reducing the computation complexity and improving accuracy of delay and crosstalk calculation in transmission-lines with frequency-dependent losses. An analysis tool based on restricted coupled-line topologies, simple two-dimensional to three-dimensional RLC matrix conversion, and use of prestored synthesized circuits that accurately capture frequency-dependent loss effects. The CAD tool can handle frequency-dependent resistive and inductive effects for coupled-interconnections on large microprocessor chips with >10K of critical nets. This is done in an interactive manner during the design cycle and allows first path fast product design.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: January 29, 2002
    Assignee: International Business Machines Corp.
    Inventors: Allan Harvey Dansky, Alina Deutsch, Gerard Vincent Kopcsay, Phillip John Restle, Howard Harold Smith
  • Patent number: 6307445
    Abstract: The invention relates to a circuit arrangement for forming an impedance match of transmission lines. The circuit arrangement includes a control state (11), a dynamic input impedance formed by resistances and a transformer (13) provided with primary and secondary coils. The control stage (11) and the input impedance are connected to the poles of the transformer's (13) secondary coil, and transmission lines having mutually different characteristic impedances are connected one at a time to the poles of the transformer's (13) primary coil. According to the invention, the circuit arrangement is characterised in that for forming a resistive input impedance the circuit arrangement includes a processor (15) and means (14) for implementing the match.
    Type: Grant
    Filed: January 6, 2000
    Date of Patent: October 23, 2001
    Assignee: Nokia Networks Oy
    Inventors: Olli-Pekka Mäkinen, Jouni Pyyhkälä, Timo Pasanen
  • Patent number: 6300846
    Abstract: A flexible circuit member includes first and second pseudo-twisted flexible conductors on a flexible dielectric substrate. The first pseudo-twisted conductor is on a first side of the substrate and the second pseudo-twisted conductor is on a second side of the substrate. Each pseudo-twisted conductor includes a periodic pattern with the first pseudo-twisted conductor being shifted longitudinally relative to the second pseudo-twisted conductor by one half of a period of the periodic pattern. A set of first and second additional conductors are also provided on the dielectric substrate. The first additional conductor is on the first side of the substrate and is spaced from and generally follows the shape of the first pseudo-twisted conductor. The second additional conductor is on the second side of the substrate and is spaced from and generally follows the shape of the second pseudo-twisted conductor.
    Type: Grant
    Filed: March 18, 1999
    Date of Patent: October 9, 2001
    Assignee: Molex Incorporated
    Inventor: David L. Brunker
  • Patent number: 6270381
    Abstract: Both differential mode-to-differential mode crosstalk compensation and differential-to-common (or common mode-to-differential mode) crosstalk compensation are realized by using a pattern of conductor crossovers in a multi-pair electrical connector dictated by the algorithm (a−b)n with n≧3, where n determines the number of compensating stages and the coefficients of the expanded algorithm in each stage. An electrical connector with a pattern of conductors fashioned with these constraints among several of the pairs of conductors.
    Type: Grant
    Filed: July 7, 2000
    Date of Patent: August 7, 2001
    Assignee: Avaya Technology Corp.
    Inventors: Luc Walter Adriaenssens, Amid Ihsan Hashim, Wayne David Larsen, Bryan Scott Moffitt
  • Patent number: 6249047
    Abstract: The present invention relates to a ball array capacitance minimizing layout that includes a ball array disposed upon a substrate with trace routing laid out between each ball pad and a respective bond wire pad. After routing of both signal and ground traces between the ball pads and their respective bond wire pads, at least one buffer trace is also disposed upon the substrate as a closed loop. The buffer trace may or may not be connected to ground. Preferably, buffer traces are configured to reduce the capacitance of the highest capacitance ball pads. This is accomplished by placing more of a give buffer trace around the perimeter of a higher capacitance ball pad, that around the perimeter of a lower capacitance ball pad. Accordingly, a capacitance difference between a higher capacitance ball pad and signal trace and a lower capacitance ball pad and signal trace can be minimized according to the present invention.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: June 19, 2001
    Assignee: Micron Technology, Inc.
    Inventor: David J. Corisis
  • Patent number: 6205138
    Abstract: This invention is a broadband matrix switch system and method of operation. The broadband matrix switch has N number of broadband inputs, each of the broadband inputs having one or more broadband signals. The matrix switch has M number of broadband outputs. There are N number of splitters. Each of the splitters has a splitter input connected to one of the broadband inputs. Each of the splitters has M number of splitter outputs that produce the splitter output signal. There are N times M number of node switches. Each node switch is uniquely connected to one of the splitter outputs. The node switches have a control input that allows the node switch to pass the respective splitter output signal upon receiving a close command at the control input and to terminate the respective splitter output signal with an input impedance upon receiving an open command at the control input. There are M number of combiners. Each combiner has a combiner output connected to one of the broadband outputs.
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: March 20, 2001
    Assignee: International Business Machines Corporation
    Inventors: Perwaiz Nihal, Robert Alan Flavin, Thompson Baum Vesecky, Norbert George Vogl, Edward Payson Clarke, Jr., Luis Rodriguez-Cortes, Geoffrey Hale Purdy
  • Patent number: 6184736
    Abstract: A clock generation system generates and distributes sinusoidal signals. Also, the clock lines are configured and shielded in a novel manner so as to provide the same overall propagation characteristics for the clock signals in all the lines, and to minimize the effects of cross-talk and electromagnetic interference.
    Type: Grant
    Filed: May 20, 1999
    Date of Patent: February 6, 2001
    Assignee: Compaq Computer Corporation
    Inventors: Daniel Wissell, Paul A. Galloway
  • Patent number: 6163233
    Abstract: A waveguide structure and a method of forming a waveguide structure is disclosed. The waveguide structure includes at least three dielectric layers juxtapositioned together such that two layers are positioned as outer layers. At least two intermediate signal path layers are positioned between respective dielectric layers. The outer dielectric layers each include a ground layer to form opposing ground planes. A controlled impedance signal track is formed at each intermediate signal path layer and a plurality of conductive vias interconnect the ground planes.
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: December 19, 2000
    Assignee: Harris Corporation
    Inventor: Calvin L. Adkins
  • Patent number: 6131269
    Abstract: A circuit module construction and method for its fabrication, in which radio-frequency (RF) or millimeter-wave circuit components (10) are electromagnetically isolated in a circuit module (12), to allow for location of multiple circuit components in close proximity without concern for signal loss or interference between components. Multiple RF or millimeter-wave circuit components (10) are installed on a dielectric substrate (14) and are separated by at least one metal isolation wall (20), which extends in depth all the way through the dielectric substrate (14) to a metal layer (16) formed under the substrate. Each isolation wall (20) is formed by first cutting a channel through the dielectric substrate (14), preferably using a laser that selectively removes the dielectric material but not the metal layer (16). Then the channel is filled with metal by electroplating, to provide continuous electromagnetic isolation in a lateral direction, parallel to the plane of the substrate (14).
    Type: Grant
    Filed: May 18, 1998
    Date of Patent: October 17, 2000
    Assignee: TRW Inc.
    Inventors: Alfred E. Lee, Steven S. Chan
  • Patent number: 6133805
    Abstract: An apparatus for propagating high frequency energy hag a wavelength of .lambda. in a dielectric medium has first and second signal lines, substantially coplanar with each other, and carrying high frequency energy, A ground trace separates the signal lines and has a plurality of vias, each spaced a distance greater than one quarter .lambda. and less than one half .lambda. apart from another one of the vias.
    Type: Grant
    Filed: May 1, 1998
    Date of Patent: October 17, 2000
    Assignee: The Whitaker Corporation
    Inventors: Nitin Jain, John Stephen Atherton, Paul John Schwab, Graham J. H. Wells
  • Patent number: 6130585
    Abstract: A stripline cross-over architecture includes a first stripline layer extending on a first side of a dielectric layer between a first signal input port and a plurality of first signal output ports. A second stripline layer extends on a second side of the dielectric layer between a second signal input port and a plurality of second signal output ports, crossing over the first stripline layer at a plurality of cross-overs of mutual overlap therebetween. The electrical lengths of the stripline layers are defined and the cross-overs are located such that electrical distances between the cross-overs and signal combination locations cause cross-coupled signals to cancel one another, when non cross-coupled signals are combined in phase.
    Type: Grant
    Filed: January 22, 1998
    Date of Patent: October 10, 2000
    Assignee: Harris Corporation
    Inventors: Walter M. Whybrew, Jeffery C. May, Douglas E. Heckaman
  • Patent number: 6111205
    Abstract: A connector for coupling high frequency signals between devices includes a substrate having an array of vias for coupling a reference voltage to reference voltage traces that extend along the substrate surface between the devices. Signal traces including device pads for coupling signals to and from the devices alternate with the reference voltage traces. The widths of the reference voltage traces are varied to maintain a substantially constant separation between the reference voltage trace and an adjacent signal trace.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: August 29, 2000
    Assignee: Intel Corporation
    Inventors: Michael Leddige, John Sprietsma
  • Patent number: 6111237
    Abstract: The present invention relates to an Atmospheric Energy Projection System for projecting electrical and thermal energy. The Microwave Facilitated Atmospheric Energy Projection System (MFAEPS) uses microwave energy at the resonant frequency or frequencies of oxygen and/or water to heat the atmosphere. This improves the potential conductivity of the air in the path of the microwave beam by heating the oxygen and water molecules in the air providing a favored pathway for breakdown. A voltage pulse generator discharges through an electrode positioned near the center of the microwave beam's recent path and creates an ionizing wave that follows the microwave beam's recent path. Alternatively, a laser can substitute for the electrode and project a high powered beam that is focused to create breakdown and thus create the ionizing pulse that travels down the favored pathway. The system can operate in an underwater environment operating at the resonant frequency of water.
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: August 29, 2000
    Assignee: Cerberus Institute for Research and Development, Inc.
    Inventor: Philip J. Paustian
  • Patent number: 6107578
    Abstract: Disclosed is a device for reducing crosstalk in an electrical connector. The device includes an insulating board with a plurality of layers. A first plurality of pairs of conductive paths is formed on a surface of at least one layer, and a second plurality of pairs of conductive paths is vertically spaced therefrom. The paths are arranged so that at least one conductive path in the first plurality of pairs overlies at least two conductive paths from different pairs in the second plurality of pairs. The capacitive coupling between the paths results in crosstalk having a polarity opposite to that of the connector so as to compensate for the connector crosstalk.
    Type: Grant
    Filed: January 16, 1997
    Date of Patent: August 22, 2000
    Assignee: Lucent Technologies Inc.
    Inventor: Amid Ihsan Hashim
  • Patent number: 6097260
    Abstract: A distributed ground pad-based isolation arrangement for a multilayer stripline architecture is configured to effectively inhibit the mutual coupling of signals between overlapping regions of adjacent stripline networks of dielectrically separated transmission networks, without substantially increasing either the mass of the laminate structure or the lossiness of the stripline. At regions of mutual overlap, the stripline layers are spatially oriented at right angles to one another, and a limited area ground pad is interleaved between the stripline layers. To maintain the desired characteristic line impedance of a stripline layer as it passes over a ground pad, the width of the stripline layer is reduced in the overlap region. Each ground pad is connected to an external ground reference by plated vias, that extend through the dielectric layers and intersect outer grounded shielding layers of the laminate.
    Type: Grant
    Filed: January 22, 1998
    Date of Patent: August 1, 2000
    Assignee: Harris Corporation
    Inventors: Walter M. Whybrew, Jeffery C. May, Douglas E. Heckaman
  • Patent number: 6072375
    Abstract: A waveguide structure and associated method for forming the waveguide structure is disclosed. The waveguide structure is formed from at least two dielectric layers having opposing, substantially planar faces and an intermediate signal path layer positioned between the faces. A conductive layer is formed on each of the opposing, substantially planar faces to form outer ground planes. At least one controlled impedance signal track is formed at the intermediate signal path layer. A plurality of conductive vias extend through the dielectric layers and interconnect the ground planes. The vias form a "sea" of vias, which provide enhanced waveguide mode rejection. A plurality of grounding lines interconnect the vias at the intermediate signal path layer. A conductive via is connected to all adjacent conductive vias outside the controlled impedance signal track to form an inner grounding line grid that is coplanar with the controlled impedance signal track for waveguide mode rejection.
    Type: Grant
    Filed: May 12, 1998
    Date of Patent: June 6, 2000
    Assignee: Harris Corporation
    Inventors: Calvin L. Adkins, Donald K. Belcher
  • Patent number: 6057743
    Abstract: A connector for telecommunication systems has input terminals and output terminals arranged in ordered arrays and connected by a circuit having a plurality of conductive paths connecting the respective input and output terminals. The circuit cancels crosstalk induced across adjacent connected terminals by sets of sections. Two of the paths have one set of sections connected in series and spaced from each other between the input and output terminals. Another pair of paths have another set of sections connected in series and spaced from each other between the input and output terminals. Each section of the two sets forms a noise reduction circuit providing a reactive coupling between the respective paths which is greater than adjacent portions of the paths spacing the sections of the two sets.
    Type: Grant
    Filed: June 22, 1998
    Date of Patent: May 2, 2000
    Assignee: Hubbell Incorporation
    Inventor: Robert A. Aekins
  • Patent number: 6040524
    Abstract: A printed circuit board and video switcher board containing the circuit board including a first dielectric lamina having opposed surfaces and a first layer deposited on one of the surfaces which has of a plurality of first layer signal lines on one of the surfaces. A plurality of first ground areas of defined width are arranged between the first layer signal lines such that each of the first layer signal lines has one of the first ground areas on a side thereof so that none of the first layer signal lines is immediately adjacent to another first layer signal line. A second substantially uninterrupted layer on the other surface of the first lamina forming a second ground area which is substantially coextensive with the other surface. At least two holes extend through the first lamina between the first and second ground areas and each of the holes has openings at the first ground areas and at the second ground area.
    Type: Grant
    Filed: December 6, 1995
    Date of Patent: March 21, 2000
    Assignee: Sony Corporation
    Inventors: Yuji Kobayashi, Shinichiro Yamashita
  • Patent number: 6028494
    Abstract: A stripline isolation cross-over is configured to cancel signals that may be mutually coupled at cross-over points between adjacent stripline networks within a compact multilayer signal distribution architecture, such as one feeding elements of phased array antennas, without a shielding layer between adjacent signal distribution networks. The signal distribution networks includes layers of stripline, patterned on opposite sides of a dielectric layer. Wherever the stripline layers mutually overlap, they are oriented at right angles to one another, and one of the striplines is configured as a pair of power dividers, connected back-to-back via stripline interconnect passing the other stripline layer, to form a signal splitting-recombining stripline pair.
    Type: Grant
    Filed: January 22, 1998
    Date of Patent: February 22, 2000
    Assignee: Harris Corporation
    Inventors: Jeffery C. May, Walter M. Whybrew, Douglas E. Heckaman
  • Patent number: 6023200
    Abstract: An apparatus for inhibiting cross talk under a difference mode is disclosed, in which undesired cross talk due to the adjacency and non-uniformness of the untwisted portion are eliminated when untwisting the UTP (unshielded twisted pair) cables to insert the UTP cables into plug holes. In four pairs which are liable to generate cross talk due to their adjacency, artificial patterns are disposed on the front and rear faces of a PCB in such a manner that an effect the same as an insertion of a spiral capacitor should be produced, so that the cross talk in the interfering lines would meet the regulated value. In arranging a plurality of transmission lines to improve the radio wave transmission performance, the four pairs of the lines are disposed on the front and rear faces of the PCB more specifically, spiral capacitors are disposed as follows. A third line is disposed on the rear of a first line, a fifth line is disposed on the rear of a third line, and an eighth line is disposed on the rear of a sixth line.
    Type: Grant
    Filed: March 9, 1998
    Date of Patent: February 8, 2000
    Assignee: Dae Eun Electric Co., Ltd.
    Inventor: Eun-Shin Rhee
  • Patent number: 6008705
    Abstract: A data transmission system generally comprising a bus with transmission lines, and a signal driver that applies a first signal to a first one of the transmission lines, and applies one or more signals to at least one other of the transmission lines which is adjacent the first transmission line, wherein the second signal has an amplitude proportional to an amplitude of the first signal such that crosstalk between the first and second transmission lines is substantially reduced. The signal driver may take the form of a current mode driver, which provides the compensating (second) signal with a current which is k/c times smaller than the current of the first signal, wherein k is the mutual capacitance between the first and second transmission lines, and c is the capacitance between either of the first or second transmission lines and a ground plane. If the first and second transmission lines are orthogonal, the current mode driver preferably includes differential input lines.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: December 28, 1999
    Assignee: International Business Machines Corporation
    Inventor: Uttam Shymalindu Ghoshal
  • Patent number: 5982249
    Abstract: A reduced crosstalk microstrip transmission-line has a plurality of microstrips sandwiched between a lower base dielectric layer of flexible circuit material and an upper coverlay with higher permittivity and of different flexible circuit material than the base dielectric layer. With the higher permittivity of the coverlay, the thickness of the coverlay is selected such that the microstrip transmission-line retains practical flexibility and far-end crosstalk to a first neighboring microstrip from a driving channel is zero.
    Type: Grant
    Filed: March 18, 1998
    Date of Patent: November 9, 1999
    Assignee: Tektronix, Inc.
    Inventor: Michael W. Bruns
  • Patent number: 5945886
    Abstract: The present invention provides for high speed signal buses in printed circuit boards. For high speed operation, each signal line of a bus has substantially the same electrical length as the other signal lines and forms a loop in two halves, each half electrically shielded from the other half. Each signal line has a first and a second terminal, with each terminal connected to a reference bias voltage through a first resistance which matches a loaded characteristic impedance of the signal line. The reference bias voltage is set at a midpoint of signal voltage swings on the signal line. Such high speed buses have particular applications to high speed memory systems with DRAMs.
    Type: Grant
    Filed: September 19, 1997
    Date of Patent: August 31, 1999
    Assignee: Sldram, Inc.
    Inventor: Bruce Millar
  • Patent number: 5939952
    Abstract: A flat flexible electrical cable includes a pair of pseudo-twisted conductors on a flexible dielectric substrate. Each conductor includes alternate straight and oblique sections. The straight sections of the conductors are generally parallel to each other and of uniform width. The oblique sections of the conductors cross each other at a crossover point. Each oblique section of each conductor is reduced in width uniformly in a direction from the straight-to-oblique transfer point of the respective conductor to the crossover point of the conductors.
    Type: Grant
    Filed: May 21, 1997
    Date of Patent: August 17, 1999
    Assignee: Molex Incorporated
    Inventors: Atsuhito Noda, Tetsuo Hoshino
  • Patent number: 5912597
    Abstract: A printed circuit board capable of suppressing radiation noise efficiently includes a first conductive layer where a plurality of power lines are provided at predetermined spacing along one direction, a second conductive layer where a plurality of power lines are provided at predetermined spacing along a direction orthogonal to the one direction, and a plurality of plated through holes for connecting the power lines on the first conductive layer and the power lines on the second conductive layer at the overlapping points of those lines. The power lines contain thin lines and thick lines spaced between a plurality of the thin lines. The predetermined spacing is determined based on a rising time or falling time of the output signal of the IC to be mounted on the circuit board.
    Type: Grant
    Filed: March 30, 1995
    Date of Patent: June 15, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideho Inagawa, Tomoyasu Arakawa, Toru Otaki, Yasushi Takeuchi, Yoshimi Terayama, Toru Osaka
  • Patent number: 5907265
    Abstract: An inexpensive high-frequency circuit device and its electronic component which allows two traces or lines to cross on the same surface without affecting other circuits characteristics. At least one of the lines is a high-frequency signal line.
    Type: Grant
    Filed: September 11, 1997
    Date of Patent: May 25, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toru Sakuragawa, Naoki Yuda, Kimio Aizawa, Ikuo Ota, Hideki Nanba
  • Patent number: 5870064
    Abstract: A ridged coaxial transmission line assembly including a plurality of parallel transmission paths is fabricated from an extrusion incorporating a plurality of slotted, longitudinal bores provided with centrally located conductors held in position by insulating stand-offs provides a structure performing the dual functions of electrically integral antenna mast and signal conductors for a linear array of antenna elements supported by the mast.
    Type: Grant
    Filed: October 1, 1997
    Date of Patent: February 9, 1999
    Assignee: TX RX Systems Inc.
    Inventor: Daniel P. Kaegebein
  • Patent number: 5828555
    Abstract: A multilayer printed-circuit board includes at least one inner-layer signal line, first and second ground layers between which the inner-layer signal line is sandwiched via a frame member made of an insulating material in a thickness direction of the multilayer printed-circuit board, and metallic wall members which are provided on inner walls of slits formed in the frame member and extending along the inner-layer signal line. The first and second ground layers and the metallic wall members shielding the inner-layer signal line.
    Type: Grant
    Filed: May 20, 1997
    Date of Patent: October 27, 1998
    Assignee: Fujitsu Limited
    Inventor: Takumi Itoh