Abstract: A clock generating circuit in which a plurality of stages of inverting circuits are connected, a start signal that causes start of clock generation and an output signal from the inverting circuit of a predetermined stage are input to one of the inverting circuits, an element having impedance that changes in accordance with a magnitude of an object analog signal that is an object of conversion to a digital signal is provided between the adjacent inverting circuits, generates a clock of a frequency in accordance with the magnitude of the object analog signal. A counter counts the number of clocks generated by the clock generating circuit and outputs a count value.

Abstract: A time-to-digital converter includes a phase-difference enhancement section configured to receive first and second input signals having a reference phase difference ?t, and to output first and second output signals having an enhanced phase difference; and a comparison section configured to receive the first and second output signals, to compare a phase difference between the first and second output signals with a reference delay time ?, and to output a comparison signal. The time-to-digital converter has a high resolution. That is to say, the time-to-digital converter has a resolution less than the minimum phase delay time of a delay element, which is obtainable in a corresponding semiconductor process.

Abstract: A received plurality of signals may be filtered to select an in-band signal and/or an out-of-band. A signal strength of the selected signal(s) may be measured. A resolution of an analog-to-digital converter may be controlled based on the measured signal strength(s). The selected in-band signal may be converted to a digital representation via the analog-to-digital converter. The resolution may be decreased when the strength of the in-band signal is higher, and increased when the strength of the in-band signal is lower. The resolution may be increased when the strength of the out-of-band signal is higher, and decreased when the strength of the out-of-band signal is lower. A signal-to-noise ratio and/or dynamic range of the selected signal(s) may be determined based on the measured signal strength(s), and may be utilized to adjust the resolution of the analog-to-digital converter.

Abstract: A system and method are provided for operating first and second components in first and second domains. In one embodiment, the method includes: generating a plurality of clock signals shifted relative to one another; operating a first component in a first domain using a first one of the plurality of clock signals; operating a second component in a second domain using a second one of the plurality of clock signals selected using a selection component; and comparing a present output of the second component to a stored value, determining whether a variation between the present output and the stored value is greater than a threshold, and, if the variation is greater than the threshold, using a controller to cause the selection component to select a third clock signal from the plurality of clock signals that is shifted relative to the second clock signal to drive the second component.

Abstract: A system and method for processing an analog signal output by a sensor. The system and method converting, using at least one analog-to-digital converter (ADC), the analog output signal to a digital signal, the digital signal including a plurality of samples at a predetermined resolution, detecting whether a trigger condition is met by analyzing the digital signal, detecting an event based on trigger information from the detecting whether a trigger condition is met, generating event information having time information included therein when the event is detected, defining one or more time windows based on the time information included in the event information, performing decimation on the digital signal based on the defined one or more time windows to generate a decimated signal, and outputting the decimated signal.

Abstract: An analog-to-digital converter may include an annular delay circuit that includes a plurality of delay units connected in an annular shape, each of the plurality of delay units delaying a pulse current that is input to each of the plurality of delay units, a current source that outputs an electric current, in accordance with an input analog signal, to selected delay units, which is selected from among the plurality of delay units, and a digital signal generation unit that generates a digital signal in accordance with a number of circulations per predetermined period of time of the pulse current circulating around the annular delay circuit.

Abstract: The invention relates to the conversion into digital information of the time difference between a first signal and a second signal. In particular, in order to determine a fractional part of the number of periods of a first signal for a period of a second signal, the following are alternately performed: /1/ delaying the second signal relative to the first signal and determining a first digital information item, a function of the fractional part, /2/ delaying the first signal relative to the second signal and determining a second digital information item, a function of the fractional part. Then the fractional part is calculated as a function of the previously obtained first and second digital information items.

Abstract: The present invention relates to an analog-to-digital converting circuit, which comprises an integrating circuit, a reference signal generating circuit, a comparator, and a first counting circuit. The integrating circuit integrates an input signal for producing an integration signal. The reference signal generating circuit produces a plurality of reference signals. The comparator receives the integration signal and the plurality of reference signals, and compares the integration signal to the plurality of reference signals sequentially for producing a plurality of comparison signals. The first counting circuit receives the plurality of comparison signals produced by the comparator, and starts to count the plurality of comparison signals for producing a reset signal and resetting the integrating circuit.

Abstract: Methods and apparatuses for time to digital conversion (TDC) are disclosed. A timing circuit comprises a TDC circuit, a calibration module, and a correction module. The TDC circuit is configured to provide a timing signal indicative of a timing difference between edges of a periodic reference clock signal and a variable feedback signal. The TDC circuit is also configured to provide a delay signal that is variably delayed relative to the reference clock signal. The calibration module is configured to provide a calibration signal to increase and decrease a total delay of the TDC circuit based on a time delay of the calibration signal plus a time delay of a correction signal. The correction module, which is configured to receive the timing signal and provide the correction signal, minimizes harmonic spurs in a frequency response of the timing signal by operating at a frequency of the reference clock signal.

Abstract: Provided is a time-domain voltage comparator including a voltage-time converter. The voltage-time converter includes a conversion unit and an output unit. The conversion unit includes a first MOS transistor which shifts a voltage level of the first detection node according to an external first voltage signal, and a second MOS transistor which shifts a voltage level of the second detection node according to an external second voltage signal. The output unit generates first and second output signals in response to voltages of the first and second detection nodes. The output unit determines a shifted time of the first output signal according to a voltage level of the first detection node and determines a shifted time of the second output signal according to a voltage level of the second detection node.

Abstract: A method and a system for converting time intervals are provided. In one embodiment, the system comprises a first time-to-digital converter having a first resolution configured to convert a first time interval, a second time-to-digital converter having a second resolution configured to convert a second time interval, and a third time-to-digital converter having a third resolution and coupled to the first time-to-digital converter and the second time-to-digital converter, the third time-to-digital converter configured to convert a third time interval and a fourth time interval.

Abstract: An asynchronous pulse processing (APP) apparatus, an APP system and a method of signal normalization employing APP provide signal normalization. The APP apparatus includes a gain block configured to scale an input signal by a first scale value and a summation block configured to produce a composite signal by subtracting from the scaled input signal each of a normalized signal scaled by a second scale value and the normalized signal multiplied by a summation signal. The APP apparatus further includes an integrator and a time encoder configured to produce the normalized signal from the composite signal. The APP system includes a plurality of APP apparatuses as APP channels. The method of signal normalization includes generating the composite signal from the scaled input signal and integrating and time encoding the composite signal to produce the normalized signal.

Abstract: A time-to-digital converter device includes a first delay chain circuit that generates a first value corresponding to a time delay between a start signal and a stop signal. The time-to-digital converter device also includes at least one second delay chain circuits that generates a second value corresponding to a time delay between a delayed start signal and the stop signal. At least one delay element generates the delayed start signal by applying a predetermined delay to the start signal, and a combining circuit generates an output value based on the first and second values. In the time-to-digital converter according to the exemplary embodiments of the present advancements, the output value corresponds to the time delay between the start signal and the stop signal.

Abstract: A time-to-digital converter includes a circular delay chain, a phase interpolator, and a time-to-digital (TDC) core. The circular delay chain receives a first input clock and generates a first set of multi-phase clocks by propagating the first input clock through delay cells in the delay chain. The phase interpolator performs phase interpolation with a second input clock and another clock to generate a second set of multi-phase clocks. The other clock may be a delayed version of the second input clock. The TDC core uses the first and second set of multi-phase clocks to determine the time difference between the first and second input clocks.

Abstract: A TDC circuit include: a first delay circuit having first inverting delay devices connected to form a loop, the first inverting delay devices outputting a inverted signal according to an input signal after a first signal delay period; a second delay circuit having second inverting delay devices connected to form a loop, the second inverting delay according to an input signal after a second signal delay period different from the first signal delay period; first flip-flop circuits that latch the logical values of third pulse signals including the first pulse signal output from the first inverting delay devices based on fourth pulse signals including the second pulse signal or pulse signals; a first counter that counts the third pulse signal; a second counter that counts the fourth pulse signal; and a detection result output circuit that stores the count from the first counter and the count from the second counter.

Abstract: An apparatus for measuring time interval between two selected edges of a clock signal. includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first constant incremental delay at each tap to the first edge. Second multi-tap delay module provides a second constant incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has a first input terminal and a second input terminal. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval.

Abstract: A current mode dual-slope temperature-to-digital conversion device is disclosed. The conversion device comprises a temperature dependent current source and a reference current source. Firstly, a capacitor is charged by the temperature dependent current source. Next, the capacitor is discharged by the reference current source. The capacitor is coupled to at least one trigger, and the trigger sends out a first digital signal to a logic controller by the voltage of the capacitor. Then, the logic controller sends out a second digital signal to a time-to-digital converter according to the first digital signal. When the capacitor is discharged by the reference current source and before the first digital signal is varied, the converter receives the second digital signal and a clock signal to generate a corresponding digital output value.

Abstract: A radiation detector module (10) for use in a time-of-flight positron emission tomography (TOF-PET) scanner (8) generates a trigger signal indicative of a detected radiation event. A timing circuit (22) including a first time-to-digital converter (TDC) (30) and a second TDC (31) is configured to output a corrected timestamp for the detected radiation event based on a first timestamp determined by the first TDC (30) and a second timestamp determined by the second TDC (31). The first TDC is synchronized to a first reference clock signal (40, 53) and the second TDC is synchronized to a second reference clock signal (42, 54), the first and second reference clock signals being asynchronous.

Abstract: According to one embodiment, a multiphase circuit, a flip-flop, and a decoder are provided. The multiphase circuit generates multiphase signals of which phases are different from each other by 180/M degrees by dividing a differential oscillation signal by M (M is an integral number not smaller than 2). The flip-flop captures the multiphase signal in synchronization with an input of a reference signal. The decoder decodes an output signal of the flip-flop.

Abstract: Methods and apparatuses for time to digital conversion (TDC) are disclosed. A timing circuit comprises a TDC circuit, a calibration module, and a correction module. The TDC circuit is configured to provide a timing signal indicative of a timing difference between edges of a periodic reference clock signal and a variable feedback signal. The TDC circuit is also configured to provide a delay signal that is variably delayed relative to the reference clock signal. The calibration module is configured to provide a calibration signal to increase and decrease a total delay of the TDC circuit based on a time delay of the calibration signal plus a time delay of a correction signal. The correction module, which is configured to receive the timing signal and provide the correction signal, minimizes harmonic spurs in a frequency response of the timing signal by operating at a frequency of the reference clock signal.

Abstract: An analog-to-digital converter converting an analog input signal into a digital signal includes a comparator comparing a reference signal with an input signal and, if the reference signal matches the input signal, inverting an output; and a counter counting a comparison time. The counter includes flip flops that perform serial input/output. An input and an output of the counter are interconnected. The counter operates in a counter mode and a shift register mode. In the counter mode, a data output of each flip flop is supplied to a clock input of the next flip flop, and, if the output of the comparator is at a predetermined level, the counter functions as a counter synchronized with a counter clock signal. In the shift register mode, the flip flops are cascade-connected, and the counter functions as a shift register synchronized with a shift register clock signal.

Abstract: Provided are a TDC having a pipeline or cyclic structure and an operating method thereof. The TDC includes a first stage block and a second stage block. The first stage block detects a first bit of a digital code for a time difference between first and second input signals. The second stage block detects a second bit of the digital code for a time difference between first and second output signals of the first stage block. The first stage block amplifies a time difference between first and second delay signals for the first and second input signals to generate the first and second output signals, and transfers the first and second output signals to the second stage block.

Abstract: A successive time-to-digital converter (STDC) method is provided for supplying a digital word representing the ratio between a phase-locked loop PLL frequency synthesizer signal and a reference clock. The number of frequency synthesizer clock cycles per reference clock cycle is counted. A first difference is measured between a reference clock period and a corresponding frequency synthesizer clock period. In response to the first measurement, a second difference is measured between a delayed reference clock period and the corresponding frequency synthesizer clock period, where the second difference is less than the first difference. A third difference is measured as a time duration between the delayed reference clock period and the corresponding delayed frequency synthesizer clock period. The first and third difference measurements and the count of the number of frequency synthesizer clock cycles per reference clock cycle are used to calculate a digital error signal supplied to the frequency synthesizer.

Abstract: Methods, systems and devices are disclosed. Among the disclosed devices is an electronic device that, in certain embodiments, includes a plurality of memory elements or imaging elements connected to a bit-line and a delta-sigma modulator connected to the bit-line. The delta-sigma modulator may include an integrator having a differential amplifier.

Abstract: The analog-digital converter (ADC) includes a modulator and a digital integrator. The modulator is configured to modulate an input signal and output a modulated signal. The digital integrator includes a plurality of accumulators serially connected to one another. The digital integrator is configured to integrate the modulated signal to output an integration result.

Abstract: According to one general aspect, an apparatus may include a terminal configured to receive an analog input signal. In various embodiments, the apparatus may also include a multistage amplifier configured to amplify the analog input signal by an amount of gain. In some embodiments, the apparatus may include a distributed threshold adjuster interspersed between the stages of the multistage amplifier configured to adjust the DC voltage of the analog input signal to facilitate a decision by an analog-to-digital converter (ADC). In one embodiment, the apparatus may include the ADC configured to convert the amplified analog input signal to a digital output signal.

Abstract: Apparatuses and methods related to time-to-digital converters (TDCs) are herein described. Generally, a time-to-digital converter is a device which measures a time period or time interval and outputs a digital value representing the measured time period. In an implementation, an apparatus is provided comprising a time-to-digital converter circuit, which further comprises a built-in self test (BIST). The built-in self test may be implemented using one or more oscillators coupled to the time-to-digital converter via one or more multiplexer devices.

Abstract: A time-to-digital converter includes a phase-difference enhancement section configured to receive first and second input signals having a reference phase difference ?t, and to output first and second output signals having an enhanced phase difference; and a comparison section configured to receive the first and second output signals, to compare a phase difference between the first and second output signals with a reference delay time ?, and to output a comparison signal. The time-to-digital converter has a high resolution. That is to say, the time-to-digital converter has a resolution less than the minimum phase delay time of a delay element, which is obtainable in a corresponding semiconductor process.

Abstract: A radio communication device performs baseband processing by subjecting a received signal to an AD conversion at a predetermined sampling frequency and converting a digital signal resulting from the AD conversion into a baseband signal by frequency conversion. The device includes a frequency converting unit configured to convert the resulting digital signal into a complex baseband signal. The device further includes a waveform shaping unit configured to subject the baseband signal to waveform shaping, and a down-sampling unit configured to subject the baseband signal to sample discrete reduction.

Abstract: A Time-to-Digital Converter (TDC) is provided.

Abstract: A digitizer includes an analog to digital converter (ADC), a sampling frequency generator, and a controller. The ADC samples an IF signal to generate a digital signal. The sampling frequency generator is connected to the ADC and provides a sampling clock of variable frequency to the ADC. The controller is connected to the sampling frequency generator and determines frequency of the sampling clock.

Abstract: Provided is an AD converter that converts an input analog signal into a digital signal, comprising an integrator that sequentially integrates signal levels of the analog signal to obtain an integrated waveform, and outputs the integrated waveform; a digital converting section that detects, with prescribed units of temporal resolution, a transition timing, which is a timing at which a magnitude relationship between a signal level of the integrated waveform and a prescribed reference value transitions to a predetermined state; a feedback section that controls the signal level of the integrated waveform with a control period longer than a unit of temporal resolution, according to a result of the detection by the digital converting section; and a signal processing section that generates the digital signal based on the detection result by the digital converting section.

Abstract: An analog-to-digital converter may include an annular delay circuit that includes a plurality of delay units connected in an annular shape, each of the plurality of delay units delaying a pulse current that is input to each of the plurality of delay units, a current source that outputs an electric current, in accordance with an input analog signal, to selected delay units, which is selected from among the plurality of delay units, and a digital signal generation unit that generates a digital signal in accordance with a number of circulations per predetermined period of time of the pulse current circulating around the annular delay circuit.

Abstract: Provided are, among other things, systems, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. According to one implementation, an apparatus includes multiple processing branches, each including: a continuous-time quantization-noise-shaping circuit, a sampling/quantization circuit, and a digital bandpass filter. A combining circuit then combines signals at the processing branch outputs into a final output signal. The continuous-time quantization-noise-shaping circuits include adjustable circuit components for changing their quantization-noise frequency-response minimum, and the digital bandpass filters include adjustable parameters for changing their frequency passbands.

Abstract: An analog-digital converter according to the present invention includes an input polarity switching unit, an integrator that integrates an input signal, an integrator output adjusting circuit that adjusts an output voltage of the integrator, a window comparator, and a controller that controls the input polarity switching unit, the integrator output adjusting circuit, and the window comparator, and generates a digital signal. When the output voltage of the integrator reaches a first reference voltage, the controller resets reference voltage of a high-voltage side comparator to a second reference voltage. Further, when the output voltage of the integrator reaches a third reference voltage, the controller resets reference voltage of a low-voltage side comparator to a fourth reference voltage. According to the analog-digital converter of the present invention, it is possible to prevent device breakdown and occurrence of through current due to fluctuation of the output voltage of the integrator.

Abstract: An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.

Abstract: A time measurement circuit measures the time difference between edges of a first signal and a second signal. A sampling circuit acquires the logical level of the first signal at a timing of the edge of the second signal. When a sampling circuit enters a metastable state, an output signal thereof transits with a long time scale. A transition time measurement circuit measures a transition time (settling time) of the output signal of the sampling circuit in the metastable state.

Abstract: Provided are a clock detector and a bias current control circuit. The clock detector outputs a digital code corresponding to the frequency of an input clock, and the bias current control circuit controls a bias current supplied to an analog circuit according to the digital code output from the clock detector. Accordingly, when the clock detector and the bias current control circuit are used, it is possible to minimize the power consumption of an analog circuit by controlling a bias current supplied to an analog circuit according to a digital code corresponding to the frequency of an input clock.

Abstract: Exemplary implementations of electrical circuits and systems are disclosed, and methods for signal processing including sampling and quantizing of amplitude and band limited signals implemented through a Passive Pulse Modulation Analog to Digital Converter (PMADC).

Abstract: In one example, a clock generation component is configured to receive a master clock and generate a plurality of clock signals that are shifted relative to one another for a chip having an analog domain and a digital domain. A first selection component is configured to select a first one of the generated clock signals and drive the digital domain according to the first clock signal. A second selection component is configured to select a second one of the generated clock signals that is shifted relative to the first clock signal currently used to drive the digital domain for driving an analog component of the analog domain.

Abstract: A clock generating circuit in which a plurality of stages of inverting circuits are connected, a start signal that causes start of clock generation and an output signal from the inverting circuit of a predetermined stage are input to one of the inverting circuits, an element having impedance that changes in accordance with a magnitude of an object analog signal that is an object of conversion to a digital signal is provided between the adjacent inverting circuits, generates a clock of a frequency in accordance with the magnitude of the object analog signal. A counter counts the number of clocks generated by the clock generating circuit and outputs a count value.

Abstract: Provided are, among other things, systems, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. According to one representative embodiment, an apparatus includes multiple continuous-time quantization-noise-shaping circuits, each in a separate processing branch and having an adder that includes multiple inputs and an output; an input signal is coupled to one of the inputs of the adder; the output of the adder is coupled to one of the inputs of the adder through a first filter; and the output of a sampling/quantization circuit in the same processing branch is coupled to one of the inputs of the adder through a second filter, with the second filter having a different transfer function than the first filter.

Abstract: An A/D conversion circuit includes: a pulse transit circuit into which either a power supply or current source and also a pulse signal is input, and through which the pulse signal transits; a transit position detection section that detects a transit position of the pulse signal within the pulse transit circuit, and outputs data in accordance with the transit position; and a digital data creation section that, based on the data output by the transit position detection section, creates digital data that corresponds to the size of the power supply or current source. The pulse transit circuit is formed by a plurality of inverter circuits that are joined together in series, and the plurality of inverter circuits are formed by identical logical elements in which delay times between input signals and output signals change in accordance with the size of the power supply or current source.

Abstract: A pipeline time-to-digital converter (TDC) is provided. The pipeline TDC includes a plurality of TDC cells. Each of the TDC cells includes a delay unit, an output unit and a determination unit. The delay unit receives a first clock signal and a first reference signal output from a previous stage TDC cell. The delay unit generates sampling phases in a period between a trigger edge of the first reference signal and a trigger edge of the first clock signal, and samples the first clock signal to obtain sampling values in accordance with the sampling phases. The output unit calculates the sampling values for outputting a conversion value. The determination unit uses and analyses the sampling values and the sampling phases for outputting time residue to a next stage TDC cell.

Abstract: A method and a system for converting time intervals are provided. In one embodiment, the system comprises a first time-to-digital converter having a first resolution configured to convert a first time interval, a second time-to-digital converter having a second resolution configured to convert a second time interval, and a third time-to-digital converter having a third resolution and coupled to the first time-to-digital converter and the second time-to-digital converter, the third time-to-digital converter configured to convert a third time interval and a fourth time interval.

Abstract: In one embodiment, an analog to digital converter includes a comparator having a first input, a second input and an output, the first input being coupled to an analog signal, a successive approximation register having a serial input coupled to the output of the comparator, and being configured to generate a plurality of control signals and an N-bit digital value corresponding to the analog signal, and a digital to analog converter having an input coupled to the plurality of control signals, the digital to analog converter further comprising a first, a second, and a third capacitor and a plurality of switches controlled by the plurality of control signals and being configured to couple the first capacitor to the second capacitor and the third capacitor to the second capacitor mutually exclusively to share charge on the first capacitor and charge on the third capacitor with charge on the second capacitor and to generate an analog signal on the second capacitor, the second capacitor being coupled to the second i

Abstract: A voltage-to-digital converting device includes a first voltage-to-time converter outputting a first delay clock having a first time delay relative to a reference clock in response to an input voltage, and a second voltage-to-time converter outputting a second delay clock having a second time delay relative to the reference clock in response to a feedback voltage. The first and second time delays correspond respectively to the input and feedback voltages. A time-to-digital converting circuit receives the first and second delay clocks from the first and second voltage-to-time converters, compares phases of the first and second delay clocks, generates the feedback voltage based on result of phase comparison made thereby, and outputs a digital signal upon detecting that the phases of the first and second delay clocks are in-phase.

Abstract: A method and apparatus are provided for sigma-delta (??) analog to digital conversion, the method including receiving an analog signal, sampling the received signal, comparing the sampled signal with a constant reference voltage, providing at least one high-order bit responsive to the constant reference comparison, comparing the sampled signal with a variable reference voltage, providing at least one low-order bit responsive to the variable reference comparison, and combining the at least one high-order bit with the at least one low-order bit; and the apparatus including a comparator, a first ADC portion supplying the comparator with a constant reference voltage for providing at least one high-order bit, and a second ADC portion supplying the comparator with a variable reference voltage for providing at least one low-order bit.

Abstract: Imbalance and distortion cancellation for composite analog to digital converter (ADC). Such an ‘ADC’ is implemented using two or more ADCs may be employed for sampling (e.g., quantizing, digitizing, etc.) of an analog (e.g., continuous time) signal in accordance with generating a digital (e.g., discrete time) signal. Using at least two ADCs allows for the accommodation and sampling of various signals having a much broader dynamic range without suffering degradation in signal to noise ratio (SNR). Generally, the signal provided via at least one of the paths corresponding to at least one of the respective ADCs is scaled (e.g., attenuated), so that the various ADCs effectively sample signals of different magnitudes. The ADCs may respectively correspond to different magnitude and/or power levels (e.g., high power, lower power, any intermediary power level, etc.). Various implementations of compensation may be performed along the various paths corresponding to the respective ADCs.

Abstract: Apparatus and methods are provided relating to time-to-digital based analog-to-digital converter. An apparatus includes a time-to-digital converter based analog-to-digital converter for generating a first signal and a second signal having a timing relationship between a rising edge of the first signal and a rising edge of the second signal based on a sampled input analog voltage level, and converting the timing relationship into a corresponding time-to-digital representation. The time-to-digital representation is obtained without any voltage comparison and current comparison.