Abstract: A TDC circuit having a small scale circuit and high resolution is disclosed, which is a time-to-digital converter that detects a phase with respect to a reference clock of a signal to be measured, comprising a first delay line in which a plurality of first delay elements with a first delay amount is connected in series, a second delay line group that is connected to a plurality of connection nodes of the first delay line or an input node in the first stage and in which at least one or more second delay elements with a second delay amount different from the first delay amount are connected in series, a plurality of judgment circuits that judge whether the changing edge of the signal to be measured is advanced or delayed with respect to the changing edges of a delayed clock output from the first delay element and the second delay element, and an operation circuit that calculates a phase with respect to the reference clock of the changing edge of the signal to be measured from the judgment results, wherein a dif

Abstract: An on-die thermal sensor includes an integrating analog-digital converter not requiring a negative reference voltage input. The on die thermal sensor includes a band gap unit, an integrating unit and a counting unit. The band gap unit senses a temperature to output a first voltage corresponding to the sensed temperature. The integrating unit integrates a difference between a reference voltage and a comparing voltage to output a second voltage wherein the comparing voltage has a voltage level higher than that of the reference voltage. The counting unit counts clocks of a clock signal input thereto until the second voltage reaches the first voltage, thereby outputting a thermal code corresponding to the voltage level of the first voltage.

Abstract: A TDC circuit includes: a first delay circuit, including at least one first delay stage for delaying a first input signal to generate a first output signal; a second delay circuit, including at least one second delay stage for delaying a second input signal to generate a second output signal; a first counter, for computing the first output signal to generate a first counter value; a second counter, for computing the second output signal to generate a second counter value; and a comparator, for comparing the first counter value and the second counter value to generate a comparing result signal; wherein the first delay stage has a larger delay amount than the second delay stage, the first counter starts before the second counter, and the comparator outputs the comparing result signal when the second counter value falls within a predetermined range of the first counter value.

Abstract: The present invention relates to a low cost analog to digital converter (ADC) and a method for converting an analog signal to a digital signal. The method includes the steps of: outputting a pulse modulation signal according to a digital value; performing a low-pass filtering to the pulse modulation signal to obtain a pulse averaged voltage; mixing a first proportion of the pulse averaged voltage and a second proportion of a voltage under test to obtain a composite voltage; comparing the composite voltage with a threshold voltage and adjusting the first digital value such that the composite voltage approaches the threshold voltage; and performing a complement operation to the digital value to obtain an analog to digital value corresponding to the voltage under test.

Abstract: Apparatus and methods are provided relating to time-to-digital based analog-to-digital converter. An apparatus includes a time-to-digital converter based analog-to-digital converter for generating a first signal and a second signal having a timing relationship between a rising edge of the first signal and a rising edge of the second signal based on a sampled input analog voltage level, and converting the timing relationship into a corresponding time-to-digital representation. The time-to-digital representation is obtained without any voltage comparison and current comparison.

Abstract: Measurement amplification methods and devices for detecting a monopolar input signal (UE) by integrating A/D conversion. Before being digitized, the input signal (UE) is inverted according to the so-called Chopper principle and converted into a bipolar intermediate signal (UZ). A reference voltage (Uref) used in A/D conversion undergoes polarity changes synchronized with the polarity changes of the intermediate signal (UZ). Offset and drift are eliminated by totaling an even number of individual measurements.

Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.

Abstract: A time to digital converter (TDC) is able to be utilized for measuring a time interval between two signals with a very fine time resolution, which is defined as the difference in propagation delay per stage between two rings or chains of delay stages. The Vernier ring TDC, Vernier TDC with comparator matrix or Vernier ring TDCs with comparator matrix comprise two rings or chains of delay stages with slightly different propagation delays per stage and a plurality of comparators for comparing two signals propagation along two rings or chains and determining when the lag signal passes the lead signal. The lead and lag signal are initiated by two events and are each fed into a separate one the first stages of one of the specified rings or chains. The comparators are able to be organized in a comparator matrix in order to occupy less space and permit reuse.

Abstract: Measurement amplification methods and devices for detecting the detuning of a measurement bridge (10) to which a bipolar, rectangular supply voltage (Us) is supplied. The methods and devices use integrating A/D conversion and are characterized in that a reference voltage (Uref) used for the A/D conversion undergoes polarity changes synchronized with the polarity changes of the supply voltage (Us). Offset and drift are eliminated by totaling an even number of individual measurements.

Abstract: An apparatus for transferring serial data (e.g., a serial interface using a single wire) generally includes a detector configured to detect a first level time period and a second level time period of an input signal, and a computing unit configured to compute a duty or duty cycle of the input signal and generate an output signal based on the duty or duty cycle.

Abstract: A delay circuit includes a MOSFET and bias voltage sources. The bias voltage sources apply a voltage difference between the drain and source of the MOSFET. The bias voltage source supplies a source voltage to a source electrode of the MOSFET. The bias voltage source supplies a drain voltage to a drain electrode of the MOSFET. An input signal to be delayed is propagated through the gate of the MOSFET in the gate width direction (y-axis direction).

Abstract: Techniques for enabling a time-to-digital (TDC) to sample with sub-inverter delay resolution are disclosed. In an embodiment, the inputs to a differential D-Q flip-flop in the TDC are coupled to a single-ended signal and a delayed and inverted version of that signal to allow time interpolation of the signal. Further disclosed are techniques to balance the loads of a first delay line and a complementary delay line within the TDC.

Abstract: A digitizer includes an analog to digital converter (ADC), a sampling frequency generator, and a controller. The ADC samples an IF signal to generate a digital signal. The sampling frequency generator is connected to the ADC and provides a sampling clock of variable frequency to the ADC. The controller is connected to the sampling frequency generator and determines frequency of the sampling clock.

Abstract: System and method for converting an analog voltage to a digital signal. The system includes an input voltage sampler, a ramp generator, a comparator, a time-to-digital converter (TDC), and a multiphase oscillator, preferably a rotary traveling wave oscillator, that provides the critical system timing. The phases of the multiphase oscillator define a sampling interval during which the input voltage is sampled and held and a conversion interval during which the ramp generator, comparator, and TDC operate to convert the sampled voltage to the digital signal. The TDC samples at times provided by the phases of the multiphase oscillator to form the bits of the digital signal. The sampler, ramp generator, and comparator can be constructed from multiple fragments, one of which is selectable for calibration while the rest of the fragments are joined for normal operation. Multiple converters can be interleaved to increase the sampling rate.

Abstract: A time-to-digital converter having at least one chain of delay elements, wherein a status of the chain of delay elements represents a digital signal relating to a time interval to be converted, wherein the time-to-digital converter having an injector for injecting a calibration pulse of known position and/or known duration in time into the chain of delay elements, wherein a first status of the chain of delay elements being expected in response to the calibration pulse, the time-to-digital converter further having a capturer for capturing the actual status of the chain of delay elements in response to the calibration pulse, a calculator for calculating a deviation between the expected first status and the actual status, and a combination unit for taking into account the deviation when converting the time interval to the digital signal.

Abstract: A time-to-digital converter includes at least one chain of delay elements, a status of which represents a digital signal relating to a time interval to be converted. The converter includes a provider for providing trigger signals having statistically equally distributed variable positions relative to a pulse forwarded in the chain of delay elements, a capturer for capturing the status of the chain of delay elements in response to the calibration trigger signals, the status depending on delay times of the delay elements, a determiner for determining an actual contribution of at least some of the delay elements to an overall delay of the chain of delay elements on the basis of occurrences of pulse positions in response to the calibration trigger signals. The converter is configured to take into account the actual contribution of at least some of the delay elements when converting the time interval into said digital signal.

Abstract: A CPU outputs digital data from a built-in RAM to a buffer in response to a request from the buffer. The buffer has a FIFO configured of a plurality of stages, each stage of the FIFO is capable of storing one unit (10 bits) of digital data, the buffer as a whole is capable of storing digital data in number of units equivalent to the number of configured stages. A register captures digital data stored inside the buffer by each unit in synchronous with an output control clock. The digital data stored in the register is outputted to a parallel DAC as data for D/A conversion. A WR signal output timer generates a writing control signal having one shot pulse of “L” in synchronous with the output control clock.

Abstract: A voltage-to-digital converting device includes a first voltage-to-time converter outputting a first delay clock having a first time delay relative to a reference clock in response to an input voltage, and a second voltage-to-time converter outputting a second delay clock having a second time delay relative to the reference clock in response to a feedback voltage. The first and second time delays correspond respectively to the input and feedback voltages. A time-to-digital converting circuit receives the first and second delay clocks from the first and second voltage-to-time converters, compares phases of the first and second delay clocks, generates the feedback voltage based on result of phase comparison made thereby, and outputs a digital signal upon detecting that the phases of the first and second delay clocks are in-phase.

Abstract: An analog reference voltage generator for generating a monotonously increasing or decreasing analog reference voltage includes a plurality of dump cells in front of an operational amplifier and controls the dump cells using a plurality of clock signals, respectively, which do not overlap each other in time, thereby increasing a ramping speed. The analog reference voltage generator including the plurality of dump cells controls the generation of an analog reference voltage using the plurality of clock signals obtained by dividing a master clock signal, thereby preventing the voltage level of the reference signal from decreasing due to an increase of the load.

Abstract: A digital to analog converter includes a time encoder that converts an analog input signal into a asynchronous pulse sequence, a pulse asynchronous DeMUX circuit that converts the asynchronous pulse sequence into a parallel stream of pulse sequences at a relatively lower speed, a parallel pulse to asynchronous digital converter, an asynchronous digital to synchronous digital converter, a timing reference circuit to generate absolute time references, and a Digital Signal Processor. This architecture provides for analog to digital conversion based on pulse encoding with a parallel digitization scheme of the pulse encoded signal.

Abstract: An inverter circuit configuring a delay unit is a so-called CMOS transistor including a PMOS transistor and an NMOS transistor, of which respective gates are interconnected and respective drains are interconnected. The source and a back gate of the NMOS transistor are connected to the ground. The source of the PMOS transistor is connected to a positive drive terminal and controlled by an analog input signal. The back gate of the PMOS transistor is connected to a control terminal and controlled by a control signal.

Abstract: An input signal is compared to 2N?1 reference voltages to generate 2N?1 corresponding binary valued comparison signals, delaying at least one of the comparison signals by a variable delay and detecting a difference in arrival time between the delayed signal and another comparison signal. A time interpolation signal encoding a plurality of bins within a least significant bit quantization level is generated, based on the detected difference in arrival time. An M-bit output data is generated based on the comparison signals and the time interpolation signal. A non-uniformity of a code density of the M-bit output data is detected, and based on the detecting the delaying is varied.

Abstract: An integrating analog to digital converter (ADC) is disclosed that comprises a Delay Locked Loop (DLL) (2, 50) which is synchronized to a reference clock signal (12). A rising edge of a clock signal therefore propagates through the DLL once each clock cycle. In use, the integrating ADC converts an analog input signal to a digital output signal dependent upon a timing measurement of an integration carried out by an integrator (4). The timing measurement is taken by reading the logical states of the individual delay cells in the DLL. This enables the position of the rising edges of the clock signal to be determined and used as a timing measurement. The timing measurement is in the form of a digital thermometer code that can be converted into a binary number.

Abstract: A digitizer comprising an analog to digital converter (ADC), a sampling frequency generator, and a controller. The ADC samples an IF signal to generate a digital signal. The sampling frequency generator is coupled to the ADC and provides a sampling clock of variable frequency to the ADC. The controller is coupled to the sampling frequency generator and determines frequency of the sampling clock.

Abstract: A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.

Abstract: An AD converter includes an analog data storing unit, a first DA converter for converting an input digital data into a first analog reference voltage which varies within a first voltage range in a range of every possible signal voltage of the input analog data, a second DA converter for converting the input digital data into a second analog reference voltage which varies within a second voltage range in the range of every possible signal voltage of the input analog data, a first comparator for comparing the input analog data with the first reference voltage, a second comparator for comparing the input analog data with the second reference voltage and a digital data storing unit for storing a digital data corresponding to a point of time when a change of state occurs in the comparison results of each of the first and second comparators.

Abstract: A time-to-digital converter includes low and high resolution time-to-digital converters for providing both high resolution and wide measurement range. The low resolution time-to-digital converter measures a time difference between first and second signals with a first quantization step. The high resolution time-to-digital converter measures the time difference between the first and second signals with a second quantization step that is smaller than the first quantization step. The low resolution time-to-digital converter has a wider measurement range than the high resolution time-to-digital converter.

Abstract: Provided is an AD conversion apparatus including a bit selecting section that sequentially selects conversion target bits of the output data, from an upper bit downward; a data control section that outputs comparison data determining a value of the conversion target bit, each time a conversion target bit is selected; a DA converting section that outputs an analog comparison signal corresponding to the comparison data; a timing generating section that outputs a comparison control signal ordering comparison initiation; a changing section that changes a timing of the comparison control signal according to a bit position of the conversion target bit, such that the timing of the comparison initiation indicated by the comparison control signal is later for higher conversion target bits; a comparing section that begins comparing the input signal to the comparison signal at the comparison initiation timing indicated by the comparison control signal having the timing changed by the changing section; and a completion d

Abstract: Apparatus for the analog/digital conversion of a measurement voltage with an analog/digital converter, which has an integrating component with an operational amplifier, a resistor and a capacitor in a feedback loop, wherein a reference voltage is applied to the inverting input of the operational amplifier and wherein the measurement voltage is applied to the non-inverting input of the operational amplifier The capacitor is charged during a charging phase of time length (t1) and discharged during a discharging phase of time length, wherein the analog/digital converter further includes a comparator connected downstream from the operational amplifier, a memory element connected downstream from the comparator, a time generator producing the charging time and a counter, the counter detects the edges, or the period length of the pulse-width modulated output signal provided by the A/D converter on the output, and a synchronizing element is provided, which synchronizes the edges of the pulse-width modulated, output s

Abstract: A time-to-digital converter includes at least one chain of delay elements, a status of which represents a digital signal relating to a time interval to be converted. The converter includes a provider for providing trigger signals having statistically equally distributed variable positions relative to a pulse forwarded in the chain of delay elements, a capturer for capturing the status of the chain of delay elements in response to the calibration trigger signals, the status depending on delay times of the delay elements, a determiner for determining an actual contribution of at least some of the delay elements to an overall delay of the chain of delay elements on the basis of occurrences of pulse positions in response to the calibration trigger signals. The converter is configured to take into account the actual contribution of at least some of the delay elements when converting the time interval into said digital signal.

Abstract: A time-to-digital converter (TDC) is disclosed, the TDC comprising: a plurality of parallel circuits for receiving a common first clock and for generating a plurality of delayed clocks; a plurality of sampling circuits for receiving and sampling said delayed clocks at an edge of a second clock to generate a plurality of decisions, respectively; and a decoder for receiving said decisions and for generating a digital output accordingly.

Abstract: A multiple output time-to-digital converter (TDC) and an Analog-to-Digital Converter (ADC) incorporating the multiple output TDC is disclosed.

Abstract: A system and method for converting analog signals to digital signals minimize the latency of the analog to digital conversion for real-time systems. The conversion system and method implements the hardware of an analog to digital converter input/output (I/O) board and a software-based I/O-driver in an expansion bus. The hardware of the ADC I/O board executes free-running conversion of an analog signal into digital form and stores the converted values in a first level of a buffer having two levels. Previously stored converted values are pushed to the second level of the buffer when a new value is written to the first level. The I/O driver then retrieves stored values from the second level of the buffer when needed by the real-time system and gates the buffer to prevent pushing during retrieval of values from the second level.

Abstract: A multiple output time-to-digital converter (TDC) and an Analog-to-Digital Converter (ADC) incorporating the multiple output TDC is dislosed.

Abstract: A method and system of decimating a Pulse Width Modulated (PWM) signal (537) is provided. The method includes computing one or more timestamps (553) of the PWM signal (537), the PWM signal being at a first sample rate (567). The one or more timestamps (553) are computed at a second sample rate (568), which is lower than the first sample rate (567). Thereafter, the method generates a plurality of pre-filter signals (557-n) based on each of the one or more timestamps (553) and a plurality of translation factors (555-n). The plurality of pre-filter signals (557-n) is then filtered at the second sample rate (568) using a plurality of Infinite Impulse Response (IIR) filters (560-n) to generate a plurality of intermediate decimated Pulse Code Modulated (PCM) signals (563). The plurality of intermediate decimated PCM signals (563) is combined to generate a PCM signal (569).

Abstract: An analog to digital converter (ADC) with interference rejection capability and method thereof are disclosed. The ADC includes a threshold generator, a comparator circuit, a counter and an integrator. By comparing a signal with positive and negative threshold signals from the threshold generator, the comparator circuit converts the signal from analog to digital based on the result of the comparison. The counter counts a percentage of the digital signal and generates a bit signal based on the counted percentage. In response to the bit signal, the integrator supplies a control signal to the threshold generator to regulate the positive and negative threshold signals so as to maintain the counted percentage at a predetermined percentage threshold.

Abstract: Some embodiments include apparatus and methods having a first module with a capacitor network configured to receive a sample of an analog input signal and an amplifier configured to couple to the capacitor network in a plurality of arrangements to successively generate a plurality of residue signals at an amplifier output node of the amplifier without resetting the amplifier between generation of least two of the plurality of residue signals, and a second module configured to generate a digital signal based on a plurality of intermediate codes generated from the sample signal and the plurality of residue signals, the digital signal including a digital value of the sample.

Abstract: Techniques for enabling a time-to-digital (TDC) to sample with sub-inverter delay resolution are disclosed. In an embodiment, the inputs to a differential D-Q flip-flop in the TDC are coupled to a single-ended signal and a delayed and inverted version of that signal to allow time interpolation of the signal. Further disclosed are techniques to balance the loads of a first delay line and a complementary delay line within the TDC.

Abstract: A comparator is provided that outputs a comparison result obtained by comparing two signals.

Abstract: An improvement in sampling a high frequency input analog signal and converting it to a digital output signal is disclosed. This is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using multiple ADCs for multiple samplings, wherein each sampling is sequentially offset a fixed amount of time from the most recent preceding sampling. Each ADC has a designated central processing unit (CPU) to obtain sufficient data transfer capabilities. The samplings from the multitude of ADCs are a series of sequential digital output values.

Abstract: A method and system for operating a comparator (602) is provided. The method includes analyzing an output (612) of the comparator (602) based on one or more of a transition of the output, present operational state of the comparator, and at least one time instant corresponding to the output. The method further includes controlling an operational state of the comparator (602) based on the analysis of the output (612).

Abstract: An analog-to-digital converter circuit comprises a first voltage comparator coupled to a first reference voltage and a signal voltage, the first voltage comparator having first negative and first positive outputs for outputting a comparison of the first reference voltage with the signal voltage; a second voltage comparator coupled to a second reference voltage and the signal voltage, the second reference voltage different than the first reference voltage, the second voltage comparator having second negative and second positive outputs for outputting a comparison of the second reference voltage with the signal voltage; and a first arrival time comparator coupled to the first positive output and the second negative output, the first arrival time comparator having a first arrival time comparator output for outputting a comparison of the first positive output with the second negative output.

Abstract: A new analog-to-digital (ADC) circuit and architecture and the corresponding method of implementation are provided. The analog input signal is converted into a modulated pulse stream such as by a pulse-width-modulation scheme. The time-duration width of the pulses are measured by a TDC (time-to-digital converter) and converted to a digital binary representation that is directly correlated with the voltage amplitude of the analog input signal. The circuit implementation is substantially free of switches and circuit issues such as associated with sigma-delta and switched-capacitor techniques for ADC's.

Abstract: An integration type A/D converter in which a dynamic range is enlarged while keeping a simple circuit configuration is provided. Offset potential of an integrator is to be variable. Specifically, offset potential in proportion to input potential is supplied to the integrator. Since an operation point of the integrator is changed in accordance with the input potential, a dynamic range can be enlarged. Further, reference potential input to the integrator in discharging is to be variable. Specifically, reference potential having a constant difference from the offset potential is input to the integrator. Accordingly, time necessary for discharging and the input potential are in proportion, so that a simple circuit configuration which is one feature of the integration type ADC can be maintained.

Abstract: This disclosure relates to analog to digital conversion using irregular sampling.

Abstract: This disclosure describes a chopper-stabilized sigma-delta analog-to-digital converter (ADC). The ADC is configured to provide accurate output at low frequency with relatively low power. The chopper-stabilized ADC substantially reduces or eliminates noise and offset from an output signal produced by the mixer amplifier. Dynamic limitations, i.e., glitching that result from chopper stabilization at low power are substantially eliminated or reduced through a combination of chopping at low impedance nodes within the mixer amplifier and feedback. The signal path of the ADC operates as a continuous time system, providing minimal aliasing of noise or external signals entering the signal pathway at the chop frequency or its harmonics. In this manner, the chopper-stabilized ADC can be used in a low power system, such as an implantable medical device (IMD), to provide a stable, low-noise output signal.

Abstract: A time-to-digital converter includes a first delay line, a second delay line, comparators, and an encoder. The first delay line includes first resistors coupled in series and receives a first signal through a start node. The second delay line includes second resistors coupled in series and receives a second signal through a node corresponding to an end node of the first delay line. The comparators compare first voltages of nodes on the first delay line with second voltages of corresponding nodes on the second delay line. The encoder generates a digital code based on outputs of the comparators. Therefore, the time-to-digital converter may decrease a chip size thereof and lower power consumption, and the time-to-digital converter may increase a range of a maximum delay time between two signals.

Abstract: A system and method are disclosed for monitoring environmental conditions of a perishable product. The system includes an environmental sensor configured to sense one or more environmental conditions of the perishable product and an analog integrator in communication with the environmental sensor, the analog integrator being formed on a polymer substrate and including one or more tunable components. The system also includes a comparator in communication with the analog integrator and configured to change state when an output of the analog integrator reaches a selected threshold level, and a control module in communication with the comparator and the analog integrator. The control module is configured to control the operation of the analog integrator based on an output of the comparator.

Abstract: A time-to-digital converting circuit and a pressure sensing device using the same are provided. The circuit includes: a delay time-varying unit generating a reference signal having a fixed delay time, and a sensing signal having a variable delay time in response to an impedance of an externally applied signal; and a delay time calculation and data generation unit calculating a delay time difference between the reference signal and the sensing signal, and generating digital data having a value corresponding to the calculated delay time difference. Accordingly, the digital data are generated using the delay time varied in response to the externally applied signal, so that the size of the time-to-digital circuit is significantly reduced. In addition, an affect due to external noises is minimized.

Abstract: A time period of an event is determined by charging a known value capacitor from a constant current source during the event. The resultant voltage on the capacitor is proportional to the event time period and may be calculated from the resultant voltage and known capacitance value. Capacitance is measured by charging a capacitor from a constant current source during a known time period. The resultant voltage on the capacitor is proportional to the capacitance thereof and may be calculated from the resultant voltage and known time period. A long time period event may be measured by charging a first capacitor at the start of the event and a second capacitor at the end of the event, while counting clock times therebetween. Delay of an event is done by charging voltages on first and second capacitors at beginning and end of event, while comparing voltages thereon with a reference voltage.