Abstract: For the realization of a unipolar analog input range, in addition to the provision of an analog input sampling circuit having an input capacitor, a charge transfer circuit, an integrator having an integrating capacitor, a comparator, and a D-type flip-flop, there is further provided a reference voltage sampling circuit for selectively adding either of a subtraction and addition voltages which are different from each other to a sampled analog input voltage in response to a delayed comparator output. The reference voltage sampling circuit has a subtraction and addition capacitors differing in capacitance value from each other.

Abstract: In one aspect of the invention, a method for sampling an input signal includes offsetting the input signal with a reference signal. The reference signal represents an offset voltage in the analog-to-digital converter. The method also includes generating a digital output signal based on the offset input signal. The method further includes adjusting the reference signal based on the digital output signal. In addition, the method includes communicating the adjusted reference signal for further offsetting of the input signal.

Abstract: A multislope, continuously integrating analog-to-digital converter includes a first switch coupled to a first reference voltage, a second switch coupled to a second reference voltage, a third switch coupled to an input voltage, and an integrator operably coupled to the first, second, and third switches. The analog-to-digital converter utilizes a primary discharge current of opposite polarity to a secondary discharge current. The analog-to-digital converter has a high resolution due to a small reference voltage, and a high dynamic range due to a large reference voltage. The analog-to-digital converter can operate in either a conversion mode or a calibration mode. During the calibration mode, a calibration factor is calculated for use during the conversion mode. When applied to the conversion mode, the calibration factor corrects for errors in the conversion process.

Abstract: Power available to a delta sigma modulator is controlled so that relatively high power is provided during one phase of operation, such as during an interval when slewing in a device is expected and relatively low power is provided during another phase. In one implementation, increased power is provided by switching in parallel current mirrors when power demands are expected to be high, whether or not high power is actually needed in a particular interval. A large step size is selected to reduce power corruption and feedback coefficients are optimized for low power by running at a higher oversampling rate than required by signal to quantization noise requirements.

Abstract: An OTA circuit is disposed between a differential pair composed of NMOS transistors and an NMOS follower transistor that composes an output buffer circuit. The OTA circuit generates a compensation current that is equal to a current that flows in a capacitance formed between the gate and the drain of each of the differential pair transistors and that flows in the reverse direction thereof. The compensation current cancels the current that flows in the capacitance formed between the gate and the drain of each of the differential pair transistors. Thus, a differential amplifier that has a high accuracy and, high gain, and a wide frequency band and that operates at a low power voltage can be accomplished. Using a differential amplifier having a high gain and a wide frequency band, a comparator that operates at high speed and an A/D converter using such a comparator can be accomplished.

Abstract: An analog to digital conversion circuit for converting an analog input signal into a plurality of binary output bits includes an operational amplifier and an integrating capacitor for storing a charge proportional to the integral of the input signal. A charge subtracting circuit removes a first predetermined charge from the integrating capacitor when an output charge of the operational amplifier is substantially equal to a second predetermined charge. The first predetermined charge level is removed from the integrating capacitor a number of times. The removal of the first predetermined charge from the integrating capacitor allows the integral of the analog input signal to be larger than a maximum charge capable of being stored by the integrating capacitor.

Abstract: A measuring apparatus has a sensor element that produces an output signal proportional to a variable to be measured. An integrator which, beginning at a starting value, integrates the output signal from the sensor element. A comparator is connected downstream of the integrator, compares the output signal from the integrator with a threshold value, and outputs an output signal corresponding to the result of the comparison. A reset device that is likewise connected downstream of the comparator and resets the integrator to the starting value at specific times. This is a simple way of achieving integrability in autonomous modules.

Abstract: A reference generator includes a memory that stores reference data which, when clocked out of the memory, produces an ATSC compliant VSB reference signal substantially free of sub-harmonics of the clock signal. A digital-to-analog converter converts the clocked out reference data to an analog signal. The analog signal may be at low IF. An up converter is arranged to upconvert the output of the digital-to-analog converter to an RF reference signal. The RF reference signal can be used, for example, to calibrate a VSB demodulator.

Abstract: An analog/digital converter including an amplifier (1) wired as an integrator, a comparator (2) electrically downstream from the integrator, a time counter (6) which continually counts the pulses of a pulse generator (5), a bistable element (4), and additional circuitry. The bistable element (4) drives the input network of the amplifier (1) with at least one switch (3) in such a way that in one of its two positions (“off” condition) a current Ix proportional to the analog measured value is integrated, and in the other position (“on” condition) a constant reference current Iref with opposite polarity to the current Ix is integrated in addition to current Ix.

Abstract: An analog-to-digital or digital-to-analog system contains a converter (706). The converter is supplied with a clock signal (CLK1) at a frequency fs derived from a crystal of a frequency fs/N. The frequency fs is derived from the fs/N crystal frequency by using an edge-triggered clock multiplier 705 which multiplies the crystal frequency by the factor N. The result is a low-cost clock solution that incorporates clock jitter around a localized frequency of fs/N. Sigma delta processing circuitry (702) is then used to place a null (e.g., low gain area) in the quantization noise at the same frequency where clock jitter noise is high in order to cancel the adverse cumulative effects of these two types of noise.

Abstract: An object is to obtain an A/D converter with improved A/D conversion accuracy. The resistor elements (R) and (R) are connected through wiring (L10) (2×L11, L12, 2×L13) mostly with two resistor elements left therebetween. For example, the resistor elements (R1) and (R2) are connected through the partial wiring (L11) and (L13) extended to the left in the diagram, and the resistor elements (R3) and (R4) are connected through the partial wiring (L11) and (L13) extended to the right in the diagram. Thus all of the wiring (L10) connecting electrically adjacent resistor elements (R) and (R) are formed of a combination of partial wiring {2×L11, L12, 2×L13}.

Abstract: A signal value representing method in which both wide dynamic range and high precision can be realized in combination with a low power source voltage. M+1 signal lines are used of which, M signal lines are digital signal values and one signal line is an analog signal value. The range of the values represented by the analog signal value representing method is equated to the smallest value of the digital signal value representing method. The signal value is represented by the combination of a discretely changing wide dynamic range signal, represented by the digital signal value representing method employing M signal lines and a continuously variable high precision signal which is represented by the analog signal value representing method employing a sole signal line and which represents a signal level position within the interval of the discrete values.

Abstract: An analog to digital (A/D) converter system and method which provides improved resolution and reduced noise for integrating-type ADCs, including dual slope, multi slope, and sigma-delta type A/D converters. After the ramp-up interval of either a dual slope or multi slope integrating A/D converter, the ramp-down interval occurs, wherein a reference signal is then applied to the integrator to return the integrator to its original value. The clock cycles are counted while the reference voltage is applied to determine a primary slope count value. During the ramp-down interval, while the reference voltage is applied, two or more integrator voltages are measured. In one embodiment, a first integrator voltage is measured before the original value and a second integrator voltage is measured after the original value, e.g., before and after the zero crossing. The method then determines a fractional slope count based on the measured two or more integrator voltages, i.e.

Abstract: A method and arrangement for converting an analog input signal into a digital output signal. The analog input signal is converted into a duty cycle modulated square wave. For reducing the communication rate of the digital output signal a time frame of subsampling periods is created and, within each subsampling period, the position of samples, which approximately coincide with the transients of the square wave, is determined. The invention further provides an image sensor comprising a plurality of such arrangements.

Abstract: A method is provided having the steps of receiving a first pixel signal; generating a first set of bits representative of the first pixel signal; receiving a second pixel signal; and, generating a second set of bits representative of a difference between the first pixel signal and the second pixel signal. An apparatus and system for performing the above method is also provided.

Abstract: A method of measuring capacitance is provided in which measurement speed is increased by as much as two orders of magnitude by optimizing timing parameters to rapidly charge and discharge the capacitor in small increments about an equilibrium voltage. The capacitor is charged at a linear rate by applying a predetermined constant current thereto, and discharged at an exponential rate determined by the RC time constant in the discharge path. Incremental charge and discharge times are selected in such a manner that results in an equilibrium voltage at a point where the charge voltage ramp and discharge voltage curve would cross if they were superimposed on one another. By appropriate selection of the incremental charge and discharge times, the equilibrium voltage may be conveniently established at a point well within the range of a measuring analog-to-digital converter (ADC). The voltage difference over the incremental charge time may be measured on one cycle and utilized to compute the capacitance value.

Abstract: A high accuracy, high speed, low power analog-to-digital conversion method and circuit. An input signal is sampled and the sample is compared to a scan signal whose amplitude varies with time. A time-to-digital conversion of the sample is obtained. At least two reference signals are also provided which are compared to the scan signal. Time-to-digital conversions of the reference signals are also obtained. The digital value of the sample is determined with reference to the known mathematical description of the scan signal, the time-to-digital conversions and the reference signals. The method and circuit may be employed in stages, where in a first stage, the most significant bits are determined and in a second stage, the least significant bits are determined.

Abstract: An apparatus comprising a charge pump configured to receive an input signal and to output incrementally a fixed amount of voltage for every selected edge of the input signal, an analog buffer coupled to said charge pump, the analog buffer feeding back a second voltage to said charge pump, the output of the charge pump linearly increases as a function of the fixed amount of voltage. A low power ramp generator that is created thereby may be used in analog to digital converters which are employed in devices such as imaging systems.

Abstract: A new method of presenting audio information is disclosed, wherein changes in amplitude and changes in frequency in two channels (stereo) has the additional parameter of phase information added to re-create the feeling of a live performance. Also, all three parameters are converted into duty cycle modulation of a high frequency digital pulse. Conventional loudspeakers and the brain decode the signal to provide audio signals that contain more information than simply frequency and amplitude changes as a function of time.

Abstract: An analogue to digital converter system for digitizing a stream of analogue symbols, the analogue to digital converter system includes an analogue to digital converter for sampling the symbols at predetermined sample timings and a feedback loop for adjusting the sample timings. The feedback loop includes an eye opening detector connected to an output of the analogue to digital converter and responsive to successive digitized symbol samples to determine eye opening signals. The eye opening detector includes a deviation detector for determining a deviation signal representative of a deviation of a digitized symbol sample value with respect to a mean sample value. Preferably, a variance measurement calculator calculates the variance of these deviations. A feedback control is responsive to successive eye opening signals to generate timing control signals for adjusting the sample timings.

Abstract: The A/D converter realizes a high-rate and high-precision A/D conversion using amplifier circuits. Each amplifier circuit amplifies a difference between the voltage of an analog signal to be converted and a predetermined reference voltage. Each bank of holding circuits holds the output signals of an oscillator circuit, the levels of which signals are variable with the passage of time, when the output voltage of the associated amplifier circuit exceeds a predetermined value. The signals held in each said bank of holding circuits are output as a value representing the amplification time of the associated amplifier circuit.

Abstract: An analog-to-digital converter utilizing pulse width modulation and ramp and count techniques. A microcontroller generates the pulse width modulated digital signal which is converted into a floating triangle. When the floating triangle signal is equal to the analog, input signal, a comparator generates and output which is sensed by the microcontroller. During an initialization process, the microcontroller uses information with respect to the timing of the comparator output to adjust the duty cycle so that the triangle wave remains within maximum and minimum levels above and below the analog, output signal. Calculation of the voltage, of the input signal is made as a function of the timing of the comparator outputs on successive upward ramps of the floating triangle signal, and of the slope of the upward ramp signal. As a result, the analog-to-digital converter utilizes the same process for low and high resolution measurements, thereby significantly decreasing its cost and increasing its speed.

Abstract: A time-to-digital converter starts a ramp signal generator when a trigger signal is received. The ramp signal generator outputs a signal with a substantially constant slope. The output of the ramp signal generator is sampled at two or more reference points. The sampled amplitudes and times at which the samples are taken are stored. An extrapolater calculates the time at which the ramp signal started from the stored amplitudes and times of the samples. Alternatively, the output of the ramp signal generator may be sampled at a periodic rate in which case only the sampled amplitudes and the time of the first sample are stored. In this manner, the time of the trigger signal can be accurately detected without the need for multiple reference signals.

Abstract: A digital waveform generator reads out simulated .DELTA..SIGMA. ADC data for a desired periodic analog waveform from a memory and converts it, using a low-resolution high speed DAC, into a synthesized analog waveform. The .DELTA..SIGMA. digital waveform generator is preferably designed to take advantage of the natural evolution of device technologies. The memory is fabricated with older technologies, which tend to be slower but have a much higher integration. The DAC is implemented in more recent technologies, which are faster but have less integration. A speed up buffer or buffers in intermediate speed intermediate integration technologies may be included to provide a bridge between the low speed memory and the low integration DAC.

Abstract: A differential mode time to digital converter uses a pair of symmetric capacitors and a pair of constant currents to generate two charging curves with the same characteristics. By charging the capacitors at different timings to produce a voltage difference between the capacitors, and then holding and amplifying the voltage difference, a relationship between time and the digital signal is obtained, thereby reducing the effects of temperature on the electronic element and providing a high noise immunity, short conversion time, and high linearity.

Abstract: A multi-range analog-to-digital converter for encoding rundown times into a single channel of pulse width encoded data which may be conveyed to a remote equipment room over a single inexpensive, low quality digital cable. An input charge pulse is divided into multiple charge pulses and rundown times of the divided charge pulses are combined and encoded into a single channel of encoded data. A digital value representation of the input charge pulse is derived from the most accurate rundown times selected from the single channel of encoded data.

Abstract: A process for the analog/digital conversion of an electric signal as well as a device for implementing the process is described. The process according to the invention provides that the time (T.sub.H, T.sub.L) be determined, which, starting from a voltage (U.sub.X) to be converted is necessary to charge up a RC component (10, 12) to a predetermined reference voltage, for example a switching threshold (S.sub.H, S.sub.L) of a comparator (14) or to discharge it. The device according to the invention provides that a selector switch (13), the comparator (14) as well as a time detector (15) are components of a microprocessor (17), which is wired with the RC component (10, 12) as well as with an input resistor (11) if necessary. The process according to the invention as well as the device according to the invention are particularly easy to realize and are suitable for use especially with a microprocessor (17) which does not have an integrated analog/digital converter.

Abstract: In a measurement device, a detector output signal indicative of a condition magnitude, e.g., radiation, pressure, temperature, etc, and a ramp signal are added, and the resulting analog summation signal is converted to a digital signal. The digital signal is sampled, integrated, and averaged over a sampling time corresponding to a predetermined sampling number, such as to achieve a condition measurement signal having reduced analog-digital conversion error.

Abstract: A pulse width modulation analog to digital converter can accommodate both wide band AC analog input signals and DC analog input signals. If the frequency of the input signal is much higher than the conversion rate of the PWM analog to digital converter, then the output digital pulse is of constant width versus the analog input signal amplitude. If the frequency of the analog input signal is lower than the conversion rate, then the output digital signal is a train of variable width pulses whose width tracks the amplitude of the analog input signal.

Abstract: A band-pass sigma-delta modulator includes a translator for tuning to a selected signal passband within the tuning range of the modulator. In a network implementation, the translator is integral with each integrator associated with the sigma-delta modulator(s). The translator can comprise a network having a transfer function defined in the Z-domain as (Z.alpha.-1)/(Z-.alpha.), where -1.ltoreq..alpha..ltoreq.1 defines the tuning. The value of .alpha. is defined as .alpha..tbd.cos(2.pi.f.sub.gm /f.sub.s), where f.sub.gm is the geometric mean frequency of the passband and f.sub.s is the input sample frequency of the sigma-delta modulator(s). The invention can benefit many signal processing applications such as, for example, A/D, D/A and D/D converters; and digital communication systems including digital radio and digital TV. In digital communications (e.g., radio, TV, etc.

Abstract: There is disclosed an integrated circuit in accordance with an illustrative embodiment of the present invention, method of operating a digital converter includes a capacitor on which a sampled analog signal is stored. The capacitor has a first element and a second element. The second element is capable of being referenced to more than one potential. The analog-to-digital converter includes a voltage gradient and a comparator for comparing the sampled analog signal to selected voltages of the voltage gradient to indicate which is larger. Each of the voltages developed along the voltage gradient corresponds to a digital code representative of the voltage.

Abstract: Pulse signals indicating up or down of a time constant are received and counted. When a time-out occurs, a time constant change signal is output. At up counting, when input signal is low, the flip-flop 80 of each bit is forcibly set to 1. Then, an up counter consisting of the high-order two bits (control bits) is provided. A time constant of a variable integrator is changed in response to output of the high-order two bits, so that the time constant can be changed rapidly. On the other hand, if the input signal is high, a 5-bit down counter is provided. Thus, the time constant of the variable integrator can be changed gently.

Abstract: In a conventional sigma-delta converter/modulator, quantisation noise of the quantiser which produces the digital output is suppressed because of a feedback loop which feeds an error signal via a filter to the quantiser, the error signal being the difference between the digital output and the input. Improved noise suppression is achieved by more filter stages, but such converter/modulators require special measures to reset them in the event of an overload i.e. a high input signal. A modified output is taken from the filter which is such that a second filter appears, when the main loop is not overloaded, to be in a loop with a simple delay, i.e. a sigma-delta circuit. The main loop has the inherent recovery properties of a second order modulator/converter and cannot be swamped by the signal from the second loop because of a limiter and, when the main loop has recovered, so does the second loop containing second filter. However, the quantisation noise is now suppressed by the combined filters.

Abstract: A measuring probe measures a parameter with a sensor. The sensor provides a sensor output signal related to a measured value. An amplifier section receives the sensor output signal and provides an amplifier output signal. An integrator has an input and an integrator output related to an integration of the input. Switching circuitry receives the amplifier output signal and a reference signal and has an output connected to the input of the integrator. Controller circuitry coupled to the switching circuitry connects the amplifier output to the integrator input during a sampling time, and the reference signal to the integrator input during a conversion time. The conversion time is related to the sensor output signal and is measured to obtain a digital representation of the sensor output.

Abstract: Analog-to-Digital Converter (A/D converter) consisting of several continuously integrating charge balancing (CB) conversion stages. During each conversion interval, all CB capacitors are discharged by a reference current. In each stage, the end of the discharge of the CB capacitor is detected by a zero crossing detector. Time intervals between the zero crossing events and corresponding discharge termination events represent time equivalents of quantization errors. Each stage, other than the first, converts the time equivalents of quantization errors of the previous stage. Output of the entire multistage A/D converter is combined from the outputs of all stages in a way which provides compensation of a quantization error of any stage by the output of the next stage. Quantization noise (sequence of quantization errors) of the entire A/D converter becomes the same as the N-time differenced (N-number of stages) quantization noise of the last stage.

Abstract: Disclosed is an integrating analog-to-digital converter characterized as a function of the temperature. The characterizing information is processed in a manner to correct the digital information before the digital information is subsequently processed by other system processors.

Abstract: A pulse circulating circuit includes inverting circuits each for inverting an input signal and outputting an inversion of the input signal. A time of signal inversion by each of the inverting circuits varies in accordance with a power supply voltage applied thereto. One of the inverting circuits constitutes an inverting circuit for starting which is controllable in inversion operation. The pulse circulating circuit circulates a pulse signal therethrough after the inverting circuit for starting starts to operate. An input terminal subjected to an analog voltage signal is connected to power supply lines of the respective inverting circuits for applying the analog voltage signal to the inverting circuits as a power supply voltage fed thereto. A counter serves to count a number of times of complete circulation of the pulse signal through the pulse circulating circuit.

Abstract: An integrating D-A/A-D converter includes a reference value generation circuit for generating at least one reference value relating to voltage or current, a control circuit for carrying out switching between a digital or analog input and the reference value every predetermined time to connect a switched one to thereby control an integral time, and an integration circuit for respectively integrating an analog value corresponding to the digital or analog input and the reference value switched in sequence every predetermined time and delivered through the control circuit to output an integral value for providing a digital or analog output.

Abstract: A current integrating analog-to-digital converter includes a comparator having a non-inverting input coupled to receive a ground voltage and an inverting input coupled to an input conductor, with an input current flowing through the input conductor, an integrating capacitor having a first terminal coupled by an isolation switch to the input conductor. A reset circuit is coupled to the integrating capacitor and is operative to reset the integrating capacitor before each integrating cycle. A digital-to-analog converter, which may be a CDAC, has an output coupled to a second terminal of the integrating capacitor, which may constitute the capacitors of the CDAC. An input of a tracking circuit is coupled to an output of the comparator to produce digital signals on digital inputs of the digital-to-analog converter to maintain the input of the comparator close to a virtual ground voltage, a digital signal on the inputs of the digital-to-analog converter representing the integral of the input current.

Abstract: Analog-to-digital (AID) converters with power line frequency noise rejection by synchronization of the converter clock with the power line frequency through a phase locked loop. Both sigma delta and integrating A/D converters may use the synchronized clock to precisely reject power line frequency noise.

Abstract: The difference between the output current of a voltage-current converter circuit and the output current of a local D/A converter circuit 2, whose output current is controlled by a feedback signal, is integrated by an analog circuit of which one end is connected to a DC potential point, and the voltage obtained by the integration thereof is quantized by a quantizing circuit. The result is integrated by a digital integrating circuit and is fed to a feedback correcting circuit 6 and, further, the result of A/D conversion is output. The feedback correcting circuit outputs a temporary feedback signal while the digital integration is being operated based on the output of the quantizing circuit. After the digital integrating operation completes the digital integration operation, a corrected feedback signal is generated instead of the temporary feedback signal. The signals inputted into the analog circuit 3 are continuously sampled even while the digital integration operation is being carried out.

Abstract: A filter processing unit 2 receives the output of an oversampling-type analog/digital (A/D) converter circuit 1. Predetermined information is acquired by a compensation circuit 3-1 with predetermined timing from the filter processing unit 2 in the course of processing for producing a filter output for a predetermined integration-phase state and the predetermined information is fed back to the filter processing unit 2 as compensation information representing a difference in magnitude between a filter output with an integration phase lagging behind or leading ahead of the predetermined integration-phase state and a filter output with an unchanged integration phase in order to produce a controllable-phase filter output DMout. The timing for the acquisition of the compensation information by the compensation circuit 3-1 is controlled by a control circuit 7-1.

Abstract: An analog-to-digital converter operates according to the multiple ramp procedure with continuous integration of the input signal in a charge storage or charge summation circuit, whereby downward integration is performed at periodically recurrent time intervals with the aid of a comparator circuit at the output of the charge storage or charge summation circuit, a logic circuit, a clock oscillator, a switching circuit, a first reference signal and a second reference signal. Hereby the duration of the switched-on state of one of the reference signals is a measure for the input signal. The transfer function of the quantization noise H.sub.q (z) with an n-th order (n=1,2,3, . . . ) high pass filter characteristic can be derived from a transfer function H(z) describing the specified configuration.

Abstract: A digital integrator (22) reduces circuit area and power consumption by implementing a two-stage integration for a decimator with only one adder (51). In the z-domain, he transfer function of a two-stage integrator can be expressed as H(z)=(1/(1-z.sup.-1)).sup.2. Expanded, the transfer function is expressed as H(z)=(1/(1 -2z.sup.-1 +z.sup.-2)). The inverse z-transform yields the expression y[n]=x[n]+2y[n-1]-y[n-2], which can be implemented with a single adder (51) and two delay portions (52, 55 and 53, 54). In one embodiment, a three-stage integrator (22) can further be implemented within a single adder circuit (91) by time-multiplexing an addition required for the two-stage integration with an addition required for a one-stage integration inside the adder circuit (91).

Abstract: An analog-to-digital converter (ADC) generates multiple analog waveforms, preferably as voltage ramps, that progressively increase in signal value over time but at different rates of increase. The ramp with the greatest slope is initially compared with an input signal sample until the ramp exceeds the sample, at which time the system switches to the ramp with the next greatest slope for comparison with the input. The operation then repeats, with the system switching to the next lower ramp each time the current ramp exceeds the input. Both the number of ramp switching events that occur during a sample cycle, and the clock count at the time of the most recent ramp switch, are recorded and used respectively as the most and least significant bits of a digital output. The switching event count proceeds from an initial maximum value from which it subtracts at each switching event, while the clock count builds up from an initial minimum value.

Abstract: The method of transmitting analog signals in digital from resides in converting the analog signals to be transmitted into two digital signals, the duration of which is proportional to the analog signals and to their full-scale value, respectively. The so transmitted information is reconverted into the original value by simply calculating the ratio of the duration of the two digital signals.

Abstract: An A/D converter system has an A/D converter element (10) which provides a first predetermined number of digital output bits for each input analog signal. An addition device (12,70) adds linear slope potential to the input analog signal. A calculator (14) provides an average of a plurality of digital output signals of the A/D converter element so that the average has larger number of bits than the first predetermined number. The addition device is implemented by a time constant circuit (70) which functions as an integral circuit for an input analog signal, and functions as a differential circuit for a slope potential.

Abstract: Method and apparatus for converting an analog input voltage signal (preferably in the form of a low-frequency rectangular voltage) to a digital output signal proportional to the input voltage. The input voltage is integrated to the integrator voltage over a certain integration time. After the expiration of the integration time, the integrator voltage is de-integrated to zero over a de-integration time by a reference voltage and the input voltage is found from the ratio of de-integration time to integration time, multiplied by the reference voltage. During the integration time, modulation pulses, preferably derived from the reference voltage, are superimposed on the input voltage and thus the integrator voltage is influenced, so that a given integrator voltage is obtained regardless of the input voltage.

Abstract: The present invention provides an analog to digital converter including an integrator for charging and discharging a capacitor according to two currents of opposite direction containing a component of the analog input signal which is continuously connected. Also, a control circuit periodically switches on one current which remains until the integrator output reaches a reference level at which time the opposite direction current is switched on. A number of such cycles forms an integration period closely approximating a predetermined period. The control circuit measures the total amount of time of the integration period and also the accumulative amount of time that current flow is in a predetermined direction. From these two times, a digital representation of the analog input signal is calculated. The next integration period begins at the end of the previous to achieve a maximum conversion rate for a given integration period.

Abstract: Analog-signal integrators are described that have a transfer function containing a composite parameter that is the product of two parameters each of which is separately changeable, via application of digital programming signals. In a continuous analog-signal integrator the integrating capacitor is a programmable capacitor array, preceded in the feed back branch with a programmable voltage divider. In a discrete-time analog-signal integrator the integrating resistor is a switched-capacitor resistor including a programmable capacitor array that is preceded in the input circuit branch by a programmable voltage divider.