Abstract: A delta-sigma modulator is provided with a multi-stage shift register coupled to receive as its input the output from a quantizer including an analog integrator. The serial digital output signal train from the shift register is fed back to the input of the integrator and because of the frequency division which takes place, for a given high clock rate, an operational amplifier with a lower gain/bandwidth product may be employed. The invention also includes a signal processor coupled to the output of the delta sigma modulator and which is arranged to provide an adaptive window based, decimation cycle whose exact timing is data dependent. The adaptive windowing process implemented in a microprocessor-based signal processor allows the first occurrence of a proper polarity state transition occurring during a window period to become the termination point of the computation cycle rather than providing a fixed time interval.

Abstract: A tuning circuit (10) and method of operation for tuning an analog filter (40). The tuning circuit (10) has an integrator with an input portion (12) and a comparator portion (14), a counter (32), and a decoder (34). The integrator is implemented with an RC time constant which is proportional to an RC time constant of the analog filter (40). The comparator portion (14) provides an enable signal during the RC time constant of the integrator to the counter (16) which quantizes the RC time constant relative to a clock period of the counter (16). A predetermined decoding is performed to provide an output control signal to control adjustment of the RC time constant of the analog filter (40).

Abstract: An analog-to-digital converter converts multiple analog signals to multiple digital signals during a single conversion period. The converter comprises a multiple input integrator stage which provides an output voltage that is selectively compared to a multiplicity of voltages. The comparison voltages include reference voltages and additional signal inputs. A plurality of UP counters measure the number of clock pulses generated by a clock generator and enable the calculation of the output function.

Abstract: An over-sampling analog-to-digital converter using a current switching circuit 102 as a local digital-to-analog converter, wherein a difference between the output currents Isig and Iq of a voltage-to-current converter circuit 101 and a current switching circuit is integrated by a capacitor 105 of which the one end is grounded to a dc potential VB. Further, the current switching circuit 102 has many bits to decrease the difference current between the signal current Isig and the feedback current signal Iq. Moreover, the level-shifting function of the voltage-to-current converter circuit 101 makes it possible to apparently subtract the dc component from the input analog signal Vsig which is produced based on an internally generated dc voltage as a dc bias voltage, and to decrease a change in the voltage between the electrodes of a capacitor caused by the integration of current.

Abstract: A delta modulator automatically adjusting the slewing rate is disclosed. In the absence of a transition in the output data of a delta modulator, the current used for the integrator of the delta modulator is increased. When the comparator of the modulator indicates that the feedback signal of the modulator has overshot the input signal, the current is decreased or reversed until the two signals are approximately equal as signalled by a 50% duty cycle.

Abstract: A dual-ranked time-interval conversion circuit. Two time trap circuits are employed to convert the time interval between a logic level transition of a first signal and a logic level transition of a second signal to an analog or digital signal representative of that time interval. Each time trap circuit employs a delay line for receiving and propagating the first signal and a series of taps and respective storage elements along the delay line for detecting and storing the logic level of the delay line at each tap at the time of receipt of a second signal. A first time trap circuit is employed to measure the time interval in course quanta of time and a second time trap circuit is employed to measure in fine quanta of time the time difference between the actual first signal-to-second signal time interval and the coarse measurement of that interval.

Abstract: A multislope A/D converter is presented which employs a multislope integration technique enabling the use of a single comparator to detect polarity changes in the integrator output voltage. The run-up interval of the integrating A/D converter is controlled by a four-step pattern that is repeated as many times as is required in order to keep the integrator output voltage within the confines of a preselected voltage range. During the first step of the four-step pattern, a positive reference charge is applied to the integrator. In the second step, a decision is made as to whether to either maintain the application of the positive reference charge to the integrator or to change over to the negative reference charge. The decision is determined such that the reference charge causes the integrator output voltage to move toward or through a preselected target voltage range.

Abstract: A precision sigma-delta analog-to-digital converter disposed to operate at a sampling rate giving rise to a relatively low oversampling ratio is disclosed herein. The high-order sigma-delta analog-to-digital converter (10) of the present invention is operative to convert an analog input signal to a digital output sequence. The inventive converter (10) includes a first integrating network (14) for generating a first sampled analog signal (X.sub.1) in response to the analog input signal. A second integrating network (18) generates a second sampled analog signal (X.sub.2) in response to the first sampled analog signal (X.sub.1). A third integrating network (22) generates a third sampled analog signal (X.sub.3) in response to the second sampled analog signal (X.sub.2). The sigma-delta converter (10) of the present invention further includes an internal quantizer (24) for generating the digital output sequence in response to the third sampled analog signal.

Abstract: A delta sigma analog-to-digital (A/D) converter includes a digitally-controlled multiplying digital-to-analog converter (MDAC) in a feedback configuration. The MDAC is driven by a digital signal obtained from the output (or an intermediate output) of the A/D converter. An incremental feedback quantum to the first stage integrator is a function of the input values that immediately precede it. In the most general implementation, a table look-up permits an arbitrary relation between the input values and feedback quantum size. In another implementation, the A/D converter output (or intermediate output) signal drive the MDAC and the compression curve of the A/D converter bears a square-root relationship to the input analog signal; a linear relationship is restored by squaring the output signal. In a third implementation, the MDAC is driven by a digital signal obtained from the output (or an intermediate output) of the A/D converter together with an added small positive constant number.

Abstract: An integrated A/D converter includes an integrator 8integrating reference signals in synchronism with an integration start signal, and counters for counting integrating clock pulses until the integrated value of the integrator reaches a value corresponding to an input signal, thereby to convert the input signal into a digital or analog signal based on the counts of the counters. An AND gate supplies the integrating clock pulses to the counters only during a predetermined period in synchronism with the integration start signal, so that the integrating clock pulses are supplied to the counters only during an integrating period for the reference signals.

Abstract: An automatic reference voltage controller of an integral A/D converter comprises a reference voltage switching circuit, an input voltage switching circuit, a Miller integrator, a comparing circuit, a logic circuit, and an automatic reference voltage control means for reducing the output error of the integral A/D converter. According to the present invention, the error of the digital output signal due to the limit error of the integral A/D converter can be reduce by automatic control of the reference voltage.

Abstract: A voltage-to-frequency converter provides an output signal, the frequency of which is proportional to the instantaneous level of a reference-frequency signal, which is proportional to the output signal of a parameter-sensing circuit. An up-down frequency counter counts the output pulses of the voltage-to-frequency converter. An up-down control terminal coupled to the reference-frequency signal switches the counting direction of the up-down counter to demodulate the output signal of the voltage-to-frequency converter and to provide a digital output signal representative of the time integral of the amplitude of the parameter being sensed.An undersired input signal is reduced by subtracting a cancellation signal having the format of the undesired signal from the undesired input signal. The filter includes a subtractor, or difference circuit, the output of which is coupled to a voltage-to-frequency converter.

Abstract: A multislope continuously integrating analog-to-digital converter for converting an analog input signal into a digital output signal where the converter employs an integrator for continuously integrating the input signal in relation to a series of reference voltages of increasing magnitude and a zero crossing detector to determine when the reference voltage has completely discharged the integrator. A counter or the like is employed for timing the duration of the discharge which corresponds to the digital equivalent of the analog input signal.

Abstract: An analog-digital converter having an analog integrator which integrates the difference between the analog input signal and a signal from, for example, a digital-analog converter controlled by a microprocessor, whereby a high resolution and a very high operating speed are rendered possible with a relatively low degree of complexity and minimal noise.

Abstract: A high resolution and high speed analog to digital converter for use with a transducer in measuring parameters such as weight, which may stay the same or which may change in the system, the converter having an integrator which integrates for a fixed period the output voltage from the transducer, and subsequently deintegrates a known reference voltage, the deintegration times varying depending upon the magnitude of the transducer output voltage which has been integrated, a comparator comparing the deintegration times of successive conversions and shortening the integration times for the transducer output so as to obtain more conversions per time period to provide a high speed readout when the transducer output is changing, but lengthening the integration times to provide a high resolution readout when the comparison of deintegration times does not reveal any change in the transducer output.

Abstract: An integrating voltage-to-frequency converter and method for converting a DSB-SC signal into a frequency-encoded signal. The DSB-SC signal is demodulated using an up/down counter, the count direction of which is alternatively switched in synchronism with the phase polarity of a reference carrier signal for the DSB-SC signal. The converter includes an integrator, a comparator, and means for rebalancing the integrator circuit. Means for tracking and storing a partial-bit analog signal level at the output of the integrator are provided, where the partial-bit analog signal level is obtained just prior to a phase transition of the reference carrier signal. The count of the up/down counter is corrected thereby to account for the partial-bit analog signal information.

Abstract: A transducer-system that corrects the actual output of each transducer (11) in the system so as to approximate a desired transducer output, i.e., one where the measured variable such as pressure is directly proportional to the actual physical variable. A connector (15) to each transducer (11) includes special calibration indicators for identifying any innacuracies in its output signal, and monitoring and correction circuitry (13) is selectively attachable to any of the transducers (11), to read the calibration indicators and appropriately adjust the transducers output signal, thereby correcting the identified inaccuracies. A preferred form for the calibration indicators is a set of eight resistors (R1-R8). Subsets of this set correct for zero level, span, and linearity of the transducer (11).

Abstract: A continuously integrating analog-to-digital converter (ADC) calculates a digital output by integrating an input voltage over a number of time intervals using a multisloping technique to define the input voltage in terms of a slope count. A residue ADC is used in lieu of a run-down interval of the integrator to calculate the least significant bits of the ADC digital output. This is accomplished by first sampling the integrator output voltage, and then after a number of time intervals, sampling the integrator output voltage a second tune. The difference between the two residue voltages is converted into a fractional slope count by multiplication with a calibration constant. The fractional slope count can then be added to the slope count from the integrator, so that the resulting total slope count is directly proportional to the input voltage at a high resolution.

Abstract: A current-integrating analog-to-digital converter includes a comparator having a non-inverting input coupled to a ground voltage and an inverting input coupled to an input conductor carrying an analog input current. An integrating capacitor having one terminal coupled to the input conductor and another terminal coupled to an output of a digital-to-analog converter. A tracking circuit is coupled to an output of the comparator to apply digital signals to inputs of the digital-to-analog converter to maintain the inverting input close to a virtual ground voltage. A digital filter filters the digital signals to produce a digital output signal that precisely represents the input current.

Abstract: Integrating analog to digital converter operating according to a multiple ramp procedure and having a charge storage or charge summation circuit which continuously up-integrates an input signal and which by means of a following comparator, a logic circuit and reference currents or reference voltages, down-integrates during periodically recurrent time intervals, the instants being defined by an oscillator, a timebase counter and a bistable stage. The time between two successive such instants being called a submeasurement. At the imput of the charge storage or charge summation circuit used for the input signal or at one its other inputs, convergence accelerating signals are superimposed after every nth (n=1,2,3, . . . ) submeasurement to provide for strongly enhanced convergence range and for shorter convergence period, and these convergence accelerating signals having Taylor series expansions according to time in the time interval of a submeasurement which are first or higher order polynomials.

Abstract: An improved high order interpolative oversampled (sigma delta) analog-to-digital converter network including a plurality of cascade-coupled integrator stages is formed on a single integrated circuit chip in a manner that conserves power and chip area. Each integrator stage includes a differential amplifier, at least one input capacitor and at least one feedback capacitor. The power dissipation and occupied chip area are minimized by down-sizing the chip area occupied by the capacitors and differential amplifiers (op amps) in all but the first integrator stage. The high gain of the first integrator stage makes the noise contribution of subsequent integrator stages negligible so that the higher noise of the subsequent integrator stages is tolerable.

Abstract: An arrangement for integrating an analog voltage signal and for converting it into a corresponding digital signal, whereby during a measuring cycle, the analog signal is fed via a comparator to a counting circuit, which to provide the time-related control of the operation of the counter is connected to a variable clock frequency generator device controlled by the analog signal. The comparator is connected to a "D"-flipflop, which is connected to an up-down counter with a digital-to-analog converter, on whose counting input is provided the Q-output of the variable clock frequency generator, which changes its clock frequency according to the absolute value of the voltage to be integrated.

Abstract: Improved analog to digital and digital to analog signal processors are disclosed wherein a quick approximation of the input signal to the signal processor is attained and a more accurate approximation is later attained for the input signal. For the analog to digital conversion, a standard analog to digital converter having a finite resolution or a predetermined quantization error is used to create part of the digital representation. The remainder of digital representation is created by processing an error signal due to the finite resolution of a standard analog to digital converter and the infinite resolution of the analog input signal to a delta modulator. In a digital to analog signal processing circuit, the first part of the digital representation is converted by a standard digital to analog converter and the remaining portion is integrated into a frequency limited analog signal and then summed to reconstruct the analog signal.

Abstract: A process and arrangement for evaluating a measurable analog electronic quantity based on the principle of the timekeeping mechanism, in which the measurable analog quantity is digitalized by counting integration processes. To exploit the simplicity and precision of the timekeeping mechanism principle also far fast and precise digital data conversion units, a deviation coding phase (AV) is inserted between the timekeeping mechanism periods (T), in which post-adjustment of the timekeeping mechanism timing ratio is possible with rapid digital circuits even in the event of abrupt fluctuations of the quantity to be measured. The invention is generally applicable for highly precise and rapid digital data conversion of analog quantities, and is especially advantageous in high-precision measuring instruments with measuring sensors in bridge circuits, for example in weighing cells based on the DMS principle in electronic balances.

Abstract: An oscillation detect and reset circuit is provided for an analog modulator that includes a first stage of integration having a single ended differential amplifier (32) which is connected to the input of three stages of subsequent integration (40), (42) and (44), in a cascaded configuration. The output of the last stage of integration (44) is connected to the input of a one-bit quantizer (48). The output of the one-bit quantizer (48) is connected to the input of a current (50) feedback, which is connected between a summing node (36) and a negative voltage supply. The summing node (36) sums the current feedback with an input voltage for input to the amplifier (32). Switches (52), (54) and (56) are provided across the inputs and outputs of the integration stages (40), (42) and (44), respectively. The sensing of an unstable condition on the output of second stage of integration (40) is detected by oscillation detect comparators (60) and (62) to initiate a count cycle in a five-bit counter (66).

Abstract: An analog-to-digital converter employs a capacitor circuit for integrating a sample of an input signal during a predetermined interval of time and, thereafter, the capacitor is discharged at a predetermined rate until the integration voltage is equal to that of a reference. The discharge time serves as a measure of the amplitude of the input signal. A measurement interval is established which is equal to an integral number of cycles of each of the possible values of frequency of the A.C. excitation. The signal integration interval has a duration less than or approximately equal to the shortest period of the A.C. excitation, this being the period of the highest frequency A.C. excitation. The signal integration is repeated periodically at each third half-cycle of the highest frequency excitation so that the total integration time experienced during positive half cycles is equal to that experienced during negative half cycles of any of the plurality of excitation frequencies.

Abstract: An analog to digital converter for high-speed, high-accuracy conversion includes a charge storage means for storing an input analog value to be converted, means for controlling discharge of the charge storage means, a comparator means for sensing discharge level of said charge storage means and transmitting a stop signal at a precise time, a tapped delay line means which is responsive to a start signal to generate a sequence of binary values, a first register means responsive to the stop signal for capturing the binary values corresponding to a delay time between the start and the stop signal, and an encoder means coupled to the register means for converting the binary values to a digital value representative of the input analog value.

Abstract: A DSB-SC signal is demodulated using an up/down counter, the count direction of which is alternately switched in synchronism with the polarity of a reference carrier signal for the DSB-SC signal. The converter includes an integrator, a comparator and a charge-rebalancing current source to reset the integrator. Correction of the court value of the up/down counter is obtained by tracking and storing a partial-bit analog signal. The partial-bit analog signal corresponds to and is obtained from the output of the integrator just prior to the pahse transition of the reference carrier signal. A capacitor samples the partial-bit analog signal information and subsequently transfers that information to the integrator input. The transfer of a charge of twice the magnitude and opposite polarity to the integrator compensates for the partial bit analog signal as it is detected by the up/down counter. A digital system for converting the partial-bit analog signal to a binary code word is provided.

Abstract: A method for A/D conversion, which includes integrating by analog apparatus, amplifying and subsequently quantizing an analog input signal for producing a quantized signal having n bits, wherein n>1, and feeding back the quantized signal to the input signal. The improvement includes integrating digitally the quantized signal by an arrangement of periodic digital summation, converting the quantized signal into an analog signal, and feeding back the analog signal to the input signal. An apparatus for carrying out the method is also disclosed.

Abstract: An analog/digital converter includes a peak holding circuit for holding a peak voltage of input analog data and a peak time detecting circuit for detecting a point of time when the input analog data reaches a peak voltage. Also included is a constant current discharging circuit for discharging the peak voltage held in the peak holding circuit at a constant current from the peak point of time detected by the peak time detecting circuit. The converter also includes a zero time detecting circuit for detecting a zero point of time when a voltage held in the peak holding circuit is reduced to zero and a time to digital converting circuit for counting a number of pulses in a pulse line obtained by gating clock pulses during a period of time from the peak time detected by the peak detecting circuit to the zero time detected by the zero time detecting circuit, the time to digital converting including a counter to output digital data corresponding to the input analog data.

Abstract: An A/D converter included in an echo canceller or the like is furnished with a plurality of rate changing filters that receive the output signals of an oversampling A/D conversion circuit in common, the integration phases of the filters are different from each other as they are selectively advanced or retarded for each one of a plurality of predetermined intervals, and further furnished with an output selection circuit by which internal digital signals delivered as outputs from one of the rate changing filters are selectively transmitted according to the desired phase change.

Abstract: A signal level detecting circuit comprises an input terminal to which an input signal with level variations is applied, a level comparator operative to compare the level of the input signal with the level of a reference signal variable in level and to produce a comparison output signal having first and second levels in response to differences between the level of the input signal and the level of the reference signal, a control signal generator operative to produce control signals one of which is obtained when a period of time in which the comparison output signal has the first level is not longer than one of two different reference periods of time and the other of which is obtained when the period of time in which the comparison output signal has the first level is not shorter than the other of two different reference periods of time, a pulse generator operative to produce a pulse signal having its pulse duty factor varied in response to the control signals obtained from the control signal generator, and an

Abstract: An analog to digital converter comprises coarse (15, 16) and fine (24, 19) quantization. The coarse quantization is of the frequency-current type or frequency-voltage frequency type. The fine quantization measures the discharge period of a residual charge stored in an integration capacitor (3) at the end of the coarse quantization phase. The discharger of this capacitor includes a capacitor (14) for quantifying this discharge.

Abstract: An analog-to-digital converter includes a constant current source that alternately charges and discharges the capacitor between predetermined levels. The difference between the rate of charging and the rate of discharging of the capacitor provide information permitting a digital representation of the input signal. The single current source operates without change during the charging and discharging of the capacitor and has temperature compensation that eliminates potential errors due to instabilities in the ambient temperature.

Abstract: An analog-to-digital converter comprises an output generator for forming an output signal in response to application of a start signal; a comparator for comparing an analog signal, to be converted to a digital signal, with the level of the output signal formed by the output generator and for providing an output representing the time period from initiation of formation of the output signal to occurrence of a predetermined relation between the output signal and the analog signal; and a clock signal generator. The converter further comprises a digital computer that includes an output terminal from which the start signal is applied to the output generator and an input terminal for receiving the output from the comparator.

Abstract: An oversampling A/D converter having a pair of sample and hold circuits that alternately sample an input signal at high frequency and a pair of arithmetic circuits that determine the difference between a respective sampled and hold signal and a local analog signal. The difference signals are alternatively integrated and quantized into an output signal. The local analog signals are generated from the quantized output signal and supplied to the arithmetic circuit.

Abstract: The invention is for an analog-to-digital converter which is useful for audio applications owing to its insensitivity to noise. The converter achieves this insensitivity by utilizing a differential, common node integrator having a non-switching capacitive feed-back loop.

Abstract: Besides an input switched capacitor (14) for sampling an input analog signal into output electric charges, an oversampling analog-to-digital converter comprises an additional switched capacitor (47) for sampling, into additional electric charges in synchronism with the input switched capacitor, controlled electric charges produced by a capacitor array (24) which is coupled to a reference voltage source (23) and is controlled by a predetermined number of control signals produced by a control logic (22) in response to an output digital signal. A summing circuit delivers the output and the additional electric charges to an integrator (15) connected to a quantizer (21) which produces a quantized signal substantially identical with the digital signal. Preferably, the summing circuit comprises a connecting switch (49) for supplying the output and the additional electric charges to the integrator in synchronism with the input and the additional switched capacitors.

Abstract: An analog-to-digital converter is provided based on supplying various multiplexed inputs, including analog input signal samples, to a voltage-to-current converter charging and discharging an integrated capacitor. A comparator determines the status of this capacitor to a control counter to provide digital representations.

Abstract: A dual-slope A/D converter circuit has an oscillator (14) whose timing frequency is determined by the value of an oscillator resistor (70) and a oscillator capacitor (72). An integrator (66) integrates an input voltage at a rate determined by an integrating resistor (64) and an integrating capacitor (68). The oscillator resistor (70) and integrator resistor (64) are designed such that their ratio will remain constant despite variations in actual value due to manufacturing inaccuracies. The oscillator capacitor (72) and integrating capacitor (68) are similarly designed. Consequently, an optimum peak integration value can be obtained at full scale input despite variations in actual resistive and capacitive values.

Abstract: A method for generating an output stream of digital data words, with each data word representing the amplitude of an analog signal at one of a multiplicity F samples each second and with substantially equally spaced time intervals T therebetween, is obtained from a digital baseband demodulation system used for array beam forming. A data stream, formed of interleaved ADC output digital data words acquired from a set of converters, is at a rate of F total samples/second. Subsequent digital demodulation, filtration, and decimation provides digital output signals which need less delay resolution prior to the formation of coherent sum signals, thereby reducing overall channel memory requirements. The output baseband data stream has enhanced dynamic range, thereby reducing the ADC bit density requirements.

Abstract: An A/D converter apparatus comprises: a sampling signal generating means to generate an oversampling signal and an internal sampling signal; a converter means to convert an input analog signal into a digital signal in synchronism with the oversampling signal; and a decimator means to perform a specified decimation on the digital signal in synchronism with the internal sampling signal; whereby the sampling signal generating means maintains the frequencies of the oversampling signal and the internal sampling signal in a specified relationship.

Abstract: An addressable transducer interface which may be associated with a particular electrical transducer, comprises means (107) for storing correction data for the correction of errors as herein defined relating to that transducer so that on addressing of the interface by external control means, the correction data may be transmitted to the control means together with measurement data from the transducer. The storing means is arranged to store said correction data in digital form.

Abstract: There is provided a digitally controlled first order hold circuit and waveform synthesizer for digitally controlling the representation of a function over an approximation interval. In accordance with the operation of the invention, the first order hold circuit and waveform generator receives a digital data input signal which contains initial condition data, up/down data, and slope data for the approximation interval. The initial condition data is loaded into an up/down counter which is incremented using counting data at a rate depending on the value of the slope data and in a direction depending on the value of the up-down data. In order to minimize delays arising from data acquistion, two frequency synthesizer circuits are provided such that one frequency synthesizer provides counting data while the other frequency synthesizer receives slope data. During alternating intervals, the other frequency synthesizer circuit provides counting data while the other circuit receives slope data.

Abstract: A condition monitoring system for a vehicle comprises a central control unit and a plurality of remote data acquisition modules, each of the modules being connected to the central control unit over a single wire and having a plurality of inputs connected to local condition-sensing transducers. Each data acquisition module serves to store data representing signals received at its inputs. The central control unit prompts the modules in turn and each module, when prompted, transmits its stored data to the central control unit over the respective single wire. This system provides a simplification of the wiring and connectors required between the various transducers and the central control unit, which drives displays displaying the conditions of the transducers.

Abstract: The invention relates to a circuit and a method adapted for measuring and digitizing the value of a resistance. The circuit includes and A/D converter operating in accordance with a charge balancing principle, and a resistance network connected to the A/D converter so that the resistance is both a component of the A/D converter and of the resistance network. The A/D converter and the resistance network are interconnected in such a manner so as to permit only a purely resistive measurement. A processor is connected to the A/D converter for obtaining a composite measured resistance value from a plurality of individual measured resistance values. The method according to the invention permits accurate (or precise) resistance measurements having a high degree of resolution of an order of magnitude of 10.sup.5 points. The method is applicable in particular for temperature measurements, for examples in calorimeters or in precision scales, but also in other resistance measurements.

Abstract: A recirculating type analog to digital converter is disclosed which has an auto-zero mode that is introduced prior to each conversion cycle. The loop is based on an arrangement of operational amplifiers and FET switches, and further includes a comparator circuit, a reference voltage source and a microprocessor which are coupled to the loop. Also coupled to appropriate points in the loop are three time gated integrator circuits which generate analog signals which respectively compensate for offset voltages of operational amplifiers in the loop, the offset voltage of the comparator circuit which is coupled to this loop, and the gain of the loop. The compensating signals which are generated in the auto-zero mode are applied to the loop during the conversion cycle.

Abstract: An electricity metering transducer is disclosed which samples voltages and currents at an innerconnection terminal of an electrical energy distribution system, converts those samples to digital form and computes selected electricity metering quantities. In a multiphase system current and voltage signals are multiplexed to a pair of codecs, one for current signals and one for voltage signals. The period of the signals being sampled is detected and used to generate a substantially nonsynchronous sampling signal so that a sample migration system is created which provides a large number of samples of a composite wave form. The steps of a digitally generated stepwise approximation of a sawtooth waveform are summed with the sequential analog samples and then removed from the digital value of each sample by software operation in order to increase the resolution of the digital to analog conversion.

Abstract: Disclosed is a digital encoding apparatus related to CVSD techniques which provides an improved signal. The apparatus includes a comparator, comparing an analog input signal to a reconstructed analog signal and for generating the digital outputs in a manner similar to the CVSD technique. An integrating means, receives a slope control signal and the digital outputs to generate the reconstructed analog signal. The slope control signal, according to the present invention, is generated in a slope control means which includes means responsive to n digital outputs from serial clock cycles for generating an m-dimensional digital vector signal, and means responsive to the m-dimensional digital vector signal for generating the slope control signal. The m-dimensional digital vector signal is converted to an analog slope control signal by generating a scalar product of the m-dimensional digital vector signal with an m-dimensional weighting vector.

Abstract: An integration type D/A and A/D converter having improved linearity and low power consumption. Logic circuits such as ECL counters consuming a major part of power of the D/A and A/D converters are realized through CMOS process. Current source circuits, current switch circuit and comparator circuit of the integration type A/D converter are realized in IC through bipolar process ensuring high accuracy and low noise. Logic parts such as counter is realized through CMOS process.