Abstract: A liquid crystal display device includes a first substrate, a second substrate and liquid crystal. The first substrate includes pixel electrodes, a peripheral circuit and a dummy wiring. The peripheral circuit and the dummy wiring are provided outside a pixel area in which the pixel electrodes are arranged. The second substrate is opposed to the first substrate through the liquid crystal. The second substrate includes a translucent conductive film that is provided on an opposite side of the second substrate to a side where the liquid crystal is present. The dummy wiring is located on an outer peripheral side of the substrates than the peripheral circuit and is provided independently of the peripheral circuit in terms of circuit. The dummy wiring is grounded outside the first substrate.

Abstract: The present disclosure provides a GOA circuit and a display device. The GOA circuit includes a plurality of cascaded GOA circuit units. An n-th stage GOA unit configured to output an n-th stage horizontal scanning signal includes a pull-up control unit, a feedback unit, a first pull-up unit, a second pull-up unit, a third pull-up unit, a pull-down unit, a pull-down control unit, and a bootstrap capacitor.

Abstract: A gate driving circuit and a display apparatus comprising the same are disclosed, in which a maximum voltage level of a plurality of scan signals output from one stage circuit can be prevented from being deteriorated. The gate driving circuit comprises first to mth stage circuits, wherein each of the first to mth stage circuits includes a logic circuit portion controlling a voltage of each of a first control node and a second control node, a node boosting circuit boosting the voltage of each of the control nodes in accordance with boosting shift clock signals, a scan output circuit outputting each of first to ith scan shift clock signals as first to ith scan signals (i is a natural number of 3 or more) in response to the boosting voltage of the first control node, and a carry output circuit outputting carry shift clock signals as carry signals in response to the boosting voltage of the first control node.

Abstract: A gate-driver-on-array (GOA) circuit includes N GOA units cascaded in series to generate N sets of driving signals. Each n-th GOA unit includes a first terminal configured to receive a high-level voltage, a second terminal configured to receive a low-level voltage, and a clock signal terminal configured to receive a clock signal, an input terminal and a reset terminal respectively configured to receive internal signals from two alternative GOA units in the series, a first output terminal configured to output a gate-driving signal, and a second output terminal configured to output a node voltage signal. Each n-th set of the N sets of driving signals includes a first driving signal being a gate-driving signal from a (n?1)th GOA unit, a second driving signal being a gate-driving signal from a n-th GOA unit, and a third driving signal being a node voltage signal from the n-th GOA unit for driving an AMOLED pixel circuit.

Abstract: A display device includes a display panel, a display panel driving circuit, and a power management integrated circuit that generates driving voltages, receives driving set data from a timing controller, stores driving hex values corresponding to the driving set data in first internal registers, and determines voltage levels of the driving voltages based on the driving hex values. The power management integrated circuit divides the driving hex values into upper and lower decimal values, derives a result decimal value by applying the upper and lower decimal values to a first authentication-formula, generates a result hex value based on the result decimal value, compares an authentication hex value corresponding to authentication data received from the timing controller with the result hex value, and selectively operates in a normal mode or in a protection mode based on a comparison result between the authentication hex value and the result hex value.

Abstract: A shift register circuit includes a pull-up control sub-circuit, a pull-up sub-circuit and a shutdown auxiliary sub-circuit. The pull-up control sub-circuit is configured to transmit a voltage from the signal input terminal to the pull-up node under the control of the voltage from the signal input terminal. The shut-down auxiliary sub-circuit is configured to pull down a voltage of the pull-up node to a voltage of the discharge voltage terminal under the control of a voltage from the pull-up node. The pull-up sub-circuit is configured to transmit a voltage from the clock signal terminal to the first signal output terminal under the control of a voltage from the pull-up node. The first signal output terminal is configured to be connected to a gate line.

Abstract: A device is applicable to a display driver, including a sampling circuit and a logic circuit. The sampling circuit is configured to sample a command signal by recording a plurality of command values of the command signal at different times. The plurality of command values corresponds to at least one data line of a pixel circuit. The logic circuit is electrically coupled to the sampling circuit, and is configured to receive the plurality of command values. The logic circuit is further configured to generate a filtered command signal according to the plurality of command values, and is configured to provide the filtered command signal to drive the pixel circuit.

Abstract: The disclosure provides a shift register including a node controller configured to control charging and discharging of a node Q and a node QB, and an output circuit including a first buffer transistor configured to output a first scan signal, a second buffer transistor configured to output a second scan signal and a third buffer transistor configured to output a carry signal in response to electric potentials of the node Q and the node QB. The first buffer transistor and the second buffer transistor have different channel region widths. The output circuit may further include a first dummy buffer transistor having a common gate and common drain connection structure with the first buffer transistor.

Abstract: Disclosed are a display panel, a display device, and a method for driving the same. The display panel includes a plurality of data lines extending in a first direction, and at least one signal compensation line extending in a second direction, insulated from and intersecting with the plurality of data lines, a compensation capacitor is arranged at a position where the plurality of data lines intersect with the signal compensation line, and one terminal of the compensation capacitor is connected with one of the plurality of data lines, and the other terminal of the compensation capacitor is connected with the signal compensation line.

Abstract: An image display device and a video wall including the same are disclosed. The image display device includes a housing, a display configured to display an image, a first wireless communication module disposed on one surface of the housing, and a second wireless communication module disposed at a position on an opposite surface of the housing corresponding to a position of the first wireless communication module. The first wireless communication module and the second wireless communication module transmit and receive a signal through the same short-range communication method. Various other embodiments are possible.

Abstract: A first latch retrieves a pixel data piece for each one horizontal scanning period of a video data signal and holds the pixel data piece as a first pixel data piece. A second latch retrieves the first pixel data piece from the first latch at a timing when the retrieval by the first latch is completed and holds the first pixel data piece as a second pixel data piece. An interpolation data generating unit obtains the first pixel data piece and the second pixel data piece and generates an interpolation data piece. A third latch alternately performs a retrieval of the second pixel data piece and a retrieval of the interpolation data piece, and sequentially outputs the retrieved data piece as a third pixel data piece. A gradation voltage output unit outputs the gradation voltage signal based on the third pixel data piece.

Abstract: A display device includes a display panel, and the display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the plurality of data lines and the plurality of gate lines. A data driver provides data signals to the plurality of data lines. A gate driver sequentially generates gate signals corresponding to a start pulse using a clock signal, and provides the gate signals to the plurality of gate lines. A timing controller provides the clock signal and the start pulse to the gate driver. The gate driver compares a data signal provided to a first data line among the plurality of data lines and at least one of the gate signals to generate a feedback signal. The timing controller sets a delay value of the clock signal based on the feedback signal.

Abstract: A display device includes: pixel columns including pixels arranged along a first direction; pixel rows including pixels arranged along a second direction crossing the first direction; data lines connected to respective pixel columns, each of the data lines including a first sub-data line provided at one side of a corresponding pixel column and a second sub-data line provided at another side of the corresponding pixel column; scan lines extending along the second direction and connected to respective pixel rows; and a power line to supply driving power to the pixels, one of the pixels of the pixel columns is connected to the first sub-data line, and a pixel adjacent to the pixel connected to the first sub-data line is connected to the second sub-data line, and the first sub-data line and the second sub-data line in the same pixel column are on different layers from each other.

Abstract: An exemplary embodiment provides a display device including: a display part configured to include a display part color filter; and a peripheral part disposed at the upper side of the display part and including an inspection pattern for checking an alignment of the display part color filter. The inspection pattern may include a plurality of color filters having colors and reference patterns disposed at at least one side of the plurality of color filters. A number of the plurality of color filters of each color corresponds to a number of shots of a division exposure process. Adjacent color filters among the plurality of color filters may be disposed at different heights.

Abstract: A shift register circuit includes a noise reduction sub-circuit and a pull-down node control sub-circuit. A control end of the noise reduction sub-circuit is connected to a pull-down node, the noise reduction sub-circuit is connected to a first voltage input end. The pull-down node control sub-circuit includes a first pull-down node control sub-circuit and a second pull-down node control sub-circuit. The second pull-down node control sub-circuit controls the pull-down control node to be connected to a first clock signal input end when the first clock signal input end inputs a first level, the pull-down node to be connected to the first clock signal input end when a potential of the pull-down control node is at the first level, so that the potential of the pull-down node is at a first level and a noise reduction transistor included in the noise reduction sub-circuit is turned off.

Abstract: The present application discloses a shift register, a gate driving circuit and a driving method thereof, and a display apparatus. The shift register includes an input sub-circuit, an output sub-circuit, a reset control sub-circuit, a pull-up node reset sub-circuit, and an output signal reset sub-circuit; the input sub-circuit is configured to pre-charge the pull-up node under the control of a signal input to the first signal input terminal; the output sub-circuit is configured to output, through the signal output terminal, a signal input to the first clock signal input terminal under the control of a potential of the pull-up node; the reset control sub-circuit is configured to control, under the control of a reset signal input to the second signal input terminal, whether the pull-up node reset sub-circuit and the output signal reset sub-circuit operate to reset the pull-up node and the signal output terminal, respectively.

Abstract: Provided herein is a scan driver including scan stages. A first scan stage includes a first transistor including a gate electrode coupled to a first node, a first electrode coupled to a first power clock line, and a second electrode coupled to a first scan line; a first capacitor connected between the first node and the first scan line; a second transistor including a gate electrode coupled to a second node, a first electrode coupled to the first scan line, and a second electrode coupled to a first power line; a third transistor including a gate electrode coupled to the second node, a first electrode coupled to a third node, and a second electrode coupled to a first control clock line; and a second capacitor connected between the second node and the third node.

Abstract: An object of the present invention is to provide a display device with high display quality. The display device of the present invention includes a pixel and a source driver circuit. The pixel includes first and second transistors (21, 22), a capacitor (25), and a display element (26). The source driver circuit is electrically connected to first and second wirings (31, 32). The first wiring (31) is electrically connected to one electrode of the capacitor 25 and one electrode of the display element (26) through the first transistor (21). The second wiring (32) is electrically connected to the other electrode of the capacitor (25) and the other electrode of the display element (26) through the second transistor (22).

Abstract: A gate scanning unit circuit is applied in a display panel including a number of gate lines and a driver configured to output clock signals. The gate scanning unit circuit is configured to scan the number of gate lines. The gate scanning unit circuit includes a flip-flop and at least two output units. The flip-flop is configured to output a trigger signal. Each output unit is connected to the flip-flop and the driver. Each of the at least two output units is connected to the number of gate lines one-to-one. The output unit is configured to output a gate scan signal to the corresponding connected gate line according to the trigger signal and the clock signals.

Abstract: A display apparatus includes a display panel; a timing control chip, connected to the display panel and including an input data temporary storage module, a data processing module, and a data output module; a plurality of first and second driver chips; a power control chip, connected to the timing control chip, the first and the second driver chips, where the power control chip generates a control signal and transmits the control signal to the second driver chips; and an image-sticking elimination module, including a logic detection unit and a storage module, where an end of the storage module is coupled to the logic detection unit, and an other end of the storage module is electrically coupled to the data output module, where the logic detection unit is coupled to the power control chip and receives the control signal, so as to control a working state of the storage module.

Abstract: A shift register circuit and a driving method thereof, a gate driving circuit and a display panel are provided. The shift register circuit includes: an input terminal; a first reference voltage terminal; a second reference voltage terminal; a first clock signal terminal; a second clock signal terminal; an output terminal; an input circuit, a first control circuit; a second control circuit; a third control circuit; a compensation circuit, a first node, a second node, a third node and an output circuit, the compensation circuit is configured to compensate a voltage of at least one of the first node, the second node, and the third node in response to the second clock signal.

Abstract: An image sensor is provided. The image sensor includes a pixel array including a plurality of pixels connected between a plurality of row lines and a plurality of column lines; an analog-to-digital converter configured to convert each of a plurality of column signals received through the plurality of column lines into a plurality of first digital signals, and convert a level of the plurality of row lines into a second digital signal; and a compensator configured to generate digital pixel data based on the plurality of first digital signals and the second digital signal.

Abstract: An electronic device may have a display and a gaze tracking system. The electronic device may display images on the display that have a higher resolution in a portion of the display that overlaps a gaze location than other portions of the display. Timing controller circuitry and column driver circuitry may include interpolation and filter circuitry. The interpolation and filter circuitry may be used to perform nearest neighbor interpolation and two-dimensional spatial filtering on low resolution image data. Display driver circuitry may be configured to load higher resolution data into selected portions of a display. The display driver circuitry may include low and high resolution image data buffers and configurable row driver circuitry. Block enable transistors may be included in a display to allow selected blocks of pixels to be loaded with high resolution image data.

Abstract: A gate driving circuit and a display apparatus including the same are disclosed, in which a plurality of gate lines may be driven through one stage circuit. The gate driving circuit includes first to mth stage circuits outputting a plurality of scan signals by dividing the scan signals into a first signal group and a second signal group. The first to mth stage circuits are grouped into k number of stage groups having two adjacent stage circuits, stage circuits of jth stage group (j is a natural number of 1 to k?1) output the scan signals of the first signal group to be earlier than the scan signals of the second signal group, and stage circuits of (j+1)th stage group output the scan signals of the second signal group to be earlier than the scan signals of the first signal group.

Abstract: A display panel, a display device and a compensation method are provided. The display panel includes at least one pixel unit group, at least one sensing line, a plurality of gate lines, a plurality of first data lines and a plurality of second data lines. Each pixel unit group includes a plurality of pixel units arranged in two rows and a plurality of columns, the plurality of pixel units in each pixel unit group are connected to a same one of the gate lines, one of two pixel units in each column of each pixel unit group is connected to one of the first data lines corresponding thereto, other one is connected to one of the second data lines corresponding thereto, the plurality of pixel units in each pixel unit group are connected to a same sensing line.

Abstract: The embodiments of the present disclosure provide a shift register unit, a gate driving circuit and a driving method thereof, and a display device. The shift register unit, includes two transfer gate modules (211, 212), two NOR gate modules (NOR1, NOR2), two AND gate modules (AND3, AND4), two capacitor modules (241, 241), and two inverter modules (225, 227). The shift register unit provided in the present disclosure can make the layout area occupied by the corresponding gate driving circuit reduce greatly as compared with that occupied by the gate driving circuit in the prior art, which facilitates border narrowing of the corresponding display device.

Abstract: The present disclosure provides a shift register unit, a driving method thereof, a gate driver circuit and a display device. The shift register unit includes: a first input subcircuit configured to transmit a first voltage signal to a pull-up node under a control of a first input signal; an output subcircuit configured to transmit a clock signal to a first output end and to transmit a second voltage signal to a second output end; a storage unit having a first end coupled to the pull-up node and a second end coupled to the first output end; a first pull-down subcircuit configured to pull down a voltage of the first output end and the second output end; and a second pull-down subcircuit configured to pull down a voltage of the first output end and the second output end.

Abstract: To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.

Abstract: The present disclosure discloses a circuit, a driving method thereof, a display panel and a display device. The circuit may include: a signal control module, a compensation control module, an initialization module, a data writing module, a driving control module, and a light emitting device. With the signal control module which is cooperated with other modules, the threshold voltage compensation time of the driving transistor can be increased, and the threshold voltage compensation can be ensured, thereby improving the image display quality.

Abstract: A display component, a display device and a display control method are provided. The display component includes a plurality of sub-pixel units arranged in a matrix; an inter-transmission connection portion; and a control portion, wherein each sub pixel unit includes a storage capacitor and an inter-transmission switching element, in each sub-pixel unit, the storage capacitor is connected to the inter-transmission connection portion via the inter-transmission switching element, the control portion is configured to execute at least one inter-transmission operation in one frame period.

Abstract: A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/?m (1×10?18 A/?m) or less. Therefore, the drive capability of the semiconductor device can be improved.

Abstract: A power management circuit of a display device includes a voltage information storage comprising a first and second bank storing first and second voltage information corresponding to first and second voltage levels different from each other, a bank select pin receiving a bank select signal, a voltage information selecting circuit selectively outputting the first voltage information stored in the first bank or the second voltage information stored in the second bank in response to the bank select signal received through the bank select pin, and a DC-DC converter generating panel driving voltages having the first voltage levels based on the first voltage information when the first voltage information is output from the voltage information selecting circuit, and generating the panel driving voltages having the second voltage levels based on the second voltage information when the second voltage information is output from the voltage information selecting circuit.

Abstract: A gate driving circuit, a driving method thereof, a gate driver, a display panel and a display apparatus. In the gate driving circuit, a pull-up sub-circuit is configured to control the potential of a pull-up node according to signals inputted from first, second, third, fourth and fifth signal terminals and the potential of a pull-down node; a reset sub-circuit is configured to reset the potential of the pull-up node according to a signal inputted from a reset terminal; a pull-down sub-circuit is configured to control the potential of the pull-down node according to a signal inputted from the fourth signal terminal, a signal outputted from an output terminal and the potential of the pull-up node; and an output sub-circuit is configured to control a signal outputted from the output terminal according to a signal inputted from the third signal terminal, the potential of the pull-down node and the potential of the pull-up node.

Abstract: Disclosed is a level shifter. The level shifter includes a level shifting circuit, a first adjusting circuit, and a second adjusting circuit. The level shifting circuit determines whether to output a first current from a supply voltage line to an output node based on a voltage level of a first node and determines whether to output a second current from the supply voltage line to a third node based on a voltage level of a second node. The first adjusting circuit blocks an output of a third current from the third node to the first node when a clock signal having a first voltage level is received. The second adjusting circuit outputs a fourth current from the first node to a ground voltage line when the clock signal having the first voltage level is received.

Abstract: A display device includes a plurality of pixel electrodes arranged in an array. A first switch electrically connected to a first pixel electrode of the pixel electrodes. A second switch electrically connected to a second pixel electrode of the pixel electrodes. The second switch is electrically connected between the first switch and a data line, and the first pixel electrode and the first pixel electrode are respectively located at two row of the pixel electrodes that are not adjacent to each other.

Abstract: A display device includes a scan driver configured to provide a scan signal to the scan line, the scan signal having an ON voltage for turning on a transistor in a plurality of horizontal periods including a current horizontal period and at least one previous horizontal period corresponding to the scan signal, and a grayscale data processor configured to correct current grayscale data of a current pixel corresponding to the current horizontal period to generate correction grayscale data based on previous grayscale data of a previous pixel corresponding to the previous horizontal period, the current pixel included in a same pixel column as the previous pixel.

Abstract: A display device includes a pixel. The pixel includes a light emitting unit and a driving circuit for driving the light emitting unit. When the light emitting unit is driven in a pulse width modulation (PWM) mode with a PWM period, the PWM period includes a plurality of pulse controllable periods.

Abstract: This application discloses a drive circuit, a drive method and a display apparatus. The drive circuit includes: an initiator configured to output a common voltage, a compensator coupled to the initiator, and a controller; the initiator includes an initial memory configured to store an initial value of the common voltage, and an operational circuit configured to convert the initial value of the common voltage into an output common voltage to output; and the controller collects the initial value of the common voltage of the initiator and a value of the output common voltage, and compares the initial value of the common voltage and the value of the output common voltage, thereby deciding whether to control the compensator to compensate the value of the common voltage or not.

Abstract: The present application discloses a driving method, a driving circuit, and a display device. The driving circuit includes an initializer that outputs a common voltage, a compensator coupled to the initializer, and a controller that collects the common voltage output from the initializer, where when the common voltage is less than a preset threshold, the controller controls the compensator to compensate for a value of the common voltage.

Abstract: The present disclosure disclosed a display information processing device and method suitable for a host system, the method comprises: determining whether specification of interfaces of a plurality of extended display devices connected to extension interfaces conforms to the default specification of interfaces of the host system; calling drivers corresponding to a plurality of extended display devices from the host system to drive the plurality of extended display devices with the specification of interfaces conforming to the default specification of interfaces of the host system; obtaining resolution information from the plurality of extended display devices, respectively; determining a common resolution from the resolution information of the plurality of extended display devices; and outputting display information of a main display device to the plurality of extended display devices based on the common resolution.

Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

Abstract: A display device which achieves both a high-accuracy sensing operation and smooth input in a touch sensor unit is provided. The display device includes a display unit and the touch sensor unit. The touch sensor unit performs a touch sensing operation when the display unit does not perform a display image rewriting operation; thus, a highly accurate sensing operation is possible. A gate driver of the display unit includes a first circuit and a second circuit. The second circuit includes a plurality of shift registers. Only a display image of a region that needs to be rewritten can be rewritten. The first circuit is a shift register and designates a shift register from the plurality of shift registers included in the second circuit to operate. In the case where an image in the entire display region does not need to be rewritten, the time assigned for the sensing operation of the touch sensor unit increases, leading to the smooth input.

Abstract: Disclosed is a method for spreading spectrum, which includes: acquiring a modulation signal corresponding to a clock signal, when the clock signal is detected; and spectrum spreading the clock signal according to the modulation signal, wherein the modulation signals respectively corresponding to two adjacent clock signals are opposite in phase. The present disclosure further provides a chip, a display panel, and a computer readable storage medium. The present disclosure solves the technical problem of poor spread spectrum effect on dual clock signals.

Abstract: A display device is provided. The display device includes an internal driving circuit, an external circuit and a plurality of signal lines. The signal lines are electrically connected with the internal driving circuit and the external circuit. Each signal line includes N signal line sections, Ma first turning points and Mb second turning points, wherein the N signal line sections are connected with each other, each of the Ma first turning points and the Mb second turning points is located at the connecting site of the two adjacent signal line sections, N and Ma are positive integers, Mb is 0 or a positive integer, N?3, Ma?2, Ma+Mb?N?1, the resistance change rate between the two adjacent signal line sections connected with each first turning point is ?R, and 0<|?R|?10%.

Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

Abstract: The present application is a display panel driving method, a driving device and a display device. The method comprises: forming 2n rows of sub-pixels in a display panel into a sub-pixel group, and dividing the sub-pixel group into a first sub-pixel group and a second sub-pixel group using a grouping method. The display panel comprises pixel units arranged in an array; each pixel unit comprises sub-pixels of at least three colors, and the sub-pixels of each color comprises sub-pixels of a first type and sub-pixels of a second type; and the sub-pixels of the first type and the sub-pixels of the second type are arranged at intervals along the row direction and the column direction of the pixel unit arrangement, and the data signal levels of the two provided by a driving module thereof are different.

Abstract: Provided is a method of reducing power consumption by a display device including a display logic for processing pixel data, and a display panel including a plurality of pixels, the method including receiving the pixel data corresponding to the plurality of pixels, determining whether a number of consecutive pixels of the plurality of pixels that correspond to identical data of the pixel data reaches a threshold number, and powering down the display logic when the number of consecutive pixels exceeds the threshold number.

Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.

Abstract: According to an aspect of the present disclosure, there is provided a gate driver and a method of repairing the same. The gate driver can include a plurality of driving stages cascade connected, at least one repairing stage disposed between the plurality of driving stages, and a plurality of repair lines connected to the at least one repair stage. The plurality of repair lines overlap with a plurality of lines connected to the plurality of driving stages. The repairing stage can replace a defective driving stage of the gate driver.

Abstract: A driver circuit includes a circuit 200, a transistor 101_1, and a transistor 101_2. A signal is selectively input from the circuit 200 to a gate of the transistor 101_1 and the transistor 101_2, so that the transistor 101_1 and the transistor 101_2 are controlled to be on or off. The transistor 101_1 and the transistor 101_2 are turned on or off; thus, the wiring 112 and the wiring 111 become conducting or non-conducting.