Abstract: According to one embodiment, a display device includes a first common electrode and a second common electrode arranged in a first direction, a first switch unit selectively supplying a first drive signal or a second drive signal different from the first drive signal to the first common electrode, and a second switch unit selectively supplying the first drive signal or the second drive signal to the second common electrode, wherein the second common electrode and the first switch unit are arranged in a second direction intersecting the first direction, the first switch unit comprises a first switch circuit and a second switch circuit arranged in the second direction.

Abstract: A liquid crystal display device according to the present disclosure includes: a liquid crystal unit including a pixel electrode, a counter electrode facing the pixel electrode, and a liquid crystal layer sealed between the pixel electrode and the counter electrode; a first writing circuit configured to write a positive polarity video signal among video signals whose polarity changes periodically; and a second writing circuit configured to write a negative polarity video signal among the video signals whose polarity changes periodically. The liquid crystal unit, the first writing circuit, and the second writing circuit are provided for each pixel. The first writing circuit and the second writing circuit include transistors having conductivity types different from each other.

Abstract: A gate driving unit includes an input module, a first output module, a second output module, a feedback module, and an output-controlling module. The input module outputs a previous level-transferring signal into a first node. The first output module outputs a present level-transferring signal. The second output module outputs a scan signal. The feedback module outputs a present-level feedback signal. The output-controlling module pulls up potential of the scan signal to a first direct-current high voltage and pulls up potential of the present level-transferring signal to a second direct-current high voltage.

Abstract: A display apparatus, including a display panel and a first driver, is provided. The display panel includes multiple pixel circuits and multiple first wires. The first wires are configured to transmit multiple first driving signals. Each of the first wires includes a first portion and a second portion. The first driving signal is transmitted in the first portion and the second portion in different directions. The first driver is coupled to the display panel. The first driver is configured to output the driving signals to drive the display panel.

Abstract: The present disclosure relates to a circuit of controlling a common voltage of a liquid crystal panel. According to an embodiment of the present disclosure, a voltage control circuit is configured to provide a common voltage to a common electrode of a liquid crystal panel. The liquid crystal panel includes M rows and N columns of pixel units. Each pixel unit is coupled to the common electrode. The voltage control circuit includes an operational amplifier arranged in a negative feedback configuration. The operational amplifier includes: an input stage, a gain stage and an output stage. The output stage includes a second NMOS transistor and a second PMOS transistor. A gate of the second NMOS transistor receives a first control signal, a drain of the second NMOS transistor is coupled to a gate of a first PMOS transistor, and a source of the second NMOS transistor is coupled to a second reference voltage.

Abstract: A detection device is provided and includes insulating substrate; detection element including first photodiode, first thin film transistor, second thin film transistor, and third thin film transistor; dummy element including second photodiode and first thin film transistor; and first scan line, wherein first scan line is a gate of each of first thin film transistors, dummy element is located adjacent to detection element, and dummy element includes first photodiode and none of second thin film transistor and third thin film transistor.

Abstract: A DLDO has a configuration that mitigates performance degradation associated with limit cycle oscillation (LCO). The DLDO comprises a clocked comparator, an array of power transistors, a digital controller and a clock pulsewidth reduction circuit. The digital controller comprises control logic configured to generate control signals that cause the power transistors to be turned ON or OFF in accordance with a preselected activation/deactivation control scheme. The clock pulsewidth reduction circuit receives an input clock signal having a first pulsewidth and generates the DLDO clock signal having the preselected pulsewidth that is narrower that the first pulsewidth, which is then delivered to the clock terminals of the clocked comparator and the digital controller. The narrower pulsewidth of the DLDO clock reduces the LCO mode to mitigate performance degradation caused by LCO.

Abstract: The present application provides a gate driving unit circuit and a method of driving the same, a gate driving circuit and a display apparatus. The gate driving unit circuit includes a shift register and a plurality of driving signal output sub-circuits. Each driving signal output sub-circuit corresponds to one of gate lines on an array substrate, is coupled to a first power supply terminal and a signal output terminal of the shift register, and also coupled to a corresponding one of driving scan signal lines. Each driving signal output sub-circuit is configured to output, under the control of a signal output by the signal output terminal of the shift register, a driving scan signal provided by the corresponding driving scan signal line or an OFF voltage provided by the first power supply terminal to the corresponding gate line.

Abstract: It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.

Abstract: An electro-optic display having a plurality of pixels is driven from a first image to a second image using a first drive scheme, and then from the second image to a third image using a second drive scheme different from the first drive scheme and having at least one impulse differential gray level having an impulse potential different from the corresponding gray level in the first drive scheme. Each pixel which is in an impulse differential gray level in the second image is driven from the second image to the third image using a modified version of the second drive scheme which reduces its impulse differential The subsequent transition from the third image to a fourth image is also conducted using the modified second drive scheme but after a limited number of transitions using the modified second drive scheme, all subsequent transitions are conducted using the unmodified second drive scheme.

Abstract: A driving apparatus for a display panel is provided. The driving apparatus for the display panel is configured on a film by means of a Chip-on-Film (COF) package. A selection circuit receives multiple driving voltages. A control circuit is coupled to the selection circuit and controls the selection circuit to output one of the multiple driving voltages, so as to drive the display panel.

Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.

Abstract: Provided are gate driver circuit, display panel, display device, and driving method thereof. The gate driver circuit includes cascaded shift registers. Each shift register includes input unit, node control unit, first output unit, and second output unit. first terminal, control terminal, and second terminal of the input unit respectively electrically connected to signal input terminal, first signal terminal, and first node. first terminal, second terminal, third terminal, fourth terminal, first control terminal, second control terminal and fifth terminal of the node control unit respectively electrically connected to the first node, the first signal terminal, first power supply voltage terminal, second power supply voltage terminal, the first node, second signal terminal, and second node. As such, one shift register outputs two control signals, the number of shift registers in the gate driver circuit can be reduced, and the bezel of the display panel and the display device can be reduced.

Abstract: Disclosed is an electronic device including a display panel displaying an image, a source driver supplying a source voltage to the display panel, and a display driver integrated circuit (DDI) including a timing controller controlling the source driver. The timing controller may be configured to identify information associated with a luminance of the image and to set a source bias current for controlling a slew rate of the source voltage based on the luminance of the image. Besides, various embodiments as understood from the specification are also possible.

Abstract: A display device is provided. The device comprises a pixel array, a scanning circuit configured to select a row in the pixel array, and a signal output circuit configured to supply image signals to pixels arranged in the row selected by the scanning circuit. The device displays an image using pixels arranged between an initial line on one side in the pixel array and an end line succeeding the initial line on the other side. The scanning circuit includes a start designation circuit configured to designate the initial line, an end designation circuit configured to designate the end line and a shift register. The shift register is configured to start selection for writing the image signals from the initial line and sequentially select the rows between the initial line and the end line in one frame period for displaying one image.

Abstract: A display device includes a display panel having a curved side or a polygonal side, the display panel including a plurality of pixels in a display region, a gate driver including a plurality of normal stages connected to each other for outputting gate signals to the pixels via a plurality of gate lines, and a plurality of dummy stages between some of the normal stages, and a data driver providing data signals to the pixels via a plurality of data lines.

Abstract: A source driver includes a data latch unit that outputs acquired pixel data, a gradation voltage conversion unit that acquires the pixel data outputted from the data latch unit and converts the pixel data to gradation voltages, an output unit that amplifies and outputs the gradation voltages to source lines, and a timing control unit that controls the timing of the output of the pixel data from the data latch unit. The timing control unit performs control such that the longer a source line is from a source driver to a pixel column, the smaller the timing difference is between acquisition of the pixel data by the data latch unit and the output of the pixel data.

Abstract: A gate driver and a display device including the same, are discussed. The gate driver includes a plurality of stages which are dependently connected to each other. Each of the plurality of pixels includes an output unit which outputs a gate voltage by a voltage of an RQ node, a voltage of a PQ node, and a voltage of a QB node, a first controller which controls the RQ node, a second controller which controls the PQ node, and a third controller which controls the QB node. The gate voltage is configured by a first clock signal having a first phase and a second clock signal having a first phase which is different from the first phase of the first clock signal.

Abstract: A display device includes a substrate that includes a display area for displaying an image and a non-display area surrounding the display area, a plurality of pixels that are disposed in the display area and each include an organic light emitting diode and a pixel circuit portion configured to operate the organic light emitting diode, and a scan driver that is disposed in the non-display area and includes a plurality of stages configured to output scan signals to the plurality of pixels. The plurality of stages may be arranged in n columns, a height of one stage may correspond to a height of n pixels, and n may be an integer of 2 or more.

Abstract: A flat-panel display comprises a display substrate, an array of pixels distributed in rows and columns over the display substrate, the array having a column-control side, and column controller disposed on the column-control side of the array providing column data to the array of pixels through column-data lines. In some embodiments, rows of pixels in the array of pixels form row groups and each column of pixels in a row group receives column data through a separate column-data line. In some embodiments, each pixel in each column of pixels in the array of pixels is serially connected and each pixel in the array of pixels comprises a token-passing circuit for passing a token through the serially connected column of pixels.

Abstract: A gate driving circuit includes a first gate driving circuit and a second gate driving circuit, wherein the m number of first clock signals input to the first gate driving circuit includes an (n+1)-th clock signal and an (n+k)-th clock signal, and the m number of second clock signals input to the second gate driving circuit includes an (n+2)-th clock signal and an (n+k+1)-th clock signal, where the n is any integer, and the k is a natural number of 3 or more, a high level voltage duration of the (n+1)-th clock signal and a high level voltage duration of the (n+k)-th clock signal do not overlap, and a high level voltage duration of the (n+2)-th clock signal and a high level voltage duration of the (n+k+1)-th clock signal do not overlap.

Abstract: A backlight system includes a backlight and a master driving circuit. The backlight includes a plurality of slave driving circuits and a plurality of light sources driven by the plurality of slave driving circuits, wherein the plurality of slave driving circuits are arranged in a matrix of driving rows and driving columns such that first through m-th slave driving circuits, where m is a positive integer greater than one, are arranged in each driving row of the driving rows, and the first through m-th slave driving circuits are connected in a daisy chain structure. The master driving circuit is configured to generate a plurality of input data signals, wherein each input data signal of the plurality of input data signals corresponds to the each driving row, and the each input data signal includes first through m-th packets including luminance data corresponding to the first through m-th slave driving circuits.

Abstract: A shift register unit, a circuit structure, a gate drive circuit, a drive circuit and a display device are provided. A shift register unit includes a substrate and an input circuit, a reset circuit, a first output circuit, a first output terminal, a first connection conductive portion connecting both the input circuit and the reset circuit, a second connection conductive portion connecting both the reset circuit and the first output circuit, and a third connection conductive portion connecting both the first output circuit and the first output terminal, all of which are on the substrate.

Abstract: This application discloses a display panel, a driving method thereof and a display apparatus. The display panel includes a substrate, the substrate being provided with a plurality of data lines, a plurality of gate lines, and a plurality of pixel units; and a gate driver chip, where each pixel unit includes subpixels of different colors; the gate driver chip outputs gate enabling signals to the gate lines to turn on the pixel units; and each row of pixel units includes a plurality of pixel groups, each pixel group includes a first column of subpixels and a second column of subpixels and a voltage of a gate enabling signal of the first column of subpixels is greater than that of a gate enabling signal corresponding to the second column of subpixels.

Abstract: A display device is provided. The device comprises a pixel array, a scanning circuit configured to select a row in the pixel array, and a signal output circuit configured to supply image signals to pixels arranged in the row selected by the scanning circuit. The device displays an image using pixels arranged between an initial line on one side in the pixel array and an end line succeeding the initial line on the other side. The scanning circuit includes a start designation circuit configured to designate the initial line, an end designation circuit configured to designate the end line and a shift register. The shift register is configured to start selection for writing the image signals from the initial line and sequentially select the rows between the initial line and the end line in one frame period for displaying one image.

Abstract: A display driving device supporting a low power mode according to an aspect of the present disclosure that is capable of minimizing power consumption when driving in the low power mode includes a plurality of output buffers connected to data lines to precharge the data lines with a first data signal corresponding to a black image when a precharge horizontal line is driven in a display panel including a first region where a standby image is displayed and the second region where the black image is displayed, the precharge horizontal line being included in the second region, and a gamma voltage generator connected to the data lines to output the first data signal to the data lines when other horizontal lines other than the precharge horizontal line in the second region are driven.

Abstract: The present disclosure relates to a shift register unit having a cascade input terminal, a cascade output terminal and a scan output terminal. The shift register unit may include a first shift circuit, a second shift circuit, an input circuit, and a control circuit. The input circuit may be configured to provide an input signal from the cascade input terminal to an input terminal of the first shift circuit under control of an input clock terminal. The control circuit may be configured to control connection of an output terminal of the first shift circuit and an input terminal of the second shift circuit based on a signal at a first control terminal.

Abstract: A level shift circuit includes an input section to which input signal of a first power supply system is input, a supply section that includes a pair of nodes, and a regulator. The supply section is connected to one of a pair of power supply lines serving as a second power supply system of which a voltage level is higher than a voltage level of the first power supply system, the supply section supplying a potential of the one of the pair of power supply lines to one of the pair of nodes according to the input signal. The regulator is connected to another of the pair of power supply lines, the regulator regulating current flowing between the one of the pair of nodes that is supplied with the potential of the one of the pair of power supply lines, and the other of the pair of power supply lines.

Abstract: A display device includes a display panel including pixels, and data lines and gate lines connected to the pixels, a timing controller configured to output source driving bit information and gate driving bit information through an intra-interface signal, a source driver configured to generate data driving signal based on the source driving bit information and to supply the data driving signal to the data lines, and a gate driver configured to generate a gate driving signal based on the gate driving bit information and to supply the gate driving signal to the gate lines, wherein the intra-interface signal is configured with predetermined data transmission units and includes both the source driving bit information and the gate driving bit information every 1 data transmission unit.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a blanking input circuit, a display input circuit, an output circuit, and a coupling circuit. The blanking input circuit is configured to input a blanking input signal to a control node and is configured to input a blanking signal to a first node in a blanking phase of one frame; the display input circuit is configured to input a display signal to the first node in a display phase of one frame in response to a first clock signal; and the coupling circuit is electrically connected to the control node and is configured to control, by coupling, a level of the control node in response to the blanking signal.

Abstract: A scan driver including a stage that includes: an input circuit controlling a voltage of a first node in response to signals at first and second input terminals; a first signal processing circuit controlling a voltage of a second node in response to the signal at the first input terminal and supplies a voltage of a first power to the second node in response to the signal at the second input terminal; a second signal processing circuit supplying a voltage of a second power to the first node in response to a signal at a third input terminal and the voltage of the second node; a first output circuit outputting the signal at the third input terminal as a first scan signal; and a second output circuit outputting a signal at a fourth input terminal as a second scan signal at a different time from the first scan signal.

Abstract: A gate driving circuit includes a bootstrapping circuit, a pre-charge circuit, and an output control circuit. The bootstrapping circuit is composed of a bootstrapping capacitor and a transistor. A first terminal of the bootstrapping capacitor has a first voltage during a first duration. The pre-charge circuit is connected to the first terminal of the bootstrapping capacitor. The pre-charge circuit boosts the first terminal of the bootstrapping capacitor from the first voltage to a second voltage during a second duration. The bootstrapping circuit boosts the first terminal of the bootstrapping capacitor from the second voltage to a third voltage during a third duration. The output control circuit is connected to the first terminal of the bootstrapping capacitor. The output control circuit boosts the first terminal of the bootstrapping capacitor from the third voltage to a fourth voltage during a fourth duration.

Abstract: A light emission driving circuit includes a driving circuit configured to output a light emission driving signal to a first output terminal and output a switching signal to a first node in response to clock signals and a first carry signal, and a first masking circuit configured to output a second carry signal to a second output terminal in response to a masking clock signal, the light emission driving signal, and the switching signal. The masking clock signal is a signal which is maintained at a first level during a normal mode and periodically changes during a low power mode.

Abstract: An object of the present invention is to provide a driver IC and a liquid crystal display apparatus which uses a circuit of an output channel which is not used to drive a liquid crystal panel as a backup of the other output channel. A driver IC includes a plurality of output channels ch1 to chn, a plurality of output buffer circuits corresponding to each of the plurality of output channels ch1 to chn, and an output channel selection circuit, and when a malfunction occurs in the output buffer circuit of an effective channel, the output buffer circuit in which the malfunction occurs is automatically switched to the output buffer circuit of an ineffective channel so that the output of the signal from the effective channel is continued.

Abstract: Shift register includes input sub-circuit coupling input terminal to first node responsive to signal of first clock terminal in input stage, control sub-circuit transmitting signal of second clock terminal to intermediate output terminal according to level at first node and controlling potential of third node according to potential of intermediate output terminal and signal of third clock terminal in input, output and reset stages, pull-up sub-circuit coupling second level terminal to final output terminal responsive to potential of intermediate output terminal in output stage, first voltage stabilization sub-circuit stabilizing voltage between final output terminal and third node responsive to signal of next-stage node connection terminal, pull-down transistor having gate electrode coupled to third node, first electrode coupled to first level terminal, and second electrode coupled to final output terminal.

Abstract: A display device includes a first display area, a second display area, a first multiplexer, and a second multiplexer. The first display area includes a plurality of first data lines. The second display area is adjacent to the first display area and includes a plurality of second data lines. The first multiplexer is electrically connected to one of the first data lines. The second multiplexer is electrically connected to one of the second data lines. The first data line is electrically connected to a first number of sub-pixels. The second data line is electrically connected to a second number of sub-pixels. The first number is less than the second number. The size of the first multiplexer is smaller than that of the second multiplexer.

Abstract: A shift register and a drive method therefor, and a gate drive circuit. The shift register includes: an input sub-circuit, a detection control sub-circuit, an output sub-circuit, a first reset sub-circuit, and a pull-down sub-circuit. The detection control sub-circuit is respectively connected to a random detection signal end (OE), a signal input end (INPUT), a first clock signal end (CLKA), a first reset end (RST1), and a pull-up node (PU), and is configured to provide a signal of the first clock signal end (CLKA) for the pull-up node (PU) under the control of the signal input end (INPUT), the random detection signal end (OE), the first clock signal end (CLKA), and the first reset end (RST1).

Abstract: The embodiments of the present disclosure propose a shift register, a driving method thereof, a gate driving circuit and a display apparatus. The shift register comprises an input sub-circuit coupled to an input terminal and a pull-up node, and configured to charge the pull-up node under control of an input signal from the input terminal; an output sub-circuit coupled to a clock signal terminal, the pull-up node, and an output terminal, and configured to transmit a clock signal from the clock signal terminal to the output terminal under control of the pull-up node; and an output shaping sub-circuit coupled to the clock signal terminal, the output terminal, and a first voltage signal terminal, and configured to transmit a first voltage signal from the first voltage signal terminal to the output terminal under control of the clock signal.

Abstract: A shift register unit, a circuit structure, a gate drive circuit, a drive circuit and a display device are provided. A shift register unit includes a substrate and an input circuit, a reset circuit, a first output circuit, a first output terminal, a first connection conductive portion connecting both the input circuit and the reset circuit, a second connection conductive portion connecting both the reset circuit and the first output circuit, and a third connection conductive portion connecting both the first output circuit and the first output terminal, all of which are on the substrate.

Abstract: A shift register circuit and its driving method, a display panel, and a display device are provided. The shift register circuit includes an input module, a first inverter, a second inverter, and an output module. The input module is connected to a first input terminal, a second input terminal, a third input terminal, and a first electrical-level terminal, to respond to signals from the second and third input terminal and control a voltage of a first node. In the first inverter, an input terminal is connected to the first node, and an output terminal is connected to a second node. In the second inverter, an input terminal is connected to the second node, and an output terminal is connected to the first node. The output module provides a signal of the fourth input terminal to an output terminal of the output module, and also provides a voltage of a first power terminal to the output terminal of the output module.

Abstract: A shift register, a gate driving circuit and a driving method for the same, and a liquid crystal display. The shift register includes: a pull-up sub-circuit configured to set a potential at a pull-up node to an operating potential when a first input signal is received via a first input terminal; a first output sub-circuit configured to output a gate driving signal at an output terminal according to a first clock signal received via a first clock signal terminal when the potential at the pull-up node is the operating potential; and a second output sub-circuit configured to output a gate driving signal at the output terminal when a second input signal is received via a second input terminal during a period other than a duration in which one frame of picture is displayed.

Abstract: A display device includes a pixel disposed in a display region. The pixel includes a light-emitting element connected between a first power source and a second power source; a first transistor connected between the first power source and the light-emitting element to control a driving current flowing in the light-emitting element in response to a voltage of a first node; and at least one switching transistor to transmit a data signal or a voltage of an initialization power source to the first node. The switching transistor includes a first channel region, a first conductive region and a second conductive region which are respectively disposed at opposite sides of the first channel region, and a first wide band-gap region disposed between the first channel region and the second conductive region.

Abstract: A display substrate, a manufacturing method and a display device are provided. The display substrate includes a scan driving circuit; the scan driving circuit includes a plurality of shift register units, at least one shift register unit includes a signal output line and an output circuit, the output circuit includes an output transistor and an output reset transistor; the signal output line includes a first output line portion extending along the first direction; the first output line portion is coupled to the second electrode of the output transistor or the output reset transistor through a plurality of first or second signal line via holes arranged in a signal line overlap area, and the plurality of first or second signal line via holes are arranged along the first direction.

Abstract: A data driving circuit of reduced power consumption by smoothing large voltage changes includes a shift register circuit, a first latch, a second latch, a level shift circuit, a digital-to-analog (DAC) circuit, and an output circuit. The first latch circuit samples the digital signal, the second latch circuit detects a boundary value of the sampled signal in a specified grayscale range. The boundary value of the sampled signal is compared with the boundary value of a previous sampled signal and if different from the previous boundary value, the second latch outputs a compensation control signal being effective; the output circuit sets the voltage of the data line at a specified voltage before outputting the driving voltage to the data line. A display apparatus is also disclosed.

Abstract: A display apparatus includes a display panel comprising a pixel which is connected to a gate line and a data line, a gate driver configured to generate a gate signal having a gate-on voltage and a gate-off voltage and to provide the gate line with the gate signal, and a gate controller configured to generate a clock signal having a duty ratio and to provide the gate driver with the clock signal, where a mean amplitude of the clock signal in a vertical blanking period of a frame cycle is smaller than the mean amplitude of the clock signal in an active period of the frame cycle.

Abstract: Disclosed are a display device and a driving method thereof. A reference compensation voltage for compensating for a node voltage of each pixel for an image holding period after a refresh period for which image data is input in a low-speed driving mode is set. Then, the node voltage of each sub-pixel is compensated for using a corresponding reference compensation voltage on at least one frame basis at each start time and each end time of the image holding period, thereby preventing low image quality and reducing power consumption.

Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, including a pixel array region and a peripheral region; and a first scan driving circuit, a plurality of power lines, a first signal line group, and a second signal line group. The first scan driving circuit includes a plurality of cascaded first shift registers; the plurality of power lines are configured to provide a plurality of power voltages to the plurality of cascaded first shift registers in the first scan driving circuit; the first signal line group includes at least one timing signal line; the second signal line group includes a first trigger signal line configured to provide a first trigger signal to a first-stage first shift register; and the first trigger signal line is between the plurality of power lines and the pixel array region.

Abstract: A shift register unit, a gate drive circuit, a display device and a driving method are provided. The shift register unit includes a sub-shift register, a second sub-shift register and an output control circuit. The first sub-shift register includes a first output terminal and a first control node, and is configured to output a first clock signal under control of a level of the first control node. The second sub-shift register include a second output terminal and a second control node, and the second output terminal outputs a display output signal in a display phase and a random output signal in a blank phase under control of a level of the second control node. The output control circuit is connected to the first sub-shift register and the second control node, and is configured to control the level of the second control node under control of an output control signal.

Abstract: A display device with a variant-shape display region other than the rectangular display region is configured to form a scanning line drive circuit along the variant-shape display region. The scanning line drive circuit includes bus wiring group with clock wiring for supplying clocks with three or more phases and the power supply wiring for supplying power, and the unit circuits for configuring the shift register including five or more transistors. The bus wiring and the unit circuits are formed on the different regions so as not to cross with one another.

Abstract: The present disclosure relates to a semiconductor integrated circuit for driving a display, and more particularly, to a semiconductor integrated circuit for driving a display to supply gamma voltages to respective DACs through a gamma bus to which a plurality of gamma voltage circuits are connected.