Abstract: The present disclosure provides a gate driving unit, a driving method thereof, a gate driving circuit and a display device. The gate driving unit includes an input resetting module, a storage module, a pull-up node control module, a pull-down node control module and an output module. The gate driving unit further includes a clock signal control module, connected to a first control signal end, a second control signal end, a first reference clock signal end, a second reference clock signal end, a first clock signal end and a second clock signal end, and configured to, under the control of a first control signal from the first control signal end and a second control signal from the second control signal end, output clock signals at a same frequency and in opposite phases to the first clock signal end and the second clock signal end respectively in accordance with a first reference clock signal from the first reference clock signal end and a second reference clock signal from the second reference clock signal.

Abstract: A shift register, a method for driving the same, a gate driving circuit and a display device are provided. The shift register includes an input sub-circuit, an output sub-circuit, a reset sub-circuit, and a first shift output sub-circuit to an m-th shift output sub-circuit. The i-th shift output sub-circuit is connected with a third node, an (i?1)-th shift node, an i-th shift node, an (i+1)-th clock signal terminal, a first power terminal, a second power terminal, an (i?1)-th shift signal output terminal and an i-th shift signal output terminal, and is configured to supply a signal of the first power terminal to the i-th shift signal output terminal and a signal of the second power terminal to the (i?1)-th shift signal output terminal and the (i?1)-th shift node under control of the (i+1)-th clock signal terminal, i being an integer between 2 and m.

Abstract: The present application discloses a driving method for a display panel, a driving device thereof and a display device. The driving method includes: performing square wave conversion on drive data to obtain data line signals, where square wave signals generated by the conversion of different gray scales in the corresponding drive data have an identical high level, and the time of high level output is different.

Abstract: A source driver 130 includes a first latch 131 outputting a first data signal D1(1) having multiple bits (e.g., eight bits), a second latch 132 outputting a second data signal D2(1) by latching the first data signal D1(1) in a plurality of steps in units of one or more bits, a DAC 133 converting the second data signal D2(1) into an analog signal A(1), and an amplifier 134 receiving the analog signal A(1) to output a source signal S(1). The second latch 132 latches the first data signal D1(1), e.g., one bit at every clock, one bit at every plurality of clocks, a plurality of bits at every clock, or a plurality of bits at every plurality of clocks.

Abstract: A DLDO has a configuration that mitigates performance degradation associated with limit cycle oscillation (LCO). The DLDO comprises a clocked comparator, an array of power transistors, a digital controller and a clock pulsewidth reduction circuit. The digital controller comprises control logic configured to generate control signals that cause the power transistors to be turned ON or OFF in accordance with a preselected activation/deactivation control scheme. The clock pulsewidth reduction circuit receives an input clock signal having a first pulsewidth and generates the DLDO clock signal having the preselected pulsewidth that is narrower that the first pulsewidth, which is then delivered to the clock terminals of the clocked comparator and the digital controller. The narrower pulsewidth of the DLDO clock reduces the LCO mode to mitigate performance degradation caused by LCO.

Abstract: A method, a digital driving circuit and a LED display where images to be displayed in successive frames are converted from an n-bit digital image to a (m+1)-bit digital image, where m<n, by truncating, for each pixel, the (n?m) least significant bits or most significant bits of the n-bit digital image, and encoding in the (m+1) bit an indication. Each pixel of the (m+1)-bit digital image is supplied with a first drive current if the (n?m) least significant bits are truncated, and each pixel of the (m+1)-bit digital image with a second drive current if the (n?m) most significant bits are truncated, where the ratio of the first drive current to the second drive current is such that it results in a brightness ratio of 2{circumflex over (?)}(n?m), and where the indication provides information on the drive current to be used.

Abstract: A gate driver includes a gate signal generating part, a switching part and a switching controlling part. The gate signal generating part is configured to generate a gate signal including a precharge time and a normal charge time using a compensated gate on voltage and a gate off voltage. The switching part is disposed between the gate signal generating part and a gate line. The switching part is configured to apply a compensated gate signal to the gate line. The switching controlling part is configured to generate a switching control signal for controlling an operation of the switching part.

Abstract: Provided is a display panel and display device. A display area of a display panel includes a first area and a second area. The number of pixel units in each row in the first area is less than the number of pixel units in each row in the second area. The scanning lines electrically connected to the first shift registers are disposed in the first area, and the scanning lines electrically connected to the second shift registers are disposed in the second area. The first shift registers and the second shift registers are electrically connected to a first clock signal line, and the first shift registers are electrically connected to the first clock signal line through resistance compensation units.

Abstract: A display driver circuit includes a receiver that receives a still image or a moving image, a frame buffer that stores the still image received by the receiver in a still image mode, an image processor that performs an image enhancement operation on the moving image transferred from the receiver or the still image transferred from the frame buffer, and a motion processor that performs a motion compensation operation using a current frame output from the image processor and a previous frame stored in the frame buffer in a moving image mode. The previous frame is data which, in the moving image mode, are processed by the image processor before the current frame and are then stored in the frame buffer. The previous frame is output from the frame buffer to the motion processor in synchronization with the current frame.

Abstract: A display panel is provided. The display panel includes sub-pixels arranged in an array, pixel driving circuits corresponding to sub-pixels in each column being connected through at least one data line. One data driving process for the sub-pixels includes: a first phase in which a data signal transmission circuit writes a data signal for an n-th row into a data signal storage circuit, and a second phase in which a data signal writing circuit receives the data signal output by the data signal storage circuit and writes the data signal into pixel driving circuits corresponding to sub-pixels in the n-th row, and the second phase of the data driving process for the n-th row is reused as the first phase of the data driving process for a (n+1)-th row, where n is a positive integer.

Abstract: A data driving circuit proofed against excessive pixel brightness because of overvoltage on the data line comprises a shift register circuit, a first latch circuit, a second latch circuit, a level shift circuit, a DAC circuit, and an output circuit. The second latch circuit detects a change in the MSB of the data signal of a sampled signal, and outputs a signal for applying a pre-operation of the current data line. When the MSB of the sampled signal is changed, the second latch circuit outputs a pre-operation enabling signal, and whether the grayscale value of the current data line is within a specified region. If within the specified region, the second latch circuit outputs an invalid signal, and the pre-operation is disabled.

Abstract: The present disclosure is related to a shift register unit. The shift register unit may include a shift register circuit and N output control circuits, wherein N is an integer larger than or equal to 2. The shift register circuit may be respectively electrically connected with an input signal terminal, a clock signal terminal, and an output node. Among the N output control circuits, an i-th output control circuit may be respectively electrically connected with an i-th control signal terminal of N control signal terminals, the output node, and an i-th gate line of N gate lines. i is a positive integer of smaller than or equal to N. The shift register unit may be configured to sequentially output a gate driving signal to the N gate lines respectively under control of the N control signal terminals.

Abstract: A shift register circuit is provided that has an input terminal and an output terminal, and includes: an input module connected to the input terminal and a first node when the input, terminal is active, sets the first node to active; a reset module connected to the input terminal and a second node when the input terminal is active, sets the second node to inactive; an output module connected to the first node and the output terminal when the first node is active, sets the output terminal to active with a clock signal; a pull down module connected to the first node, the output terminal and the second node when the second node is active, sets the first node and the output terminal to inactive.

Abstract: The apparatus for controlling a display mirror for a vehicle includes an operation mode determiner for determining an operation mode based on a position of a mirror assembly, the mirror assembly accommodating a display for displaying an image obtained by an imaging device within an inner space formed by a mirror coupled to a surface of a mirror housing; a power supply for supplying a power to the display; and a controller configured to adjust an intensity of the power supplied to the display based on the determined operation mode. The operation mode determiner determines between a first operation mode in which an image reflected by the mirror is visible to a driver and a second operation mode in which the image obtained by the imaging device is displayed on the display. In particular, the display remains turned on in the first operation mode and the second operation mode.

Abstract: A display device includes a plurality of light emitting diodes and a plurality of pixel driver circuits for driving the plurality of light emitting diodes; a panel driver including a plurality of driver integrated circuits (ICs) and a first switching element; a timing controller including a second switching element; and a signal transmission line connecting the first switching element and the second switching element. The timing controller is configured to control the first switching element and the second switching element to transmit an image data signal from the timing controller to the panel driver through the signal transmission line during a first time period, and control the first switching element and the second switching element to receive a state data signal of the display panel from the panel driver through the signal transmission line during a second time period different from the first time period.

Abstract: The light emitting display apparatus includes a substrate including a display area including a plurality of pixel areas and a non-display area surrounding the display area, a plurality of gate lines passing through the display area of the substrate, a plurality of data lines passing through the display area of the substrate, a plurality of pixel driving power lines passing through the display area of the substrate, a plurality of pixels respectively provided in the plurality of pixel areas of the substrate and connected to an adjacent gate line, an adjacent data line, and an adjacent pixel driving power line, and a gate buffer provided in the display area of the substrate and connected to a corresponding gate line of the plurality of gate lines.

Abstract: A switch timing controlling circuit includes a first timing controlling circuit including a first inverting sub-circuit configured to form a first inverting signal that is inverted from an initial signal having a first level as an inactive level and a second level as an active level input from an initial signal terminal; a first delaying sub-circuit configured to delay a time point of the first inverting signal at which the first inverting signal changes from the first level to the second level to form a first delaying signal; and a second inverting sub-circuit configured to form a reset signal inverted from the first delaying signal; and a second timing controlling circuit including a second delaying sub-circuit configured to delay a time point of the initial signal at which the initial signal changes from the first level to the second level to form a display control signal.

Abstract: A display device comprising: a plurality of pixel electrodes supplied with a pixel signal and a display functional layer configured to perform a display operation based on the pixel signal; a plurality of touch detection electrodes configured to output a touch detection signal and perform a touch detection operation; and a controller configured to control the display operation and the touch detection operation.

Abstract: A gate driver includes clock signal lines respectively transferring clock signals, at least two of the clock signals being mutually the same; and gate driving units electrically connected to the clock signal lines, respectively and configured to sequentially generate gate signals having a multi-clock pulse based on the clock signals.

Abstract: A driver control circuit and a display device are disclosed, where the driver control circuit includes: a first transistor with a first terminal connected with a supply voltage of a main loop, and a second terminal connected with a first ground terminal; and a first control component connected with a control terminal of the first transistor, and configured to control the first transistor to be in a state of incomplete conduction in amplification region, when the supply voltage of the main loop is powered on.

Abstract: A gate driving circuit includes driving stages for providing gate signals to gate lines of a display panel. A k-th driving stage a k-th driving stage (k being equal to or greater than 2) among the driving stages includes a gate output unit configured to output a clock signal as a k-th gate signal in response to a voltage of a first node, a carry output unit configured to output the clock signal as a k-th carry signal in response to the voltage of the first node, a control unit configured to control a voltage level of the first node in response to a (k?1)th carry signal, a first discharge unit configured to discharge the k-th carry signal to a voltage level in response to the (k?1)th carry signal, and a second discharge unit configured to discharge the k-th carry signal to a voltage level in response to a discharge signal.

Abstract: A display device that achieves both high-accuracy sensing by a touch sensor unit and smooth input using the touch sensor unit is provided. The display device includes a display unit and the touch sensor unit. The touch sensor unit performs touch sensing operation at a different timing from display image rewriting by the display unit, whereby the high-accuracy sensing can be achieved. The display unit has a function of rewriting a display image only in a region that needs to be rewritten. In the case where the entire display region is not necessarily rewritten, the time for the sensing operation by the touch sensor unit can be lengthened, whereby the smooth input can be achieved.

Abstract: A display device includes a display panel having a curved side or a polygonal side, the display panel including a plurality of pixels in a display region, a gate driver including a plurality of normal stages connected to each other for outputting gate signals to the pixels via a plurality of gate lines, and a plurality of dummy stages between some of the normal stages, and a data driver providing data signals to the pixels via a plurality of data lines.

Abstract: A gate driving unit and a gate driving method are provided. The gate driving unit includes an input unit, a driving unit, a pull-down unit, and a pull-down control unit. The pull-down unit has an output terminal of a current stage cascaded signal and an output terminal; in the pull-up phase, the output terminal of the current stage cascaded signal and the output terminal output signal, a voltage of the output terminal of the current stage cascaded signal is pulled down to a first reference low electric level, and a voltage of the output terminal is pulled down to a second reference low electric level.

Abstract: A shift register unit, a gate driving circuit, a display device and a driving method are provided. The shift register unit includes an input circuit, an output circuit, a first reset circuit, a second reset circuit and a common reset circuit. The input circuit is configured to control a level of a first node in response to an input signal; the output circuit includes an output terminal and is configured to output an output voltage signal to the output terminal under control of the level of the first node; the common reset circuit includes a reset control terminal and is configured to reset the first node when a reset turn-on signal is input to the reset control terminal; and the first reset circuit is configured to provide the reset turn-on signal to the reset control terminal in response to a first reset signal.

Abstract: The display device is provided with a precharge power source that supplies only precharge voltages (precharge voltages corresponding to the maximum gradation value for each of the positive polarity and the negative polarity) corresponding to one gradation value. The source driver includes a data voltage generation circuit configured to generate data voltage depending on input data and an output circuit configured to apply the data voltage to each source bus line after applying precharge voltage. The output circuit changes the length of the precharging period during which the precharge voltage is applied to each source bus line, depending on input data.

Abstract: A flexible display device including a first display area including first data lines arranged in a first direction, first scan lines arranged in a second direction intersecting the first direction, and first pixels arranged in regions defined by the first data lines and the first scan lines, a second display area including second data lines arranged in the first direction, second scan lines arranged in the second direction, and second pixels arranged in regions defined by the second data lines and the second scan lines, a first bending area disposed between the first and second display areas, a first circuit unit disposed adjacent to a first side of the first display area, a second circuit unit disposed adjacent to a second side of the first display area, and a third circuit unit disposed adjacent to a first side of the second display area.

Abstract: A chip-on-film package includes a base substrate on which a first pad region, a second pad region, and a third region located between the first pad region and the second pad region are defined, a dummy pad disposed on the first pad region, input pads disposed on the first pad region, output pads disposed on the second region, a first detection line disposed on the base substrate, and a second detection line disposed on the base substrate. The first detection line is connected to a first input pad and a second input pad via the second pad region to form a first loop between the first input pad and the second input pad, and the second detection line is connected to the dummy pad and the first detection line via the third region to form a second loop between the dummy pad and the first input pad.

Abstract: A display may have rows and columns of pixels that form an active area for displaying images. A display driver integrated circuit may provide multiplexed data signals to demultiplexer circuitry in the display. The demultiplexer circuitry may demultiplex the data signals and provide the demultiplexed data signals to the pixels on data lines. Gate lines may control the loading of the data signals into the pixels. The display may have a length dimension and a width dimension that is shorter than the length dimension. The data lines may extend parallel to the width dimension and the gate lines may extend parallel to the length dimension such that there are more data lines than gate lines in the display. A notch that is free of pixels may extend into the active area. Data lines extending parallel to the width dimension of the display may be routed around the notch.

Abstract: A display device including: a controller including: a zone splitting block configured to divide input image data into a plurality of partial image data respectively corresponding to a plurality of partial panel zones of the display panel; a plurality of panel zone frequency deciding blocks configured to determine a plurality of driving frequencies for the plurality of partial panel zones by analyzing the plurality of partial image data, respectively; a non-driving period setting block configured to classify a plurality of frame periods into a driving frame period and a non-driving frame period based on a maximum driving frequency of the plurality of driving frequencies; and a scan driver control block configured to provide the scan driver input signal to the scan driver in the driving frame period, and to not provide the scan driver input signal to the scan driver in the non-driving frame period.

Abstract: Provided is an electric field generating substrate and a liquid crystal lens containing the same. The electric field generating substrate contains: a first substrate; and a first electric field generating unit disposed on the first substrate. The first electric field generating unit contains: a first main electrode; a second main electrode; and a first sub-electrode disposed between the first main electrode and the second main electrode. The first sub-electrode electrically connects to the first main electrode and the second main electrode. A first resistor is disposed between the first main electrode and the first sub-electrode, and a second resistor is disposed between the first sub-electrode and the second main electrode. In addition, the first main electrode, the second main electrode and the first sub-electrode are substantially parallel to each other.

Abstract: An object is to provide a technique capable of increasing a display quality of a liquid crystal display device. A liquid crystal display device includes a liquid crystal panel including a liquid crystal layer with a liquid crystal, an electrode applying voltage to the liquid crystal, and a pair of polarization plates sandwiching the liquid crystal layer. A first voltage is applied to a liquid crystal in a local area in the liquid crystal panel when a transmissivity of the local area is set to a predetermined local minimum value, and a second voltage is applied to a liquid crystal in a remaining area other than the local area in the liquid crystal panel when the transmissivity of the remaining area is set to a predetermined local minimum value. The first voltage is different from the second voltage.

Abstract: According to one embodiment, a display device includes an insulating substrate, a first insulating film, terminal portions and a pattern. The first insulating film covers the insulating substrate. The terminal portions are disposed on the first insulating film. The pattern is between the insulating substrate and the first insulating film. The pattern is formed by a semiconductor or a light-shielding material, and the pattern is covered with the first insulating film. The pattern is located just under a first terminal and a second terminal of the terminal portions.

Abstract: It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.

Abstract: A source driver includes a gamma voltage generator to generate gamma voltages having mutually different voltage levels, a digital-to-analog converter to generate a data voltage corresponding to a grayscale value using the gamma voltages, an output buffer unit to output the data voltage, and a chopping controller to generate a chopping control signal, and to provide the chopping control signal to the output buffer unit. The output buffer unit includes an amplifier connected to an output terminal of the digital-to-analog converter, and a chopping circuit to periodically change a polarity of an offset of the amplifier in response to the chopping control signal. The chopping controller is to change a slew rate of the chopping control signal.

Abstract: A display device includes a display panel, a first connection circuit board, a second connection circuit board, and a sealing member. The display panel may include an insulation layer, a first pad, and a second pad. A distance between a top surface of the insulation layer and a bottom surface of the second connection circuit board may be substantially the same as that between the top surface of the insulation layer and a top surface of the first connection circuit board.

Abstract: A gate driver and a display device using the same are disclosed. The gate driver includes a plurality of stages connected in a cascade connection manner, and each of the stages include a clock input configured to receive a shift clock signal, a first output terminal, and a second output terminal. Each of the stages generates a first output voltage that is transmitted to another stage through the first output terminal and a second output voltage that is supplied to a gate line of a display panel through the second output terminal. Each of the stages includes a first diode connected between the clock input and the first output terminal.

Abstract: A method of driving a display by communicating with a controller through a first channel and a second channel includes; generating recovery data from a signal received through the first channel during a frame data period, detecting a vertical blank period between frame data periods, checking a training trigger event history during the vertical blank period, and during the vertical blank period, transmitting a training request direct to the first channel through the second channel when there is a training trigger event history.

Abstract: A display device includes: first and second dots arranged on a first horizontal line in a first direction, each of the first and second dots including first to fourth pixels; a switch unit configured to selectively couple first to fourth output lines respectively to the first to fourth pixels of each of the first and second dots, in response to a first control signal and a second control signal; and a data driver configured to supply data voltages to the first to fourth output lines in a time-sharing manner. The data driver may include: a data processor configured to generate data signals corresponding to the first to fourth output lines; and first to fourth digital-to-analog converters (DACs) configured to convert the data signals into the data voltages. Each of the first to fourth DACs may be supplied with a corresponding one of first to fourth gamma voltages.

Abstract: A driving circuit, a driving method and a driving apparatus, wherein the driving circuit includes: a driving signal generation sub-circuit; a plurality of first signal lines, configured to receive the driving signal generated from the driving signal generation sub-circuit; a plurality of second signal lines, configured to output the driving signal to the plurality of pixels in the display panel; a switch sub-circuit, set between the plurality of first signal lines and the plurality of second signal lines, and configured to selectively connect a part of the plurality of second signal lines or the plurality of first signal lines and the plurality of second signal lines; and a control sub-circuit, configured to control turn-on or turn-off of the switch sub-circuit, so that the plurality of pixels of the display panel are driven in a first mode or in a second mode.

Abstract: A display device comprises: a panel comprising a pixel array; a data driver for outputting video data signals to the panel; and a latch part for receiving the video data signals from the data driver and outputting the received video data signals to the pixel array. With this configuration, the number of data drive ICs of the data driver can be reduced while maintaining the panel driving frequency.

Abstract: A gate driving circuit includes a plurality of stages. Adjacent two stages from among the plurality of stages constitute a stage pair. The adjacent two stages in the stage pair include switching elements connected with each other. When a carry signal of an N-th stage in the stage pair has a defect, the N-th stage is configured to output a carry signal of an (N+1)-th stage in the stage pair. N is a positive integer. When a defect has occurred at a carry signal of a stage in a stage pair, the carry signal of the stage having the defect may be repaired by a carry signal of another stage in the stage pair.

Abstract: A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

Abstract: A shift register unit, a driving method, a gate driving circuit and a display device are provided. The shift register unit includes: a starting circuit configured to control, under control of a first clock signal input terminal, turning on or off coupling between a first node and a starting voltage input terminal; a first capacitor circuit, having a first terminal being coupled to a second clock signal input terminal, and a second terminal being coupled to the first node; a first node control circuit configured to control, under control of a third node, turning on or off coupling between the first node and a first level input terminal; a potential control circuit configured to control, under control of the first node, turning on or off coupling between the second node and a second level input terminal; a second capacitor circuit; a second node control circuit; an output circuit; and a third node control circuit.

Abstract: The invention provides a semiconductor device and a shift register, in which low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire. One of a source and a drain of the third transistor is connected to a second wire, the other of the source and the drain thereof is connected to the gate electrode of the second transistor, and a gate electrode thereof is connected to a fourth wire.

Abstract: The disclosure discloses a shift register, a gate drive circuit, a driving method thereof, and a display device, and the shift register includes: an input sub-circuit, an output sub-circuit, and an output control sub-circuit, where the input sub-circuit is configured to provide a signal of a first reference voltage signal terminal to a pull-up node under control of an input signal terminal; the output sub-circuit is configured to provide a signal of a clock signal terminal to a first signal output terminal under control of a potential of the pull-up node; and the output control sub-circuit is configured to provide a signal of the first signal output terminal to a second signal output terminal under joint control of an output control signal terminal, a third reference voltage signal terminal, and a fourth reference voltage signal terminal.

Abstract: The present invention teaches a Gate Driver on Array (GOA) circuit for a display panel. The GOA circuit includes a first dummy GOA unit and/or a second dummy GOA unit not connecting scan lines of the display panel's active area, and normal GOA units connecting scan lines of the active area. The normal GOA units are cascaded into a chain. The first dummy GOA unit is cascaded to a first normal GOA unit of the chain and/or the second dummy GOA unit is cascaded to a last normal GOA unit of the chain. A start signal of the display panel's vertical scanning as a cascaded signal is input into the first dummy GOA unit and/or the second dummy GOA unit. The GOA circuit excludes the line of afterimage from the active area, thereby allowing the fast black frame insertion after abnormal shutdown.

Abstract: This display device is provided with: a plurality of pixels (3); a plurality of source lines (SL); a source drive circuit (12a); and a plurality of switches (40, 41). The plurality of pixels are arranged in a matrix, and form a display region (10a) in which an image is displayed. The plurality of source lines (SL) are wired in the row direction of the pixel matrix on the display region, and connected to the respective pixels. The source drive circuit has a plurality of signal lines (PL) through which signals supplied to the respective pixels via the source lines are outputted. The switches are provided between the source lines and the signal lines. More than one of the source lines are wired to the pixels in the same row in the matrix. The source lines (SLe, SLo) for pixels in the same row and one of the signal lines of the source drive circuit, are connected via the switches.

Abstract: Systems, apparatuses and methods may provide for an electronic spine and one or more digital pages removably attached to the electronic spine, wherein the one or more digital pages include a first side with a first flexible display and a second side with a second flexible display. In one example, the system may further include a magnetic interface, wherein the digital page is removably attached to the electronic spine via the magnetic interface.

Abstract: A stage and a scan driver including the same for supplying a scan signal using a stage formed of P-type transistors to prevent output of an unwanted noise in a period where the scan signal is not supplied.