Abstract: A matrix-array detector includes an array of pixels that are sensitive to a physical effect and arranged in a matrix along rows and down columns, each pixel generating a signal according to the physical effect; row conductors, each allowing the pixels of one row to be driven; driver modules delivering selection signals to the row conductors, the driver modules being configured to deliver signals according to either of two levels, one being a high level allowing one of the rows of pixels to be selected and the other being a low level not allowing it to be selected. The detector further comprises impedance modules that are connected to each of the row conductors and configured to decrease the impedance of each row conductor and to keep the impedance of each row conductor low in a phase of reading the array of pixels as long as the corresponding selection signal is at the low level, the impedance modules being separate from the driver modules.

Abstract: Some embodiments of the present disclosure provide a shift register and a method of driving the same, a gate driving circuit, and a display device. The shift register includes a first input sub-circuit for outputting a voltage on a first control voltage terminal to a pull-up node under control of a first signal input terminal; n output sub-circuits for outputting signal from output clock signal terminals to signal output terminals in sequence under control of the pull-up node; a first pull-down control sub-circuit for outputting a voltage on the first control voltage terminal to a pull-down node under control of a first clock signal terminal; a second pull-down control sub-circuit for pulling down a voltage on the pull-down node to a first voltage under control of the pull-up node; and a pull-down sub-circuit for pulling down a voltage on the pull-up node to the first voltage under control of the pull-down node.

Abstract: An organic light emitting display device including: a display panel including a plurality of pixels; a gate driver including a plurality of stage groups each including at least one stage providing a gate signal to the pixels; a timing controller providing a first stage initiation signal or a second stage initiation signal to the at least one stage; and a first stage initiation line and a second stage initiation line transmitting the first stage initiation signal and the second stage initiation signal from the timing controller to the gate driver.

Abstract: A driving method and a driving device of a display panel, and a display device are provided, wherein, the driving method of the display panel comprises steps of: turning on gates of transistors of an Nth row of pixels at a first rising edge moment of a clock signal; charging the Nth row of pixels according to a data signal; turning on gates of transistors of an (N+1)th row of pixels before a second rising edge moment of the clock signal; charging the (N+1)th row of pixels according to the data signal; wherein the second rising edge moment follows after the first rising edge moment and neighbors the first rising edge moment, where N is a positive integer.

Abstract: A shift register unit and a method for driving the same, a gate driving circuit, and a display apparatus are disclosed. The shift register unit includes: an input circuit configured to transmit an input signal to a pull-up node; an output circuit configured to transmit a clock signal to an output signal terminal under control of a voltage at the pull-up node; a first reset circuit configured to reset the pull-up node to a first level under control of a first reset signal; a first pull-down control circuit configured to control levels at the pull-up node and the output signal terminal under control of a first control signal; and a first voltage control circuit electrically connected to a second control signal terminal, and configured to control a voltage signal waveform at the first pull-down node under control of a second control signal.

Abstract: A shift register unit, a gate driving circuit, a display device and a driving method are disclosed. The shift register unit includes an input circuit, a first reset circuit, an output circuit, and a node control circuit. The input circuit is configured to control a level of a first node in response to an input signal; the first reset circuit is configured to reset the first node in response to the first reset signal; the output circuit is configured to output a driving signal to an output terminal under control of the level of the first node; and the node control circuit is configured to control a level of a second node in response to the driving signal.

Abstract: A gate driver on array (GOA) circuit and a thin film transistor (TFT) substrate are provided. The GOA circuit includes a pull-up control module, a pull-up module, a pull-down module, a pull-down maintaining module, and a switch module. The switch module is configured to be turned off after a preset time delay when the pull-up module outputs a current-level scan signal at a high potential. The bootstrap module is configured to maintain a pull-up control signal at a high potential within the preset time delay of the switch module, and when the switch module is turned off, the bootstrap module cuts off a connection with the current-level scan signal.

Abstract: An array substrate, a touch display panel and a touch display device are provided. In the array substrate, the number of inverters in a second buffer unit is smaller than the number of inverters in a first buffer unit, or a size of an inverter in the second buffer unit is smaller than a size of an inverter in the first buffer unit, or the number of inverters in the second buffer unit is smaller than the number of inverters in the first buffer unit and the size of the inverter in the second buffer unit is smaller than the size of the inverter in the first buffer unit.

Abstract: By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

Abstract: A driving method and a driving device of a display panel are provided. The driving method includes: controlling a timing controller to output a start signal to a level shifter; configuring a parameter of a register of the level shifter; and controlling the level shifter to generate a drive signal according to the parameter upon receiving the start signal, and outputting the drive signal to a first drive circuit.

Abstract: An electronic device may include a display such as a light-emitting diode display. The electronic device may be a head-mounted device that provides a virtual reality or augmented reality environment to a user. To reduce artifacts in the display, a display may be operable in both a normal scanning mode and a partial scanning mode. In the normal scanning mode, every row of the display may be enabled to emit light in each frame. In the partial scanning mode, only a subset of the rows of the display may be enabled to emit light in each frame. The display may have a higher refresh rate in the partial scanning mode than in the normal scanning mode. To ensure uniform transistor stress across the display, the scanning driver for the display may scan the disabled rows in the partial scanning mode even though the rows will not be used to emit light.

Abstract: A display apparatus is disclosed, which is capable of reducing the number of output channels in a column driving circuit. The display apparatus comprises a display portion including pixels arranged in pixel areas defined by row line groups and column line groups, a row driving circuit configured to supply a scan control signal to the row line groups, a column driving circuit configured to sequentially output a data signal every horizontal period, and a data distribution circuit configured to sequentially supply the data signal, which is sequentially output from each of output channels of the column driving circuit, to the column line groups in accordance with a data selection signal, wherein a period of the data selection signal is longer than 1 horizontal period.

Abstract: A GOA circuit and a display panel are provided. The GOA circuit could reduce the number of transistors electrically connected to the first node in the GOA circuit. Thus, the number of the current leakage paths is also reduced. In addition, the GOA circuit could real-time compensate the pixel circuit in the blank time period and thus raise the stability of the GOA circuit.

Abstract: According to an aspect, a display device includes: a plurality of sub-pixels, each sub-pixel including at least one memory; a setting circuit configured to select either a first mode in which a still image is displayed or a second mode in which a moving image is displayed; and a switching circuit configured to switch coupling between the sub-pixels and the memories according to the selection made by the setting circuit. The first mode is a mode in which each of the sub-pixels is coupled to one of the at least one memory included in the sub-pixel, and the second mode is a mode including a time period in which at least one of the sub-pixels is coupled to the at least one memory included in another of the sub-pixels.

Abstract: A shift register and a corresponding driving method, a gate driving circuit and a display device, the shift registers includes an input and reset circuit, a first output circuit, a second output circuit, a first pull-down circuit and a second pull-down circuit; the first output circuit and the second output circuit output gate driving signals according to potentials at a first clock signal terminal and a second clock signal terminal respectively, the first pull-down circuit and the second pull-down circuit reset potentials at a pull up node, a first output terminal and a second output terminal according to potentials at a first pull-down node a second pull-down node respectively.

Abstract: A display device comprises a plurality of pixels and a plurality of multiplexers. Each of the plurality of multiplexers is coupled with N data lines, and configured to receive N?1 switching signals and a data signal. N is a positive integer larger than or equal to 3, and each of the N data lines is coupled with one column of pixels of the plurality of pixels. When any of the N?1 switching signals has an enabling voltage level, the multiplexer is disabled from transmitting the data signal to an N-th data line of the N data lines. When each of the N?1 switching signals has a disabling voltage level, the multiplexer transmits the data signal to the N-th data line.

Abstract: A method implemented in an electronic device is provided. The method includes determining at least one update of content of at least one application, wherein the at least one update is associated with an activity related to the content accessed by a user, generating at least one statement corresponding to the at least one update of the content of the at least one application in accordance with the activity related to the content.

Abstract: A shift register unit cascaded in a gate drive circuit, wherein the shift register unit comprises: a control circuit configured to output a control signal, at least two buffer circuits coupled to the control circuit, each of the at least two buffer circuits configured to output scan signal to a gate line. As such, the scan signals output from the at least two buffer circuits would be synchronized so that the gate lines respectively coupled to the two buffer circuits can be scanned simultaneously.

Abstract: A display driver includes a D/A converter circuit for outputting a gradation voltage, and an amplifier circuit that is input with a gradation voltage at an input node. The amplifier circuit includes an operational amplifier, resistance provided between the input node and a node, resistance provided between a node and an output node of the operational amplifier, and an adjustment resistance circuit. The adjustment resistance circuit adjusts a first adjustment resistance value, that is a resistance value between a node and an inverting input node of the operational amplifier, and a second adjustment resistance value, that is a resistance value between the node and the inverting input node.

Abstract: A voltage control circuit and a method of controlling the same, and a display device are provided. The comparison sub-circuit is coupled to a first reference voltage end, a second reference voltage end, a feedback voltage end and a comparison output end which is coupled to the switching sub-circuit. The switching sub-circuit is further coupled to an output voltage end, an initial voltage end and a replacement voltage end. The comparison sub-circuit determines whether a voltage of the feedback voltage end is between the first reference voltage and the second reference voltage. The switching sub-circuit transmits a voltage of the initial voltage end to the output voltage end in response to a first control signal of the comparison output end; transmit a voltage of the replacement voltage end to the output voltage end in response to a second control signal of the comparison output end.

Abstract: The disclosure discloses a display panel, a method for compensating for the same, and a display device. The display panel includes a primary driver chip and at least one slave driver chip, each of which includes a gamma circuit; a processing circuit; and signal collectors on respective driver chips, configured to acquire current voltage at corresponding binding points of respective gamma circuits. The processing circuit is configured to compare current voltage at corresponding binding points of respective gamma circuits on respective slave driver chips with current voltage at a corresponding binding point of a gamma circuit on the primary driver chip, and to compensate for voltage to be output at the corresponding binding points of the respective gamma circuits on the respective slave driver chips according to comparison results so that current voltage at the corresponding binding points of the respective gamma circuits on the respective driver chips are same.

Abstract: A display device that achieves both high-accuracy sensing by a touch sensor unit and smooth input using the touch sensor unit is provided. The display device includes a display unit and the touch sensor unit. The touch sensor unit performs touch sensing operation at a different timing from display image rewriting by the display unit, whereby the high-accuracy sensing can be achieved. The display unit has a function of rewriting a display image only in a region that needs to be rewritten. In the case where the entire display region is not necessarily rewritten, the time for the sensing operation by the touch sensor unit can be lengthened, whereby the smooth input can be achieved.

Abstract: A shift register includes a pull-up control circuit, at least two output circuits, a pull-down control circuit, at least two pull-down circuits, and at least two output signal terminals. The pull-up control circuit, the at least two output circuits, and the pull-down control circuit are respectively coupled to the pull-up node; the pull-down control circuit, the at least two pull-down circuits, and the pull-up control circuit are respectively coupled to the pull-down node. Each of the at least two output circuits is coupled to a corresponding one of the at least two output signal terminals; each of the at least two pull-down circuits is coupled to a corresponding one of the at least two output signal terminals; and each of the at least two output signal terminals is coupled to a corresponding one of at least two gate lines.

Abstract: A gate driving circuit includes 4n stages of shift register units, and n stages of inversion units. One of the inversion units is disposed between every two groups of four adjacent stages of shift register units. A (n+1)th stage of the inversion units is disposed between two of the shift register units, and configured to output in inverted phases gate driving signals outputted by the two shift register units in a heavy-load screen stage, and output in positive phases gate driving signals outputted by the two shift register units in a normal screen stage.

Abstract: The present disclosure provides a driving method, a display panel and a control method thereof. The driving circuit is configured to drive pixel circuits arranged in an array. The driving circuit includes a plurality of driving modules and a plurality of data writing modules. Each of the plurality of driving modules is connected to two adjacent rows of the pixel circuits through a controlling line and is configured to drive the two adjacent rows of the pixel circuits simultaneously. Each of the plurality of data writing modules is connected to a data line and one column of the pixel circuits, respectively, and is configured to write display data of the data line into a pixel circuit of odd row and a pixel circuit of even row in the one column of pixel circuits in a time sharing manner in response to the driving modules driving the pixel circuits.

Abstract: A gate driver can include a plurality of stages, each of the plurality of stages including a transistor T1 configured to apply a start signal of a gate-on voltage to a node Q in response to a clock signal and activate the node Q; a transistor T7 configured to supply an emission signal of the gate-on voltage to an output node when a node QA is bootstrapped in synchronization with a timing at which the node Q is activated; a QB controller configured to activate a node QB based on the clock signal, the start signal and a voltage of the node Q; and a transistor T8 configured to supply the emission signal of a gate-off voltage to the output node while the node QB is activated prior to activation of the node Q.

Abstract: An array substrate includes a plurality of sub-pixels and at least one light photosensitive detection assembly, and each photosensitive detection assembly corresponds to at least one sub-pixel. The at least one photosensitive detection assembly includes: a photosensitive element and a signal reading element coupled to the photosensitive element and a first reading signal line, the photosensitive element is configured to detect a luminance of a corresponding sub-pixel, and output a light detection signal according to the luminance of the corresponding sub-pixel. The signal reading element is configured to read the light detection signal output by the photosensitive element, and output a first detection signal to the first reading signal line according to the light detection signal.

Abstract: A Gate Driver on Array circuit and a driving method thereof, and a display device. The Gate Driver on Array circuit includes at least one group of shift registers, each group of shift registers includes a plurality of shift registers in cascade, the plurality of shift registers including a first shift register, a second shift register connected after the first shift register, and a third shift register connected after the second shift register, wherein the third shift register is provided with an initializing terminal connected to an output terminal of the first shift register.

Abstract: A display driver includes a plurality of source amplifiers configured to drive a plurality of source lines of a display panel, and an amplifier control system configured to control the source amplifiers. Each of the source amplifiers is configured to drive a source line with a drive voltage corresponding to a grayscale value specified by an image data associated with each of the source amplifiers. The amplifier control system is configured to control execution and stopping of an amplifying operation of each of the source amplifiers based on the image data associated with each of the source amplifiers is a grayscale value corresponding to black portions of the display panel.

Abstract: A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node a rises. When the potential of the node ? reaches (VDD?VthN), the node ? became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105.

Abstract: A display device includes: pixel columns including pixels arranged along a first direction; pixel rows including pixels arranged along a second direction crossing the first direction; data lines connected to respective pixel columns, each of the data lines including a first sub-data line provided at one side of a corresponding pixel column and a second sub-data line provided at another side of the corresponding pixel column; scan lines extending along the second direction and connected to respective pixel rows; and a power line to supply driving power to the pixels, one of the pixels of the pixel columns is connected to the first sub-data line, and a pixel adjacent to the pixel connected to the first sub-data line is connected to the second sub-data line, and the first sub-data line and the second sub-data line in the same pixel column are on different layers from each other.

Abstract: The present disclosure provides a shift register circuitry, a gate driving circuit, and a display device. The shift register circuitry of the present disclosure includes a first shift register unit, a second shift register unit, a pull-down control sub-circuit (20), and a pull-down sub-circuit (30); wherein the first shift register unit includes a first input Sub-circuit (11), a first output sub-circuit (12), a first reset sub-circuit, and a first noise reduction sub-circuit (14); a second shift register unit includes a second input sub-circuit (21), a second output sub-circuit (22), a second reset sub-circuit and a second noise reduction sub-circuit (24).

Abstract: A display device includes drivers. The drivers apply a voltage having a polarity opposite to a polarity of a voltage applied to red, green, blue, and white picture elements in one first picture element columns to red, green, blue, and white picture elements in another first picture element columns adjacent to the one first picture element columns, and apply a voltage having a polarity opposite to a polarity of a voltage applied to red, green, blue, and white picture elements in one second picture element columns to red, green, blue, and white picture elements in another second picture element columns adjacent to the one second picture element columns.

Abstract: A display device in one embodiment includes a display panel configured to display an image in first and second display areas, a plurality of first gate lines corresponding to the first display area, and a plurality of second gate lines separated from the first gate lines and corresponding to the second display area. Accordingly, the distance between the first gate lines of the first display area and the second gate lines of the second display area is maximized to prevent static electricity from occurring between the electrodes, thereby increasing product yield.

Abstract: The present invention discloses a driving circuit of display device, including an output module, a signal amplification module, a plurality of signal conversion modules, a plurality of column scanning signals. The output module is used for providing a plurality of scanning signals for displaying. The signal amplification module is used for amplifying the plurality of scanning signals. The plurality of signal conversion modules are used for converting each of the plurality of amplified scanning signals into at least two column scanning signals. The plurality of column scanning signals are used for transferring the plurality of column scanning signals to a display control circuit of display device.

Abstract: A structured light projector and a method for structured light projection are disclosed. The structured light projector includes a projection module, a liquid crystal (LC) lens and a processor. The projection module is configured to project an optical pattern. The (LC) lens module is disposed over the projection module, and is configured to focus the optical pattern onto a region of space. The processor is configured to generate a control signal depending on an environment temperature of the projection module for controlling the LC lens.

Abstract: A display device includes a plurality of first pixels coupled to first scan lines and data lines and a plurality of second pixels coupled to second scan lines and the data lines. Each of the first scan lines receives 2i first scan signals during a frame period. Each of the second scan lines receives i second scan signals during the frame period, where i is a natural number.

Abstract: Embodiments of the application provide a shift register comprising a shift signal generating circuit and at least two time-sharing controlling circuits. The shift signal generating circuit may be configured to generate a shift signal. Each of the time-sharing controlling circuits comprises a first driving sub-circuit and a second driving sub-circuit, wherein the first driving sub-circuit is configured to enable the time-sharing controlling circuit to output the shift signal during the preset period, and the second driving sub-circuit is configured to enable the time-sharing controlling circuit to output an invalid signal during the non-preset period. During a driving cycle, the first driving sub-circuits in each of the at least two time-sharing controlling circuits are turned on sequentially, so that each of the at least two time-dividing controlling circuits outputs the shift signal sequentially.

Abstract: A display apparatus includes first and second display areas, first pixels in the first display area, and second pixels in the second display area. Gate lines are connected to the first pixels. First gate electrode lines are connected to the second pixels. First gate driving lines are respectively connected to the first gate electrode lines. A first gate driver outputs first scanning signals to the first pixels via the gate lines. A second gate driver outputs second scanning signals to the second pixels via the first gate driving lines and the first gate electrode lines.

Abstract: The embodiments of the present application disclose a shift register unit and a method for driving the same, a gate driving circuit and a method for driving the same, and a display apparatus. The shift register unit comprises an input sub-circuit connected to an input signal terminal and a pull-up control node, and configured to charge the pull-up control node under control of an input signal; and an output sub-circuit connected to the pull-up control node, a clock signal terminal, a first voltage terminal, and an output signal terminal, and configured to output a first constant voltage to the output signal terminal under control of a clock signal and the pull-up control node.

Abstract: The display evenness of a large or high-resolution display device is improved. The display device includes a source driver, a first gate driver, a second gate driver, a first pixel, and a second pixel. The first pixel is electrically connected to the source driver and the first gate driver. The second pixel is electrically connected to the source driver and the second gate driver. The first pixel is located closer to the source driver than the second pixel is. The first gate driver has a function of supplying a first write signal to the first pixel. The second gate driver has a function of supplying a second write signal to the second pixel. The pulse width of the second write signal is larger than the pulse width of the first write signal.

Abstract: A shift register, a method of driving a shift register, a gate driving circuit and a display device are disclosed. The shift register includes an input circuit, a first output circuit and a second output circuit. The input circuit is connected to a first node and is configured to control a level of the first node in response to an input signal. The first output circuit is connected to the first node, a first output terminal and a third output terminal, and is configured to transmit a received clock signal to the first output terminal and the third output terminal in response to the level of the first node. The second output circuit is connected to the first node, a first voltage terminal, a second voltage terminal and a second node.

Abstract: Embodiments of a multi-form factor Information Handling System (IHS) with automatically reconfigurable hardware keys with automatically reconfigurable hardware keys are described. In an illustrative, non-limiting embodiment, an IHS may include: a processor; and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution by the processor, cause the IHS to: identify a posture of a second display relative to a first display; and in response to a keyboard event, execute a command selected, at least in part, based upon the posture.

Abstract: A driving method of a display panel is provided, including setting the first red, first green, first blue, second red, second green, and second blue multiplexed signals. In the 2i?1th multiplexing period, the charging time of the sub-pixels corresponding to the switching units controlled by the first red, the first green, and the first blue multiplexed signals is earlier than that controlled by the second red, the second green, and the second blue multiplexed signals. While In the 2ith multiplexing period, the charging time of the sub-pixels corresponding to the switching units controlled by the first red, the first green, and the first blue multiplexed signals is later than that controlled by the second red, the second green, and the second blue multiplexed signals. The method will eliminate the stripe feeling of the scream picture displayed on the display panel and so improve the display quality.

Abstract: A display device comprises a plurality of pixel unit sets and a plurality of common electrode (VCOM) signal generation circuits. Each of the pixel unit sets comprises a first portion pixel unit and a second portion pixel unit. Each of the first portion pixel unit and each of the second portion pixel unit comprise a plurality rows of pixel units. Each row of the pixel units comprises a plurality of pixel units. The VCOM signal generation circuits are respectively coupled to one of the pixel unit sets. The VCOM signal generation circuits are divided into a plurality of groups of number m. The VCOM signal generation circuits in each of the groups generate a first VCOM signal and a second VCOM signal to the coupled pixel unit set according to a first clock signal, a second clock signal and one of a plurality control signal sets of number m.

Abstract: Disclosed is a source signal driving apparatus capable of implementing channels at high integration density. The source signal driving apparatus is configured to sequentially output source signals by sequentially delaying enable time points of enable signals provided to channel circuits.

Abstract: Regarding any gate clock signal transmission line, assuming that two signal transmission lines that are adjacent to the focused gate clock signal transmission line are defined as a first adjacent signal line and a second adjacent signal line, and that a combination of a potential of the first adjacent signal line and a potential of the second adjacent signal line when a potential of the focused gate clock signal transmission line changes from a high level to a low level is defined as an adjacent signal line state, a plurality of signal transmission lines including the plurality of gate clock signal transmission lines are disposed between the signal input terminal and the gate driver so that the adjacent signal line state for all of the plurality of gate clock signal transmission lines are the same.

Abstract: A display apparatus includes a display panel configured to display an image. A gate driver is configured to output a plurality of gate signals to the display panel. A data driver includes a first area and a second area. The first area of the data driver includes a first channel group configured to output first data voltages in a first output sequence. The second area of the data driver includes a second channel group configured to output second data voltages in a second output sequence opposite to the first output sequence.

Abstract: A display device includes: a pixel unit including first pixels in a first pixel region, second pixels in a second pixel region, and third pixels in a third pixel region; a first scan driver configured to drive first scan lines coupled to the first pixels; a second scan driver configured to drive second scan lines coupled to the second pixels; and a third scan driver configured to drive third scan lines coupled to the third pixels, wherein the first scan driver, the second scan driver, and the third scan driver differently set a supply order of a scan signal supplied to the first scan lines, the second scan lines, and the third scan lines, corresponding to a first mode and a second mode different from the first mode.

Abstract: An emission control driver includes stages sequentially outputting emission control signals through emission control lines. Each stage includes a first signal processor receiving a first voltage and generating first and second signals in response to first and second sub-control signals, a second signal processor receiving a second voltage having a level higher than a level of the first voltage and generating third and fourth signals in response to the third sub-control signal, the first signal, and the second signal, and a third signal processor receiving the first and second voltages and generating the emission control signal in response to the third and fourth signals. The first signal processor of each stage receives the emission control signal output from a previous stage as the first sub-control signal, and the first signal processor of a first stage among the stages receives a start signal as the first sub-control signal.