Abstract: Provided is a document providing system, a providing-side apparatus, and a display-side apparatus, capable of increasing the usability. The providing-side apparatus 1 broadcasts the designated information for specifying the designated document. The display-side apparatus 2 holds the documents to be provided, and upon receiving the broadcasted document specifying information, the display-side apparatus 2 searches the held documents to retrieve a document specified by the received information, and displays the retrieved document.

Abstract: Embodiments disclosed herein generally relate to techniques for routing data through one or more cascaded memory modules. Each memory module can include a plurality of data buffers. Each data buffer includes a plurality of ports for routing data to and/or from other memory modules. In one embodiment, the data buffer is configured to route write data to DRAM devices on a first memory module or route write data to a data buffer of at least one downstream memory module. The data buffer is also configured to receive read data from a DRAM device of the first memory module or receive read data from a downstream memory module.

Abstract: In on embodiment, a hybrid fabric interconnects multiple graphics processor cores within a processor. The hybrid fabric interconnect includes multiple data channels, including programmable virtual data channels. The virtual data channels carry multiple traffic classes of packet-based messages. The virtual data channels and multiple traffic classes may be assigned one of multiple priorities. The virtual data channels may be arbitrated independently. The hybrid fabric is scalable and can support multiple topologies, including multiple stacked integrated circuit topologies.

Abstract: Coding techniques for a video image compression system involve improving an image quality of a sequence of two or more bi-directionally predicted intermediate frames, where each of the frames includes multiple pixels. One method involves determining a brightness value of at least one pixel of each bi-directionally predicted intermediate frame in the sequence as an equal average of brightness values of pixels in non-bidirectionally predicted frames bracketing the sequence of bi-directionally predicted intermediate frames. The brightness values of the pixels in at least one of the non-bidirectionally predicted frames is converted from a non-linear representation.

Abstract: An display driving circuit including a buffer write controller transmitting a different image frame to a first buffer or a second buffer, a buffer scan controller scanning an image frame stored in the first buffer or the second buffer on the basis of a predetermined cycle, a write signal detector controlling the buffer write controller such that a second image frame is transmitted to the second buffer after a first image frame is transmitted to the first buffer, and a scan buffer switching controller receiving an EOF (End of Frame) command indicating the completion of transmission of the first image frame to the first buffer and controlling the buffer scan controller such that the first image frame stored in the first buffer is scanned after the image frame previously stored in the second buffer is scanned.

Abstract: An image processor, a display device including the same, and a method for driving display panel using the same are disclosed. In one aspect, the display device includes an image shifter configured to shift a data signal by at least one pixel based at least in part on a shift start signal and output the shifted data signal and a shift direction signal. The display device also includes an image buffer configured to output current data and previous data based at least in part on the shifted data signal and the shift direction signal. The display device also includes an image mixer configured to mix the current data and the previous data over M frames starting at a start frame when the shift start signal is received and output image data, M being a natural number.

Abstract: A method of and device for removing a processor from a low power mode. The method includes and the device provides for performing multiple processor start-up tasks in parallel. Memory interface training between the processor and memory and restoration and initialization of the processor are performed in parallel with each other and with a serial bus controller entering serial bus training to facilitate communication between the processor and a system controller.

Abstract: A display device is disclosed, which may supply gate signals to allow pulse widths of gate signals supplied to adjacent gate lines to be overlapped with each other and at the same time minimize cost increase caused by increase of the number of line memories. The display device comprises a display panel, a gate driver and a timing controller. The display panel includes gate lines, data lines and pixels provided at crossing areas between the gate lines and the data lines. The gate driver supplies gate signals to the gate lines. The timing controller supplies a start signal and gate clock signals for controlling an operation timing of the gate driver to the gate driver. One frame period includes an active period for supplying the gate signals to the gate lines and a vertical blank period for not supplying the gate signals to the gate lines, and the start signal is supplied within the vertical blank period.

Abstract: A texture processing pipeline is configured to store decoded texture data within a cache unit in order to expedite the processing of texture requests. When a texture request is processed, the texture processing pipeline queries the cache unit to determine whether the requested data is resident in the cache. If the data is not resident in the cache unit, a cache miss occurs. The texture processing pipeline then reads encoded texture data from global memory, decodes that data, and writes different portions of the decoded memory into the cache unit at specific locations according to a caching map. If the data is, in fact, resident in the cache unit, a cache hit occurs, and the texture processing pipeline then reads decoded portions of the requested texture data from the cache unit and combines those portions according to the caching map.

Abstract: A method and system for performing general matrix-vector multiplication (GEMV) operations on a graphics processor unit (GPU) using Smart kernels. During operation, the system may generate a set of kernels that includes at least one of a variable-N GEMV kernel and a constant-N GEMV kernel. A constant-N GEMV kernel performs computations for matrix and vector combinations with a specific value of N (e.g., the number of columns in a matrix and the number of rows in a vector). Variable-N GEMV kernels may perform computations for all values of N. The system may also generate 1B1R kernels, constant-N variable-rows GEMV kernels, and variable-N variable-rows GEMV kernels. The system may generate constant-N variable-threads GEMV kernels, and variable-N variable-threads GEMV kernels. The system may also generate variable-threads-rows GEMV kernels for the set. This may include ConstN kernels (e.g., constant-N variable-threads-rows GEMV kernels), and VarN kernels (e.g., variable-N variable-threads-rows GEMV kernels).

Abstract: An image can be presented using render-tiles, which are movable rendering contexts in which multiple image-tiles can be drawn as a single image. To optimize performance, the render-tiles can be large enough to minimize the number of render-tiles necessary to present the image within the screen view of a client device, while remaining small enough to avoid memory or performance issues when panning or zooming the image. A set of active image-tiles and active render-tiles can be identified based on a specified view boundary that represents a portion of the image that is presented by a client device. The active render-tiles can be presented by the client device and the image-tiles can be drawn into the render-tiles to present the image. The render-tiles can be generated as needed and inactive render-tiles can be stored for later use or recycled.

Abstract: A system-on-chip (SoC) device includes: a display controller configured to receive a trigger signal, and to output image data based on the trigger signal; and a transceiver configured to receive a first interrupt. In a first mode, the display controller is configured to output the image data in synchronization with a pulse of the trigger signal. In a second mode, which is different from the first mode, the display controller is configured to output the image data in synchronization with a pulse included in the trigger signal only after receiving the first interrupt.

Abstract: To prioritize repopulation of in-memory compression units (IMCU), a database server compresses, into an IMCU, a plurality of data units from a database table. In response to changes to any of the plurality of data units within the database table, the database server performs the steps of: (a) invalidating corresponding data units in the IMCU; (b) incrementing an invalidity counter of the IMCU that reflects how many data units within the IMCU have been invalidated; (c) receiving a data request that targets one or more of the plurality of data units of the database table; (d) in response to receiving the data request, incrementing an access counter of the IMCU; and (e) determining a priority for repopulating the IMCU based, at least in part, on the invalidity counter and the access counter.

Abstract: Embodiments provide for a graphics processing apparatus comprising render logic to detect rendering operations that will result in framebuffer having the same data as the initial clear color value and morphing such rendering operations to optimizations that are typically done for initial clearing of the framebuffer.

Abstract: The array substrate includes a substrate and at least one display pixel arranged on the substrate. The display pixel includes a plurality of first pixels and a plurality of second pixels arranged along a row direction and a column direction. The period along the row direction or the column direction includes three display pixels. Wherein within at least one period along the row direction and the column direction, the display pixel of the first row includes one second pixel and two first pixels adjacent to the second pixel. The display pixel of the second row includes one first pixel and two second pixels adjacent to the first pixel. The display pixel of the third row includes one first pixel and two second pixels adjacent to the first pixel, and the first pixel of the third row is in different column from the first pixel of the second row.

Abstract: Embodiments of the present invention provide resource managing methods and systems. The method comprises: receiving a request to allocate resources sent from host code of an application program located on a first device; in accordance with the allocation request and a maintained mapping logic mapping available hardware resources of at least one graphics processing unit (GPU) of the first device to a unified virtual GPU resource, allocating required resources for a device code of the application program from the available hardware resources of at least one GPU of the first device; and forwarding information of the allocated resource back to the host code. The present invention can efficiently utilize GPU resources and reduce implementation costs.

Abstract: A data transfer device includes a shifter block that generates first and second input signals and first and second output signals, an input/output control block that selects the first input signal and the first output signal in correspondence to a mode signal and outputs an input control signal and an output control signal for controlling a data input/output operation, or selects the second input signal and the second output signal and outputs the input control signal and the output control signal, and a buffer block that latches first input data or second input data which have different data bit widths according to the input control signal, and outputs first output data or second output data which have different data bit widths according to the output control signal.

Abstract: Active gameplay of a video game on a computer gaming device is overseen by a platform-level in-game recording companion that executes separately from any of a plurality of different video games. During active gameplay of the video game, the active gameplay is continuously and automatically buffered to a temporary storage buffer. During active gameplay the computer gaming device receives a command to save a segment of the active gameplay for subsequent viewing. Without interrupting the active gameplay, the segment of the active gameplay is saved from the temporary storage buffer to a library of the platform-level in-game recording companion.

Abstract: An image forming apparatus that performs image processing using information stored in a semiconductor memory includes an obtaining unit configured to obtain from the semiconductor memory a block size used for data reading and writing, and a management unit configured to discretely arrange and manage, with respect to a specific region set in the semiconductor memory, use-based information to be updated along with execution of the image processing, included in the stored information, according to the obtained block size.

Abstract: Embodiments of the present invention are directed to improving the performance of anti-aliased image rendering. One embodiment is a method of rendering a pixel from an anti-aliased image. The method includes: storing a first set and a second set of samples from a plurality of anti-aliased samples of the pixel respectively in a first memory and a second memory; and rendering a determined number of said samples from one of only the first set or the first and second sets. Corresponding system and computer program product embodiments are also disclosed.

Abstract: A memory device includes a row selection unit for selecting word lines of a memory array, a column selection unit for selecting data lines of the memory array, a last address storing unit for storing a last row address and a last column address, and a selection address generating unit for providing a row selection address and a column selection address to select the word lines and the data lines. In the memory device, start row and column addresses are determined based on the first and last row addresses, the first and last column addresses, the row section address and the column selection address and forwardly or backwardly counted based on directions corresponding to image data injection directions in a display panel to which the memory device provides the image data.

Abstract: A first set of signal carriers of a plurality of signal carriers may be determined to be faulty. The first set of signal carriers may be for transmitting a first set of respective lane signals of a plurality of lane signals. A second set of signal carriers of the plurality of signal carriers may be identified as not faulty. The second set of signal carriers may be for transmitting a second set of lane signals of the plurality of lane signals. Based on the determining and identifying, one or more of the first set of lane signals may be routed from the first set of signal carriers through a first subset of the second set of signal carriers, the routing of the one or more of the first set of lane signals may cause a bandwidth capacity to increase to a highest available bandwidth.

Abstract: A display driving apparatus including a signal transmission interface, a timing control circuit and an image detection circuit is provided. The signal transmission interface is configured to receive video image data and output the video image data. The timing control circuit is configured to receive the video image data and drive a display panel based on the video image data. The image detection circuit determines whether the video image data is a static image and determines whether the display driving apparatus operates in a power-saving mode based on the determination result. Under the power-saving mode, the signal transmission interface masks a part of the video image data, so as not to output the masked video image data to the timing control circuit. Furthermore, a display driving method adapted for the foregoing display driving apparatus is also provided.

Abstract: A display (101) is controlled by a display drive signal (S2) generated based on an input signal (S1) encoding a safety-critical quantity. A checksum (S4) is computed based on the display drive signal and is used to verify the rendering process by which the display drive signal has been produced. In order for the checksum to depend on the safety-critical quantity only, the checksum is computed based on a filtered display drive signal (S3) in which pixels with a certain value have been excluded. In embodiments of the invention, safety-noncritical quantities are represented using colors that are due to be excluded. Similarly, a checksum for verifying a given quantity can be made independent of other quantities represented in adjacent screen areas by representing the latter using excluded colors. In other embodiments, pixel values corresponding to particular pixel positions may be excluded from contributing.

Abstract: An image display system is provided. The image display system includes a host, and a touch controller configured to generate touch event information corresponding to a touch signal and supply the touch event information to an accelerator, wherein the touch signal is output from a touch panel. The accelerator is configured to generate, based on the touch event information supplied from the touch controller, output image data corresponding to a touch event. The image display system further includes a display controller configured to supply the output image data generated by the accelerator to a display panel.

Abstract: Techniques are disclosed for rendering scene volumes having scene dependent memory requirements. A image plane used to view a three dimensional volume (3D) volume into smaller regions of pixels referred to as buckets. The number of pixels in each bucket may be determined based on an estimated number of samples needed to evaluate a pixel. Samples are computed for each pixels in a given bucket. Should the number of samples exceed the estimated maximum sample count, the bucket is subdivided into sub-buckets, each allocated the same amount of memory as was the original bucket. Dividing a bucket in half effectively doubles both the memory available for rendering the resulting sub-buckets and the maximum number of samples which can be collected for each pixel in the sub-bucket. The process of subdividing a bucket continues until all of the pixels in the original bucket are rendered.

Abstract: Methods and systems for implementing a secure migratable architecture are disclosed. One method includes, upon initiating execution of a process, allocating a portion of a memory for use by the process during execution, the process including a firmware environment representing a virtual computing system having a second computing architecture different from a first computing architecture of a computing system on which the process is executed. The method also includes executing the process hosted by the operating system, wherein the firmware environment manages the portion of the memory using one or more area descriptors to describe the portion of the memory, each of the one or more area descriptors defining to the firmware environment a base address at which a memory area is located, the base address translated to an address in the memory managed by the operating system, the memory area being within the portion of memory allocated for use by the process.

Abstract: Methods and systems for implementing a secure migratable architecture having improved performance features over existing virtualization systems are disclosed. One method includes allocating a portion of a memory for use by a process, the process including a firmware environment representing a virtual computing system having a second computing architecture different from a first computing architecture of a computing system on which the process is executed. The method includes associating area descriptors with each of a plurality of memory areas within the portion of the memory used by the process, and receiving a request within the firmware environment to store data within a first memory area of the plurality of memory areas, the first memory area defined by a first area descriptor of the area descriptors, the request being associated with a plurality of memory addresses within the first memory area.

Abstract: A video transmission system is disclosed. The video transmission system comprises a multi-drop bus, a first source driving chip, a second source driving chip and a timing controller. The first source driving chip comprises a first source driving circuit and a first terminal circuit. The first terminal circuit is coupled to the multi-drop bus and the first source driving circuit for providing a first terminal resistor. The second source driving chip comprises a second source driving circuit and a second terminal circuit. The second terminal circuit is coupled to the multi-drop bus and the second source driving circuit for providing a second terminal resistor. The timing controller is coupled to the first source driving chip and the second source driving chip via the multi-drop bus.

Abstract: A method allows changing an image raster direction from an application raster direction to a screen raster direction, in-flight while pixel values of an image are transferred successively from an application output memory to a display unit. A single buffer memory array is implemented between the application output memory and the display unit. Two writing orders for cells of the buffer memory array are used in turn, each being combined with a different reading order for the cells. The method can be hardware-implemented, and is adapted for burst-handling of the pixel values.

Abstract: A method and system for shared virtual memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a system memory. A CPU virtual address space may be created, and the surface may be mapped to the CPU virtual address space within a CPU page table. The method also includes creating a GPU virtual address space equivalent to the CPU virtual address space, mapping the surface to the GPU virtual address space within a GPU page table, and pinning the surface.

Abstract: An image processing device includes: a memory section that has memory areas equivalent to data of k rows of an image; a correction section that corrects data of a given pixel belonging to a row designated by a first counter, out of data stored in the memory section, using data of a pixel in a position designated by an offset vector corresponding to the given pixel; an output section that outputs data corrected by the correction section; and a write section that writes data, out of the image, of a row designated by the second counter into a corresponding memory area of the memory section.

Abstract: A graphics processing system has a rendering space which comprises one or more tiles. The system comprises a processing module configured to perform hidden surface removal for primitives of a tile to determine primitive identifiers identifying the primitives which are visible at each of a plurality of sample positions in the tile. A set of two or more tag buffers store the primitive identifiers determined for each of the sample positions in a tile, thereby representing overlapping layers of primitives. A tag control module controls: (i) selection of a tag buffer for the storage of each of the primitive identifiers according to the layering of the primitive identifiers stored in the tag buffers, and (ii) flushing of primitive identifiers from the tag buffers. A texturing engine applies texturing to the primitives identified by the flushed primitive identifiers.

Abstract: A cut-to-measure display device comprising a plurality of pixel groups (300) and a main controller. Each pixel group comprises one sub-controller (301) and a plurality of individually controllable pixels (305), out of which all are connected to the sub-controller of the pixel group and at least one is further connected (304) to a sub-controller of an adjacent pixel group. The main controller is connected to the sub-controllers and configured to selectively control the sub-controllers in order that the pixels display an image corresponding to predetermined image data. Cutting a display device with these features into an arbitrary geometric shape may disconnect some pixels from their respective sub-controllers. However, at least one pixel in each pixel group is connected to a further sub-controller which is operable to take the place of a sub-controller from which it has been cut off, so there is a low risk of completely disconnecting pixels.

Abstract: A data storage device includes a nonvolatile memory device including a first plane and a second plane; and a controller configured to provide a read command for reading simultaneously the first plane and the second plane, a first address for accessing the first plane and a second address for accessing the second plane, to the nonvolatile memory device, wherein the nonvolatile memory device reads all page types that should be read from the first plane and the second plane, from each of the first plane and the second plane, according to the read command, the first address and the second address.

Abstract: A quarter product code codeword includes various R code symbols and C code symbols each including a plurality of symbols. Each symbol is loaded into a diagonal anti-diagonal structure in two unique locations. To provide for fast loading, the symbols may be shifted by one or more shift registers associated with the diagonal or anti-diagonal structure. The two locations at which each symbol is positioned are included within different diagonals or anti-diagonals making it possible to load or unload either symbol or multiple symbols in a single clock cycle. Further, by partitioning the diagonal anti-diagonal structure, multiple respective symbols or plurality of symbols may be loaded or unloaded in a single clock cycle.

Abstract: One display frame period is divided into one or a plurality of display driving periods and non-display driving periods, and immediately before transition from the non-display driving period to the display driving period, a dummy driving period is inserted. During the dummy driving period, using dummy data changed from display data at the time of driving stop of a signal electrode during the non-display driving period, driving of the signal electrode starts. Thereafter, a display line is selected, and, using the display data corresponding to each display line selected, the signal electrode is driven.

Abstract: To provide a semiconductor device having large memory capacity and high reliability of data or a small-size semiconductor device having a small circuit area. A memory cell includes first and second data retention portions capable of storing multilevel data. A data voltage is written to the first data retention portion from a first wiring through a transistor and a second wiring, and a data voltage is written to the second data retention portion from the second wiring through a transistor and the first wiring. With the configuration, data voltages reduced by the threshold voltages of the transistors can be retained in the first and second data retention portions. The written data voltages where the threshold voltages of the transistors are canceled can be read by precharging and then discharging the first wiring.

Abstract: A self refresh method with dithering has at least the following steps: generating a plurality of original frames; performing a dithering process upon the plurality of original frames to generate a plurality of dithering frames to a timing controller; checking if the plurality of original frames is unaltered; and when it is detected that the plurality of original frames is unaltered, requesting the timing controller to enter a self refresh mode, and stopping transmission of dithering frames after transmitting a specific frame and dithering information associated with the specific frame to the timing controller for further dithering processing.

Abstract: A method for running application software for a mobile device by virtualizing a mobile device operating system (OS); running a virtual instance of the mobile device OS with the application software on a server on the cloud; and rendering on the server and sending a display image for the mobile device screen to be displayed on the mobile device.

Abstract: A system-on-chip is provided which includes a data producer; a FIFO buffer which stores data transferred from the data producer at a memory area corresponding to a write pointer; a first consumer which pops data of a memory area corresponding to a first read pointer of the FIFO buffer out; and a second consumer which pops data of a memory area corresponding to a second read pointer of the FIFO buffer out. The FIFO buffer requests a pop-out operation at the second consumer according to the difference between the write pointer and the first read pointer or overwrites data provided from the data producer at a memory area corresponding to the second read pointer.

Abstract: Disclosed is a method of modifying a graphics command. The method receives a graphics command comprising a drawing operation and a pattern (ROP3) of the region and obtains spatial frequencies of the pattern. The method determines if the obtained spatial frequencies of the pattern in the graphics command define a transparency attribute of the region to be rendered and replaces at least the pattern in the graphics command with a transparency coefficient based on the obtained spatial frequencies.

Abstract: Systems and methods for determining priorities of pixel fetch requests of separate requestors in a display control unit. The distance between the oldest pixel in an output buffer and the output equivalent coordinate of the oldest outstanding source pixel read request for each requestor in the display control unit is calculated. Then, a priority is assigned to each requestor based on this calculated distance. If a given requestor lags behind the other requestors based on a comparison of the distance between the oldest pixel and the output equivalent coordinate of the oldest outstanding source pixel read, then source pixel fetch requests for this given requestor are given a higher priority than source pixel fetch requests for the other requestors.

Abstract: An electronic shelf label tag includes a communications unit configured to wirelessly communicate with an electronic shelf label repeater; a control unit configured to control operations including receiving display data including display information mapped to a display information index from the communications unit prior to a preset time, storing the display data, receiving change command data including the display information index from the communications unit after the preset time, retrieving the display information mapped to the display information index included in the change command data from the stored display data, and displaying the retrieved display information on a screen; a memory unit configured to store the display data including the display information mapped to the display information index under the control of the control unit; and a display unit configured to display the retrieved display information on the screen under the control of the control unit.

Abstract: Apparatuses, systems, and methods may sample a texture, manage a page fault, and/or switch a context associated with the page fault. A three-dimensional (3D) graphics pipeline may provide texture sample location data corresponding to a texture, wherein sampling of the texture is to be executed external to the 3D graphics pipeline. A compute pipeline may execute sampling of the texture utilizing the texture sample location data and provide texture sample result data corresponding to the texture, wherein the 3D graphics pipeline may composite a frame utilizing the texture sample result data. The compute pipeline may manage a page fault, wherein the page fault and/or management of the page fault may be hidden from a graphics application. In addition, the compute pipeline may switch a compute context associated with the page fault to allow a graphics task not associated with the page fault to be executed and/or to prevent a stall.

Abstract: Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.

Abstract: Systems and methods for initiating attract sequences on gaming machines based on a determined presence of a player through a camera are described. The gaming machine includes a cabinet. The gaming machine further includes a display coupled to the cabinet. The gaming machine includes a user input coupled to the cabinet. The gaming machine includes a video camera coupled to the cabinet, the video camera configured to output video data, wherein the video camera is positioned to capture video data of players walking by the gaming machine. The gaming machine includes a master gaming controller. The master gaming controller is configured to receive the video data from the video camera, determine the presence of a player in the vicinity of the gaming machine, and initiate an attract feature based on the determined presence of the player.

Abstract: An apparatus for processing graphics data may include a plurality of processing pipelines, each pipeline configured to receive and process pixel data. A functional unit may combine the outputs of each processing pipeline. A buffer included in a given processing pipeline may be configured to store data from the functional unit in response to a determination that the given processing pipeline is inactive. The buffer may then send the stored data to a memory.

Abstract: A portable data terminal including a multi-core processor having at least a first core and a second core, at least one illumination assembly and at least one imaging assembly and data storage means configured to store a plurality of program instructions, the program instructions including at least one one-dimensional decoder and at least one two-dimensional decoder.

Abstract: A docking device including a casing and an extension supporting mechanism is disclosed. The extension supporting mechanism includes a sliding member, a transmission member, a supporting member and a clamping member. The sliding member is slidably disposed on the casing. The transmission member, the supporting member and the clamping member are pivoted to the casing, respectively. The transmission member is coupled to the sliding member. The supporting member is coupled to the transmission member. The clamping member further abuts against the sliding member and is for sliding the sliding member as rotating, such that the sliding member drives the transmission to rotate. Accordingly, the transmission member is driven to activate the supporting member to stretch an extension portion of the supporting member out of the casing.