Abstract: A system, method and apparatus are disclosed, in which a processing unit is configured to perform secondary processing on graphics pipeline data outside the graphics pipeline, with the output from the secondary processing being integrated into the graphics pipeline so that it is made available to the graphics pipeline. A determination is made whether to use secondary processing, and in a case that secondary processing is to be used, a command stream, which can comprise one or more commands, is provided to the secondary processing unit, so that the unit can locate and operate on buffered graphics pipeline data. Secondary processing is managed and monitored so as to synchronize data access by the secondary processing unit with the graphics pipeline processing modules.

Abstract: A non-buffered video line memory eliminates the need for double buffering video data during processing. While most double buffering systems double the amount of memory necessary to store video data, a non-buffered approach reduces the hardware memory costs substantially. A set of write and read pointers coupled with write and read incrementors allows data to be stored in raster order and removed in block order from a non-buffered memory device. The incrementors, in conjunction with a set of write and read pointers generate a base address for data to be written to and read from the non-buffered memory at substantially the same time. Encoding systems benefit substantially by being able to read and write information into a common memory rather than continuously switching between two different memories, by reducing complexity and cost.

Abstract: An apparatus, system, and method of outputting an image, and image output control program stored in a recording medium are described. The image output apparatus that displays data through a display obtains first element identification information for identifying a first element included in a specified folder, determines whether the first element is a folder based on the first element identification information, obtains second element identification information for identifying a second element included in the first element when the first element is determined to be the folder, analyzes whether the second element is a data file having a data format compatible with the display to generate an analysis result, determines a display format of the first element that is determined to be the folder based on the analysis result of the second element, and causes the display to display an image that reflects the first element in the determined display format.

Abstract: In one embodiment there is provided, a display driver system, comprising, at least one display driver; a magnetic random access memory (MRAM) macro; and a display driver interface coupling the MRAM macro and the at least one display driver.

Abstract: A system, method, and computer program product for recovering from a memory underflow condition associated with generating video signals are disclosed. The method includes the steps of determining that a first counter is greater than a second counter, incrementing an address corresponding to a memory fetch request by an offset, and issuing the memory fetch request to a memory. The first counter represents a number of pixels that have been read by a display pipeline for a current frame and the second counter represents a number of pixels requested from a memory for the current frame.

Abstract: An image cache memory performs caching of image data, the image cache memory includes a cache buffer, a cache tag unit, a comparator, and a controller. The cache buffer stores cache data for each rectangular block including a plurality of pixels arranged in rectangle, and the cache tag unit stores tags each corresponding to a rectangular-block group including a plurality of rectangular blocks. The comparator makes comparison by using the tags stored in the cache tag unit, and the controller performs the caching by controlling the cache buffer, the cache tag unit, and the comparator.

Abstract: There is provided a display controller for reading frame data from a frame buffer, and generating a screen output image to be displayed on a display, wherein the display controller is provided with a path for extracting the screen output image as a screen image for transfer to be transferred to another apparatus, and writing the screen image for transfer to a dedicated memory provided separately from the frame buffer.

Abstract: According to one embodiment, a graphics/video processor includes a memory controller. The memory controller includes a first arbiter that receives memory client requests to access a memory device, and a first memory buffer coupled to the first arbiter. The first arbiter stores client requests that are selected by the first arbiter. The memory controller also includes a second arbiter coupled to the first memory buffer and a second memory buffer coupled to the second arbiter. The second arbiter receives requests from the memory client requests stored in the first memory buffer. The second memory buffer stores the client requests selected by the second arbiter. Further, the memory controller includes a third arbiter coupled to the second memory buffer. The third arbiter provides access of the memory device to the client requests stored in the second memory buffer.

Abstract: An image processing device improves processing performance at low cost. The image processing device is provided with a memory controller that divides up and assigns banks accessed by a video inputter, a drawer, and a video outputter to multiple frame memories. The image processing device arbitrates access requests from master units, such as the video inputter, the drawer, and the video outputter, and controls data transmission so that the multiple master units can access both the frame memories in parallel.

Abstract: A remote control, upon determining that a power-saving flag is on, or in other words, upon determining that the remote control is conducting power-saving operating behavior, decides on a monochrome image stored in a reduced image memory as image information to be read by a renderer. The monochrome image has ? the amount of information compared to a color image stored in a normal image memory. Consequently, in the case of power-saving operating behavior by the remote control, the renderer is able to read a monochrome image stored in the reduced image memory with less power compared to the case of reading a color image stored in the normal image memory. Consequently, power consumed in the remote control may be restricted in the case of power-saving operating behavior by the remote control.

Abstract: A data access method is provided. The data access method is applied for a data device access device to access data from N layers to display an image, where N is a positive integer. Each of the N layers includes a horizontal start point, a horizontal end point, a vertical start point and a vertical end point. The data access method includes: dividing the image into a plurality of regions according to the horizontal start points, the horizontal end points, the vertical start points and the vertical end points, wherein the regions respectively correspond to the N layers; and accessing data from the respective layers corresponding to the regions when displaying the image.

Abstract: A processing system is disclosed. The processing system comprises a first integrated circuit. The first integrated circuit includes a processor core, a display interface and memory controller coupled to a first bus interface. The display interface is adapted to display graphical information generated by a graphics engine. A graphics engine is not on the first integrated circuit. The processing system includes a second bus interface for allowing communication with the first integrated circuit via the first bus interface. The second bus interface is adapted to allow for communication to a graphics engine.

Abstract: An image processing apparatus includes a memory control circuit that stores pixel data in a frame memory, an image processing circuit that processes the pixel data stored in the frame memory, and an output circuit that outputs processed pixel data. The memory control circuit divides the pixel data into upper bit portions and lower bit portions, and a lower bit processing circuit stores the lower bit portions in the frame memory by one of (i) dividing lower bit portion of each of the pixel data into n unit portions and storing corresponding one of n unit portions in the frame memory during each of n successive frame periods, and (ii) dividing pixels constituting each of the frames into n groups and storing the lower bit portions of the pixel data of pixels in corresponding one of n groups in the frame memory during each of n successive frame periods.

Abstract: The portable terminal includes a display unit configured to display a screen; a first buffer and a second buffer configured to sequentially store display data for the displayed screen; a first determination unit configured to determine whether to perform single-buffer control or double-buffer control based on update data for the displayed screen; and a setting unit configured to set, if single-buffer control is appropriate, a display control method of the display unit to a display control method using the first buffer and to set, if double-buffer control is appropriate, a display control method of the display unit to a display control method using the first buffer and the second buffer.

Abstract: Systems, apparatus, articles, and methods are described including operations to set an interrupt range in an interrupt register associated with a display controller. A determination may be made regarding whether a front buffer portion of a frame buffer is within the interrupt range. An interrupt may be communicated based at least in part on the determination that the front buffer portion of the frame buffer is within the interrupt range.

Abstract: Embodiments are described for handling focus when a gesture is input in a multi-screen device. In embodiments, a first image displayed on a first touch sensitive display of a first screen may be currently in focus. In embodiments, the gesture is a tap on a second touch sensitive display of the device. In response to the gesture, an application is launched, which displays a second image on a second display of a second screen. Focus is then changed from the first image on the first touch sensitive display to the second image on the second touch sensitive display.

Abstract: In accordance with some embodiments, a mask or table may be maintained to record information about whether or not each pixel within a tile is cleared. As used herein, a “cleared” tile is one that is not covered by any other depicted objects. The clear mask may store a bit per pixel or sample to indicate whether the pixel or sample contains a color value or whether it is cleared. As a result, the compression ratio may be increased for partially covered tiles in some embodiments.

Abstract: A display device is provided. The device includes memories, a display unit, and a data collecting memory. The memories store a plurality of kinds of image data generated based on information acquired from different kinds of sensors, respectively. The display unit displays the image data that is selected by a user among the plurality of kinds of image data. The data collecting memory stores, in response to a predetermined report instruction, at least data of an image displayed on the display unit at the timing of the report instruction and, among the image data stored in the memories at the timing of the report instruction, the image data that is not displayed on the display unit.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

Abstract: An object is to provide an image processing circuit adaptable to displays having a variety of pixel numbers. The image processing circuit includes a data adjustment circuit, a first line memory and a second line memory capable of storing K pieces of data, an output timing control circuit, and an arithmetic circuit. To the data adjustment circuit, (X×Y) pieces of pixel data are input. Y pieces of pixel data are transmitted to the first line memory. When Y is less than K, (K?Y) pieces of dummy data are added to fill the first line memory. Then, the K pieces of data are output from the first line memory to the second line memory and a new set of K data is input to the first line memory. The arithmetic circuit stores the data input from the line memories and performs filtering.

Abstract: In contrast to a conventional computing system in which the graphics processor (graphics processing unit or GPU) is treated as a slave to one or several CPUs, systems and methods are provided that allow the GPU to be treated as a central processing unit (CPU) from the perspective of the operating system. The GPU can access a memory space shared by other CPUs in the computing system. Caches utilized by the GPU may be coherent with caches utilized by other CPUs in the computing system. The GPU may share execution of general-purpose computations with other CPUs in the computing system.

Abstract: Disclosed are methods and systems for multimedia scripting, including evaluating a script at runtime and invoking a process for editing multimedia in dependence upon the script. Multimedia may include a still image and video images. Multimedia scripting may also include accepting text entered into a text-input graphical user interface as a script for runtime evaluation, accepting from a non-text-based graphical user interface a designation of scripts for runtime evaluation, and effecting a disposition of the edited multimedia in dependence upon a script, such as storing the multimedia as a file, presenting the multimedia, or encoding the edited multimedia as an email attachment.

Abstract: A memory access controller for managing data flow between a memory unit and a processing unit is described. The memory access controller comprises an addressing unit and an unpacking unit. The addressing unit may receive an address from said processing unit and select a data location within said memory unit in dependence on that address. The unpacking unit may read a first word from the selected data location, unpack the first word into a second word by applying a data conversion scheme which depends on the received address, and provide the second word to the processing unit. The data conversion scheme may comprise, for at least one possible address, a pixel format conversion. A data processing system and a method are also proposed.

Abstract: A method and apparatus for controlling writing of data to a graphic memory is provided. In the method and apparatus, a plurality of consecutively input data pieces are controlled to be not consecutively written to the same memory area in terms of time or space.

Abstract: In an embodiment, a display pipe is configured to composite one or more frames of images and/or video sequences to generate output frames for display. Additionally, the display pipe may be configured to compress an output frame and write the compressed frame to memory responsive to detecting static content in the output frames is detected. The display pipe may also be configured to read the compressed frame from memory for display instead of reading the frames for compositing and display. In some embodiments, the display pipe may include an idle screen detect circuit configured to monitor the operation of the display pipe and/or the output frames to detect the static content.

Abstract: In an embodiment, a display pipe is configured to composite one or more frames of images and/or video sequences to generate output frames for display. Additionally, the display pipe may be configured to compress an output frame and write the compressed frame to memory responsive to detecting static content in the output frames is detected. The display pipe may also be configured to read the compressed frame from memory for display instead of reading the frames for compositing and display. In some embodiments, the display pipe may include an idle screen detect circuit configured to monitor the operation of the display pipe and/or the output frames to detect the static content.

Abstract: Aspects of this disclosure may describe techniques to display a static image with reduced power consumption. In some examples, a graphics processing unit (GPU) may retrieve the static image from a system memory, scale the static image to a reduced spatial resolution version of the static image, and store the reduced spatial resolution version of the static image in local memory. A display processor may retrieve the reduced spatial resolution version of the static image from local memory. The display processor may rescale the reduced spatial resolution version of the static image, and display the rescaled image on a display for presentation.

Abstract: A method and apparatus is provided for providing local screen data of a source device, such as a personal computer, to a sink device, such as a television, game console, or home theatre system, at a rate determined by the sink device. In one example, the method and apparatus responds to requests from the sink device to provide local screen data by serving the local screen data to the sink device from a circular buffer. The local screen data is written to the circular buffer in FIFO order based on the requests from the sink device, and read from the circular buffer based on the requests.

Abstract: Before initializing a memory of an information handling system, a method includes loading an image of a video option ROM code for a graphics interface device to a cache associated with a processor of the information handling system, and executing the video option ROM code to initialize the graphics interface device. The method also includes executing a memory reference code to initialize the memory, and while executing the memory reference code, providing status information from the graphics interface device.

Abstract: This disclosure provides systems, methods and apparatus for modulating light to form an image on a display, as well as methods manufacturing such apparatus. The display apparatus includes dual-level shutter assemblies. Each dual-level shutter assembly includes front and rear light obstructing levels positioned adjacent to respective front and rear light blocking layers. The front and rear light blocking layers define apertures providing optical paths from a backlight to the front of the display. The dual-level shutters selectively obstruct these optical paths to generate an image.

Abstract: An image display device includes a memory component, a color specification component and a display component. The memory component stores frame data that forms a display image, a color table that stores color data for each selection condition with the color data being indicative of a plurality of colors specified to the frame data, and reference data that associates the selection condition with the color data of the color table. The color specification component specifies the color data to the frame data based on the reference data according to the selection condition. The display component generates the display image based on the frame data and the color data.

Abstract: A protected graphics module can send its output to a display engine securely. Secure communications with the display can provide a level of confidentiality of content generated by protected graphics modules against software and hardware attacks.

Abstract: A method and apparatus are provided for compressing vertex parameter data in a 3D computer graphic system, where the vertex parameter data is a data block relating to a plurality of vertices used for rendering an image. The data relating to each vertex includes multiple byte data relating to at least one parameter. The parameters include X, Y and Z coordinates and further coordinates for texturing and shading. Decompression is also provided for decompressing vertex parameter data thus compressed. These are able to access randomly the compressed data, rather than having to read a stream of data.

Abstract: An integrated circuit device includes a first pad group connected to a first memory pad group arranged along a first chip side of a chip of an image memory stacked on the integrated circuit device, a second pad group connected to a second memory pad group arranged along a third chip side, a control section which controls display of an electro-optical device, and a third pad group from which a data signal and a control signal for display control. The first pad group is arranged along a first side of the integrated circuit device, wherein the second pad group is arranged along a third side facing the first side, and wherein the third pad group is arranged along a second side which intersects with the first side and the third side.

Abstract: In a mobile device with a processing unit, main memory, display memory and display, a context module identifies a user-context, a determiner module determines correspondence or non-correspondence of data images in the main memory to the user-context, a first selector module selects corresponding data images for access by the display memory in case of correspondence, a second selector module select data items in case of non-correspondence, a transformation module transforms selected data items to corresponding data images and stores them in the main memory, and an access module lets the display memory access the selected data images.

Abstract: Graphics cards normally control the image display of data processing systems.

Abstract: In an embodiment, a system includes hardware optimized for communication to a network display. The hardware may include a display pipe unit that is configured to composite one or more static images and one or more frames from video sequences to form frames for display by a network display. The display pipe unit may include a writeback unit configured to write the composite frames back to memory, from which the frames can be optionally encoded using video encoder hardware and packetized for transmission over a network to a network display. In an embodiment, the display pipe unit may be configured to issue interrupts to the video encoder during generation of a frame, to overlap encoding and frame generation.

Abstract: Techniques are described that can used to synchronize the start of frames from multiple sources so that when a display is to output a frame to a next source, boundaries of current and next source are aligned. Techniques are useful to avoid visual distortions when changing from a first video source to a second video source.

Abstract: In an embodiment, a display control unit is configured to transmit read operations to the memory in the system to read image data for processing, and may employ QoS levels with the read operations to ensure that enough data is provided to satisfy the real time display requirements. To determine which QoS level to use for a given read request, the display control unit may be configured to compare an amount of image data in the display control unit (e.g. in various input and/or output buffers in the display control unit) to one or more thresholds. The display control unit may also be configured to dynamically update the thresholds based on a memory stress level in the memory controller.

Abstract: A data processing device according to embodiments comprises a data converting unit, a selecting unit, a managing unit, a updating unit, and a controller. The data converting unit is configured to convert update-data for updating at least a part of an electronic paper into processed update-data to be displayed. The selecting unit is configured to select an update-control-information identifier to be used for updating the electronic paper with the processed update-data. The managing unit is configured to store the processed update-data and a selected update-control-information identifier on a first memory. The updating unit is configured to instruct a drawing step of the electronic paper using the processed update-data and the update-control-information identifier stored on the first memory.

Abstract: A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit.

Abstract: Techniques are disclosed relating to power management within an integrated circuit. In one embodiment, a display buffer receives image data through a data transfer interconnect. A data transfer interconnect is powered down based on the received image data being greater than a threshold amount of data. The display buffer transmits at least a portion of the image data to one or more outputs, and in response to the transmitting, the data transfer interconnect is powered up. In some embodiments, the display buffer includes a plurality of line buffers, each configured to store a respective image source line. In such an embodiment, a display pipe configured to render images to be displayed includes the display buffer, and the powering down is performed in response to the received image data including two or more image source lines.

Abstract: Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a first memory, a memory controller, and a display controller coupled to a display module. The memory controller is selectively coupled to the first memory and to a second memory that has higher power consumption than the first memory. The second memory includes a frame buffer storing pixel data of images to be displayed on the display module. When the integrated circuit enters a power saving mode, the memory controller, while coupled to the first memory and the second memory, pre-fetches pixel data of an image from the second memory into the first memory at a first data rate.

Abstract: A signal controlling method for a display device for signal processing between an external system and a display panel that displays an image by receiving a signal from the external system. The method includes receiving N clock signals and N data signals synchronized with the N clock signals from the external system through N channels, N being a natural number no less than 2; writing the received N data signals in N storage units in order of reception time of the N data signals; extracting one clock signal from the N clock signals; and outputting the N data signals written in the N storage units simultaneously in synchronization with the extracted clock signal.

Abstract: A graphics processing unit 2 includes a texture pipeline 6 which performs filter operations upon texture values. If the texture values are integer texture values, then they may be processed by the texture pipeline in a variable order corresponding to the order in which they are retrieved from a memory 4. If the texture values are floating point texture values, then they are processed in a fixed order in order to ensure result invariants as the filter operation is non-associative for floating point values. The filter operation is not commenced until all of the floating point texture values have been retrieved from the memory 4 and other available for processing.

Abstract: A display drive device includes a correction data memory circuit, a data reading control circuit, and an image data correction circuit. The correction data memory circuit stores a plurality of pieces of correction data according to characteristics of pixels in association with positions where the pixels are arranged in a display panel. The data reading control circuit sets a reading order of the plurality of pieces of correction data to an order corresponding to a display form and reads the correction data in the set reading order. The image data correction circuit associates the image data with each of the plurality of pieces of correction data and generates corrected image data obtained by correcting the image data using the corresponding correction data.

Abstract: An image display device of the present invention comprises a first determination section for monitoring information respectively appended to a plurality of images, and detecting information that has been appended to the most images among the plurality of images as first information, a second determination section for detecting information other than the first information, among the information that has been respectively appended to the plurality of images, as auxiliary information, and a third determination section for detecting an image to which the first information has been appended, and which is an image having the auxiliary information, as a priority image.

Abstract: A method and apparatus is provided in which a digital image is transmitted to a presentation projector resource over a wireless transmission medium using a reduced amount of bandwidth by transmitting a subset of the digital image data. The subset of image data may be a delta subset that represents those areas of the image that have changed since the previous transmission. The subset image data may also be a scalable vector graphics representation of the subset of the digital image. A projector discovery logic selects a suitable projector resource based on the order or signal strength of the discovery replies. A wireless image transmission session is established with the selected projector resource during which the projector is unavailable to other devices. The subset image data may be compressed and transmission coordinated with the projector resource so that the data is sent only when it is ready to be received.

Abstract: Circuit and methods provide for adjustable power consumption using a plurality of memory controllers. In one example, a first memory controller has a first power consumption level. A second memory controller has a second power consumption level that differs from the first power consumption level. Memory controller bypass logic is connected to the first and second memory controllers and selects for a memory client at least one of the first and second memory controllers in response to a change in a power conservation condition.

Abstract: Systems and methods of operating a memory controller may provide for receiving a write request from a motion compensation module, wherein the write request includes video data. A compression of the video data may be conducted to obtain compressed data, wherein the compression of the video data is transparent to the motion compensation module. In addition, the compressed data can be stored to one or more memory chips. Moreover, a read request may be received, wherein stored data is retrieved from at least one of the one or more memory chips in response to the request. Additionally, a decompression of the stored data may be conducted to obtain decompressed data.