Abstract: A timing controller, a display apparatus, and an operation method thereof are provided. The display apparatus includes a display panel and a timing controller. The timing controller includes a refresh mark controller and a pixel controller. The refresh mark controller includes a refresh mark table, and a plurality of refresh marks in the refresh mark table correspond to a plurality of sub-regions of a display region in the display panel. The refresh mark controller determines whether the sub-regions need to be refreshed according to an image signal and responds to a specific sub-region required to be refreshed to adjust a specific refresh mark according to a mapping ratio. The pixel controller sequentially looks up whether the refresh marks in the refresh mark table are adjusted, obtains the sub-regions corresponding to the adjusted refresh marks according to the mapping ratio, and performs a pixel refresh operation to the sub-regions.

Abstract: A display apparatus has an image display unit having a plurality of arrayed pixel circuits, and an image signal compensation circuit compensating an image signal and outputs the compensated signal to the image display unit. Each of the pixel circuits has a compensating capacitor which compensates the threshold voltage of the driving transistor. The image signal compensation circuit has a compensation memory storing a compensation data for compensating the current variation of the driving transistors, a first comparison circuit which compares the image signal and first threshold value, and an arithmetic circuit compensating the image signal. When the image signal has a luminance larger than the threshold value, the compensation is performed.

Abstract: A method of super-resolution image processing. The method includes inputting first image data representative of a first version of at least part of an image with a first resolution to a machine learning system. The first image data includes pixel intensity data representative of an intensity value of at least one color channel of a pixel of the first version of the at least part of the image, and feature data representative of a value of at least one non-intensity feature associated with the pixel. The first image data is processed using the machine learning system to generate second image data representative of a second version of the at least part of the image with a second resolution greater than the first resolution.

Abstract: A memory controller circuit coupled to multiple memory circuits may receive requests to access particular locations within the multiple memory circuits. A request may be assigned a particular quality-of-service level. During operation, the memory controller circuit may reallocate the quality-of-service level of a particular request to a new quality-of-service level based on accumulated bandwidth credits associated with the new quality-of-service level.

Abstract: A method of sharing content rendered on a device, including executing an application which generates audiovisual content, retrieving the application's audiovisual content from a graphics memory, and transmitting the retrieved content to a destination device via a network.

Abstract: Various exemplary embodiments of the present disclosure relate to an apparatus and method for outputting content in an electronic device. In this case, the electronic device includes a display module, a power module configured to interrupt power supply to at least one element of the electronic device based on a control signal, and a processor. The processor may be configured to transmit to the power module the control signal for interrupting the power supply to the processor if a designated condition is satisfied, and transmit content information to the display module so that the display module displays the content information when the power supply to the processor is interrupted.

Abstract: Methods, systems, and apparatus, including an apparatus for accessing data. In some implementations, an apparatus includes address offset value elements that are each configured to store an address offset value. For each address offset value element, the apparatus can include address computation elements that each store a value used to determine the address offset value. One or more processors are configured to receive a program for performing computations using tensor elements of a tensor. The processor(s) can identify, in the program, a prologue or epilogue loop having a corresponding data array for storing values of the prologue or epilogue loop and populate, for a first address offset value element that corresponds to the prologue or epilogue loop, the address computation elements for the first address offset value element with respective values based at least on a number of iterations of the prologue or epilogue loop.

Abstract: Processing of commands at a graphics processor are controlled by receiving input data and generating a command for processing at the graphics processor from the input data, wherein the command will cause the graphics processor to write out at least one buffer of data to an external memory, and submitting the command to a queue for later processing at the graphics processor. Subsequent to submitting the command, but before the write to external memory has been completed, further input data is received and it is determined that the buffer of data does not need to be written to external memory. The graphics processor is then signalled to prevent at least a portion of the write to external memory from being performed for the command.

Abstract: Systems, apparatuses, and methods for implementing a timestamp based display update mechanism. A display control unit includes a timestamp queue for storing timestamps, wherein each timestamp indicates when a corresponding frame configuration set should be fetched from memory. At pre-defined intervals, the display control unit may compare the timestamp of the topmost entry of the timestamp queue to a global timer value. If the timestamp is earlier than the global timer value, the display control unit may pop the timestamp entry and fetch the frame next configuration set from memory. The display control unit may then apply the updates of the frame configuration set to its pixel processing elements. After applying the updates, the display control unit may fetch and process the source pixel data and then drive the pixels of the next frame to the display.

Abstract: A lossless compression method and system applied to hardware video decoding are provided. The method sequentially includes a video decoding step, a compression step, a storage step and a decompression step, wherein in the compression step, lossless compression is performed by taking a 16×4 Y luma block and a corresponding 8×2 U chroma block and V chroma block as a compression unit; in the storage step, compact compression and storage is performed on a complete frame of image by taking four pixel lines as a unit, and a starting address of every four pixel lines is fixed; and the video decoding step includes a reference frame reading step, and a two-level Cache structure is adopted in the reference frame reading step. The system is a system applying the method.

Abstract: A graphics processing system has a rendering space which comprises one or more tiles. The system comprises a processing module configured to perform hidden surface removal for primitives of a tile to determine primitive identifiers identifying the primitives which are visible at each of a plurality of sample positions in the tile. A set of two or more tag buffers store the primitive identifiers determined for each of the sample positions in a tile, thereby representing overlapping layers of primitives. A tag control module controls: (i) selection of a tag buffer for the storage of each of the primitive identifiers according to the layering of the primitive identifiers stored in the tag buffers, and (ii) flushing of primitive identifiers from the tag buffers. A texturing engine applies texturing to the primitives identified by the flushed primitive identifiers.

Abstract: An apparatus includes an interface and a circuit. The interface may be connectable to (i) a plurality of counters and (ii) multiple pipelines. The circuit may be configured to (i) increment two or more given counters of the counters associated with a plurality of first data units in response to the first data units being available in a buffer, where two or more of the pipelines each (a) reads a plurality of current units from the first data units and (b) decrements a respective one of the given counters in response to each read of one of the current units, (ii) monitor the decrements of the given counters and (iii) block a second data unit from being copied into the buffer until all of the given counters indicate that the buffer has room to hold the second data unit.

Abstract: A memory device for storing data is disclosed. The memory device comprises a plurality of memory banks, wherein each memory bank comprises a plurality of addressable memory cells. The memory device also comprises a plurality of pipelines each comprising a plurality of pipestages, wherein each pipeline is associated with a respective one of the plurality of memory banks. Further, the device comprises a plurality of cache memories, wherein each cache memory is associated with a respective one of the plurality of memory banks and a respective one of the plurality of pipelines, and wherein each cache memory is operable for storing a second plurality of data words and associated memory addresses, and wherein further each data word of said second plurality of data words is either awaiting write verification associated with a given segment of an associated memory bank or is to be re-written into a given segment of said associated memory bank.

Abstract: Certain aspects of the present disclosure provide techniques for scalably and efficiently converting linear image data into multi-dimensional image data for multimedia applications. In one example, a method for managing image data includes receiving a line of image data in a linear format via a system bus of width T, wherein the image data's native format is a tile format of H lines per tile; forming H subsets of image data from the line of image data in the linear format; writing the H subsets of image data to a memory comprising BN=H banks of BW=T/BN pixel width, wherein each subset of the H subsets is written to a different bank of the BN banks; and outputting the H subsets of image data in the tile format.

Abstract: Systems, methods, and computer programs are disclosed for providing power-efficient file system operation to a non-volatile block memory. An exemplary embodiment of a system comprises a non-volatile block memory having a file system, a dynamic random access memory (DRAM), and a system on chip (SoC). The SoC comprises a central processing unit (CPU), one or more non-core processors, a DRAM controller, a data interface coupled to an off-chip processor, and a multi-host storage controller. The CPU allocates a storage buffer in the non-volatile block memory. The multi-host storage controller comprises a virtualized client interface for providing the non-core and off-chip processors with direct read/write file system access using the allocated storage buffer while the CPU and the DRAM are in a low power state.

Abstract: Systems, apparatuses, and methods for tracking page reuse and migrating pages are disclosed. In one embodiment, a system includes one or more processors, a memory access monitor, and multiple memory regions. The memory access monitor tracks accesses to memory pages in a system memory during a programmable interval. If the number of accesses to a given page is greater than a programmable threshold during the programmable interval, then the memory access monitor generates an interrupt for software to migrate the given page from the system memory to a local memory. If the number of accesses to the given page is less than or equal to the programmable threshold during the programmable interval, then the given page remains in the system memory. After the programmable interval, the memory access monitor starts tracking the number of accesses to a new page in a subsequent interval.

Abstract: Methods and systems may provide for an apparatus having a graphics processing unit (GPU) and a non-volatile memory dedicated to the GPU. If a request for content is detected, a determination may be made as to whether the non-volatile memory contains the content.

Abstract: An apparatus and method are described for managing a virtual graphics processor unit (GPU). For example, one embodiment of an apparatus comprises: a dynamic addressing module to map portions of an address space required by the virtual machine to matching free address spaces of a host if such matching free address spaces are available, and to select non-matching address spaces for those portions of the address space required by the virtual machine which cannot be matched with free address spaces of the host; and a balloon module to perform address space ballooning (ASB) techniques for those portions of the address space required by the virtual machine which have been mapped to matching address spaces of the host; and address remapping logic to perform address remapping techniques for those portions of the address space required by the virtual machine which have not been mapped to matching address spaces of the host.

Abstract: Disclosed herein are techniques to provide both asynchronous frame updates and panel self-refresh in a single implementation. A platform can be arranged to provide frame updates asynchronously with the refresh rate of a connected panel while the connected panel can be arranged to self-refresh where no new updates are provided.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for queuing storage operations. An integrated circuit memory element receives a storage operation command associated with a bank of storage locations of a memory element. An integrated circuit memory element queues a storage operation command for execution on a bank of storage locations by determining a storage location in a page register for data associated with the storage operation command. A storage location in a page register includes a subset of available storage locations in the page register. An integrated circuit memory element stores data associated with a storage operation command at a determined storage location in a page register.

Abstract: The present describes low latency streaming using temporal frame transformation. An execution component in an edge server executes a first instance of an application. A server interface component receives, from a remote server, a resolution delta frame indicating differences between a high resolution first frame and a low resolution first frame of a second instance of the application or, alternatively, receives the high resolution first frame. A video manipulation component generates a motion delta frame by identifying differences between a low resolution first frame and a low resolution second frame of the first instance of the application. The video manipulation component generates a high resolution transformed frame by applying the resolution delta frame and the motion delta frame to the low resolution second frame.

Abstract: A computer-implemented method, computer program product, and computer processing system are provided for eliminating a memory fence for reading a read-mostly volatile variable of a computer system. The read-mostly variable is read from more than written to. The method includes writing data to the read-mostly volatile variable only during a Stop-The-World (STW) state of the computer system. The method further includes executing the memory fence in any mutator threads and thereafter exiting the STW state. The method also includes reading the read-mostly volatile variable by the mutator threads without executing the memory fence after the STW state.

Abstract: A graphics processing system has a rendering space which is divided into tiles. Primitives within the tiles are processed to perform hidden surface removal and to apply texturing to the primitives. The graphics processing system includes a plurality of depth buffers, thereby allowing a processing module to process primitives of one tile by accessing one of the depth buffers while primitive identifiers of another, partially processed tile are stored in another one of the depth buffers. This allows the graphics processing system to have “multiple tiles in flight”, which can increase the efficiency of the graphics processing system.

Abstract: An apparatus for a microprocessor computer system and method for configuring the same where said microprocessor computer system comprises a processor core and at least one hardware buffer FIFO with memory-mapped head and tail that handles data movement among the processor cores, networks, raw data input and outputs, and memory. The method for configuring said microprocessor computer system comprises utilizing a FIFO auxiliary processor to process said data traversing said hardware FIFO; utilizing said hardware FIFOs to efficiently pipe data through functional blocks; and utilizing a FIFO controller to perform DMA operations that include non-unit-stride access patterns and transfers among processor cores, networks, raw data input and outputs, memory, and other memory-mapped hardware FIFOs.

Abstract: The present disclosure relates generally to improved systems and methods for control of a first-in, first-out (FIFO memory). More specifically, the present disclosure relates to improved timing and/or control signals used to control operation of the FIFO memory. For example, access circuitry of the memory device may pulse a control signal used to control latching of data at the FIFO memory. Further, the access circuitry may pulse one or more bits of a column address bus to generate a column address corresponding to data to be latched at the FIFO memory. Accordingly, the current, power, and/or area consumed by the memory device may be reduced.

Abstract: An image processing device includes: an integrated circuit chip arranged on a substrate to perform processing on image data; a first memory chip arranged adjacent to the integrated circuit chip on the substrate and connected to the integrated circuit chip; and a second memory chip stacked on the integrated circuit chip and connected to the integrated circuit chip, wherein the integrated circuit chip sets, according to the processing content, any one of a plurality of operation modes including a first operation mode to operate the first memory chip and limit operation of the second memory chip, and a second operation mode to operate the first memory chip and the second memory chip.

Abstract: A layout engine generates a visual layout tree for a visual description tree of a document whose content is to be rendered in one or more display areas. A visual description tree describes the content of a document along with formatting and logical arrangement the content. Visual description nodes of a visual description tree represent the organization of the constituent elements a document hierarchically. A visual layout tree defines the layout of a document within one or more display areas. Visual layout nodes of a visual layout tree represent the layout of the content of a document hierarchically. The layout engine receives as input a visual description tree and generates the corresponding visual layout tree. A rendering engine then inputs the visual layout tree and generates a graphics buffer containing the pixels representing the layout of the document as defined by the visual layout tree.

Abstract: A communication apparatus includes the first memory unit which stores data to be a sending target to another communication apparatus and the second memory unit accessible at higher speed than the first memory unit, and transfers the sending target data to the second memory unit concurrently with transfer of the data to the first memory unit. The communication apparatus sends the sending target data from the second memory unit to the other communication apparatus and discards the data from the second memory unit after that sending and before receiving a response to the data from the other communication apparatus. When resending the data, resending processing to the other communication apparatus is performed based on the data transferred to the first memory unit.

Abstract: Devices that include a logic circuit and first and second buffers are provided. The first buffer is spaced apart from the logic circuit by a first distance (and/or is refreshed in a first cycle), and the second buffer is spaced apart from the logic circuit by a second distance that is shorter than the first distance (and/or is refreshed in a second cycle that is different from the first cycle). Moreover, the logic circuit is configured to output, to the first buffer, first data corresponding to fewer toggles than second data that is output from the logic circuit to the second buffer. Methods of operating the devices are also provided.

Abstract: A technique for graphics processing, which completes graphics processing of an image loaded from a system memory by performing a series of slice processing steps. A device for graphics processing has an internal vector dynamic memory for buffering slices of pixel data loaded from the system memory. The internal vector dynamic memory has a first buffer for buffering non-overlapped pixel data, which is not reused in a next slice processing step and a second buffer for buffering overlapped pixel data, which is reused in the next slice processing step.

Abstract: Methods and systems for attention-based rendering on an entertainment system are provided. A tracking device captures data associated with a user, which is used to determine that a user has reacted (e.g., visually or emotionally) to a particular part of the screen. The processing power is increased in this part of the screen, which increases detail and fidelity of the graphics and/or updating speed. The processing power in the areas of the screen that the user is not paying attention to is decreased and diverted from those areas, resulting in decreased detail and fidelity of the graphics and/or decreased updating speed.

Abstract: A system-on-chip (SoC) device includes: a display controller configured to receive a trigger signal, and to output image data based on the trigger signal; and a transceiver configured to receive a first interrupt. In a first mode, the display controller is configured to output the image data in synchronization with a pulse of the trigger signal. In a second mode, which is different from the first mode, the display controller is configured to output the image data in synchronization with a pulse included in the trigger signal only after receiving the first interrupt.

Abstract: A data processing system can use a method of fine-grained address space layout randomization to mitigate the system's vulnerability to return oriented programming security exploits. The randomization can occur at the sub-segment level by randomizing clumps of virtual memory pages. The randomized virtual memory can be presented to processes executing on the system. The mapping between memory spaces can be obfuscated using several obfuscation techniques to prevent the reverse engineering of the shuffled virtual memory mapping.

Abstract: A display device correction method is provided for correcting luminance unevenness in a display device including pixels, which are arranged in a matrix and include light-emitting elements that emit light according to a luminance signal. The method includes obtaining in advance first correction data, which includes correction data components each corresponding to a different one of the pixels and is for correcting the luminance signal. The method also includes transforming the first correction data into second correction data by decomposing the correction data components included in the first correction data into frequency components, and removing a predetermined frequency component among the frequency components. The method further includes correcting the luminance signal using the second correction data.

Abstract: A color test pattern comprising color patches can be printed together with an image (text and/or a pictures, for example) of a print job. After printing, reflections, known as flare, from the image may adversely affect measurements taken of the color patches. To help reduce the effects of flare, a determination is made prior to printing as to the layout of the color patches. The determination involves comparing the color properties of the color patches with those of the image.

Abstract: An image processing apparatus includes an extraction unit, a memory controller, and a transfer unit. The extraction unit extracts, on the basis of image information, pieces of color information having a high frequency of occurrence as color information that is necessary to perform image processing. The memory controller causes a first memory to store a color information group including the pieces of color information extracted by the extraction unit. The transfer unit transfers the color information group from the first memory to a second memory, an access time of the second memory being shorter than an access time of the first memory.

Abstract: Active gameplay of a video game on a computer gaming device is overseen by a platform-level in-game recording companion that executes separately from any of a plurality of different video games. During active gameplay of the video game, the active gameplay is continuously and automatically buffered to a temporary storage buffer. During active gameplay the computer gaming device receives a command to save a segment of the active gameplay for subsequent viewing. While displaying gameplay of the currently-executing video game, an interface for the platform-level in-game recording companion is displayed. The segment of the active gameplay is saved from the temporary storage buffer to a library of the platform-level in-game recording companion.

Abstract: An apparatus includes an integrated circuit configured to be operatively coupled to a sensor array that is configured to generate an ultrasonic wave. The integrated circuit includes a transmitter circuit configured to provide a first signal to the sensor array. The integrated circuit further includes a receiver circuit configured to receive a second signal from the sensor array in response to providing the first signal. The sensor array includes an ultrasonic transmitter configured to generate the ultrasonic wave in response to the first signal and a piezoelectric receiver layer configured to detect a reflection of the ultrasonic wave.

Abstract: When untransformed display lists are used in a tile-based graphics processing system, the processing involved in deriving sub-primitives may need to be performed in both the geometry processing phase and the rasterization phase. To reduce the duplication of this processing, the control stream data for a tile includes sub-primitive indications to indicate which sub-primitives are to be used for rendering a tile. This allows the sub-primitives to be determined efficiently in the rasterization phase based on this information determined in the geometry processing phase. Furthermore, a hierarchical cache system may be used to store a hierarchy of graphics data items used for deriving sub-primitives. If graphics data items for deriving a sub-primitive are stored in the cache, the retrieval of these graphics data items from the cache in the rasterization phase can reduce the amount of processing performed to derive the sub-primitives.

Abstract: Systems and methods for live migration are provided. A hypervisor receives a request to migrate a virtual machine from a source host machine to a destination host machine, and maps memory of the virtual machine on the source host machine to a storage device accessible by the source host machine and by the destination host machine.

Abstract: Provided are a touch display control device and an information terminal device, which are arranged so that the noise resulting from the actions for activation and display on a display panel, and the noise caused by the actions of activation and detection on a touch sensor never affects each other, and are useful for suppressing the elicitation of the difference in brightness attributed to non-display in a display frame. The information terminal device includes: a display controller operable to change start timings of display and non-display periods in a cycle of a frame synchronizing signal of a display frame, in each cycle of the frame synchronizing signal or each sequence of cycles thereof; and a touch panel controller operable to perform the activation of a touch panel and a touch detection during the non-display period.

Abstract: A method and apparatus for video encoding to generate a partitioned bitstream without buffering transform coefficient and/or prediction data for subsequent coding units are disclosed. An encoder incorporating an embodiment according to the present invention receives first video parameters associated with a current coding unit, wherein no first video parameters associated with subsequent coding units are buffered. The encoder then encodes the first video parameters to generate a current first compressed data corresponding to the current coding unit. A first memory address in the first logic unit is determined and the encoder provides the current first compressed data at the first memory address in the first logic unit.

Abstract: A memory control apparatus including: a writing unit configured to output a write request for writing to a memory and issues a first event every time a write operation of each of the first blocks is completed; a reading unit configured to output a readout request for reading of image data that has been written to the memory by the writing unit and issues a second event every time a readout operation of the second block is completed; and a controller that performs a process of incrementing a count value in response to the first event, performs a process of decrementing the count value in response to the second event, and controls whether to permit the write request and the readout request, respectively, based on the count value.

Abstract: A graphics processing system has a rendering space which comprises one or more tiles. The system comprises a processing module configured to perform hidden surface removal for primitives of a tile to determine primitive identifiers identifying the primitives which are visible at each of a plurality of sample positions in the tile. A set of two or more tag buffers store the primitive identifiers determined for each of the sample positions in a tile, thereby representing overlapping layers of primitives. A tag control module controls: (i) selection of a tag buffer for the storage of each of the primitive identifiers according to the layering of the primitive identifiers stored in the tag buffers, and (ii) flushing of primitive identifiers from the tag buffers. A texturing engine applies texturing to the primitives identified by the flushed primitive identifiers.

Abstract: An aspect of the present invention proposes a method for performing partial refresh on display panels. According to one or more embodiments of the present invention, the display panels may be implemented as self-refreshing display panels communicatively coupled with a computing device that generates graphical data for display in the display panel. To perform partial refresh, consecutive frames are compared to identify the portions of the frames with updated material. In one or more embodiments, only the pixels corresponding to the updated portion(s) are refreshed in the display panel.

Abstract: An apparatus having an interface and a circuit is disclosed. The interface may be connectable to a plurality of counters and a plurality of pipelines. The circuit may be configured to increment the counters associated with a first data unit in response to the first data unit being available in a buffer, and monitor a plurality of decrements of the counters by the pipelines. Each pipeline may decrement a respective counter when finished with the first data unit in the buffer. The circuit may also be configured to block the pipelines from processing a second data unit in the buffer until all of the counters associated with the first data unit have been decremented.

Abstract: A driving system capable of supporting multiple display modes is provided. The driving system includes a memory for storing gamma codes corresponding to various display modes, a gamma voltage generation device producing gamma voltages corresponding to the gamma codes, and a timing controller accessing the gamma codes stored in the memory and writing the gamma codes into the gamma voltage generation device according to mode switch signals. The gamma voltage generation device then produces gamma voltages corresponding to the input gamma codes during the vertical blank interval of the display device, thereby achieving display mode switch. The memory may also be integrated in the timing controller. Compared to the prior art, the driving system is compatible with various display modes with reduced cost.

Abstract: The present disclosure includes apparatuses, systems, and methods related to multiple address registers for a solid state device (SSD). An example apparatus includes a controller including a plurality of base address registers (BARs) each including same addresses for data storage in a same memory resource and an SSD that includes the same memory resource.

Abstract: A parallel processor and a method of reducing texture cache invalidation are disclosed. In one embodiment, the parallel processor includes a cache configured to receive lines of data; and a parallel execution unit associated with the cache and configured to execute parallel counterparts of an operation. The parallel counterparts, when executed, are configured to create, in the cache, corresponding aliases of a line of data pertaining to the operation such that the parallel counterparts are operable to invalidate only the corresponding aliases.

Abstract: Methods, systems, and apparatus, including an apparatus for accessing data. In some implementations, an apparatus includes address offset value elements that are each configured to store an address offset value. For each address offset value element, the apparatus can include address computation elements that each store a value used to determine the address offset value. One or more processors are configured to receive a program for performing computations using tensor elements of a tensor. The processor(s) can identify, in the program, a prologue or epilogue loop having a corresponding data array for storing values of the prologue or epilogue loop and populate, for a first address offset value element that corresponds to the prologue or epilogue loop, the address computation elements for the first address offset value element with respective values based at least on a number of iterations of the prologue or epilogue loop.