Abstract: A memory aarrangement for exposure data used in multiple exposures stores gray level data which include a high bit portion and a low bit portion. The memory arrangement includes a first memory for storing the high bit portion of the gray level data and a second memory for storing the low bit portion of the gray level data. The first memory and the second memory can be controlled by separate chip selection control signals. Further, the memories are provided with two separate byte enable signals, respectively, to control accesses to a high byte and a low byte in each memory unit. In writing, the gray level data are written in an interleaving manner to avoid conflicts between data lines. In reading, the high byte and the low byte which are interleaved are exchanged before they are read out.

Abstract: This invention discloses a novel collaborative screen sharing system. In the invented method for collaborative screen sharing, updates to a previously displayed screen are transmitted from a local computer to a remote computer for display. At the local computer, the updates are divided into unit blocks circulated by rigid lines and compared with screen displays stored in the cache memory of the local computer and the remote computer. In transmitting the updates, only identities of unit blocks with screen display identical to screen displays previously stored are transmitted. For unit blocks with screen display not identical to any screen display previously stored, identities and screen display information of the unit blocks are transmitted. Images and unit blocks stored in the local computer and the remote computer are maintained identical and are updated simultaneously.

Abstract: An image processing apparatus is composed of a plurality of function processing units for performing image processing, a high priority function selection part for selecting functions, execution of each of which is required by a corresponding one of the function processing units, based on the predetermined priority for each of the functions; and a data control unit including a data transfer part for preferentially accessing the shared memory which the function selected by the high priority function selection part requires, and a plurality of data holding parts, each of the data holding parts holding a predetermined amount of data transmitted with each of the plurality of function processing units, wherein the data transfer part controls the bus connecting the CPU and the shared memory based on requirement sent from each of the function processing units, and each of the plurality of function processing units transmits data with the data control unit separately from the others of the plurality of function proces

Abstract: A graphics system using multiple processors which is able to fully support multi-processor operation using only PCI read operations between processors. Each of the graphics processors performs its operations on its respective scanlines, and writes to its own framebuffer, but the need for writes from one processor to the framebuffer of another processor is eliminated.

Abstract: An imaging device and a method for implementing simultaneous image capture and image display update in an imaging device are provided. The imaging device of the present invention implements first and second image capture buffers within a memory module such that a first buffer captures image data from the imager while the second buffer displays the image on the imaging device display. A method for simultaneous image capture and image display update comprises capturing first-in-time image data to a first image capture buffer that is in communication with an imager, capturing second-in-time image data to a second image capture buffer that is in communication with an imager and displaying the first-in-time image data on a display while the image device captures the second-in time image data to the second image capture buffer.

Abstract: A method and apparatus for implementing a dynamic display memory is provided. A memory control hub suitable for interposition between a central processor and a memory includes a graphics memory control component. The graphics memory control component determines whether operands accessed by the central processor are graphics operands. If so, the graphics memory control component transforms the virtual address supplied by the central processor to a system address suitable for use in locating the graphics operand in the memory. In one embodiment, the graphics control component maintains a graphics translation table in the memory and utilizes the graphics translation table in transforming virtual addresses to system addresses. Furthermore, in one embodiment, the graphics control component reorders the addresses of the graphics operands to optimize for performance memory accesses by a graphics device.

Abstract: A method and apparatus are disclosed for achieving improved mipmapped texture mapping performance in computer graphics systems. Page residence indicators obviate the need for address comparisons during texel accessing. A mipmap page number is generated for texture data of interest. A page residence bit is then selected responsive to the mipmap page number. If the page residence bit is in a first state, then the texture data is retrieved from a memory located within the graphics subsystem; but if the page residence bit is in a second state, then the texture data is retrieved from system memory. System-wide texture offset addressing obviates the constraints associated with fixed relative addressing schemes.

Abstract: In a device and system which perform processing (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.

Abstract: An MPEG decoder and an MPEG decoding method with two memory controllers is capable of separately controlling compressed data and decoded data. An MPEG decoder decodes a compressed input data formatted in an MPEG type. The MPEG decoder comprises a compressed data memory controller and a decoded data memory controller. The compressed data memory controller is coupled to a compressed data memory and controls the compressed data. The decoded data memory controller is coupled to a decoded data memory, and controls the decoded data. Since the compressed data flow and the decoded data flow are divided, the memory transfer rate is increased, and also the memory control is simple. In addition, the compressed data are able to be stored within the MPEG decoder. Therefore, the high-performance of the MPEG decoder and the high quality of the image are possible.

Abstract: A method of increasing the speed of image creation on a computer system for the interactive creation of images via a series of creation steps. A resultant image of each of the creation steps is copied to a corresponding separate storage buffer. When making an amendment to the series of creation steps previously performed, one or more of the resultant images is used, so as to reduce the rendering time of producing a final output image.

Abstract: A method of buffering graphics vertex commands adaptively. A minimally-formatted vertex values buffer is created. As vertex commands are received from application software, attribute values are stored in an attribute values buffer until a vertex coordinate command is received. Upon receipt of a vertex coordinate command, attribute values are copied from the attribute values buffer into the vertex values buffer. Whenever application software issues a vertex attribute command corresponding to an attribute type that is not currently reflected in the vertex values buffer format, the vertex values buffer is automatically reformatted to include the new attribute type. Thus, the vertex values buffer automatically adapts itself to the behavior of the application. Multiple primitives are buffered between flushes. First-call and subsequent-call versions of code are provided for vertex commands. At initialization, a dispatch table is populated with pointers to the first-call versions.

Abstract: An object is to provide a serial access memory and a data write/read method applicable thereto and capable of reducing the test time of the serial access memory. After transferring the data stored in the memory cells MC11 to MCm1 connected with a word line WL1 to the read registers Rreg-1 to Rreg-m all at once, the data stored in the memory cells MC12 to MCm2 connected with a word line WL2 is transferred to the write registers Wreg-1 to Wreg-m all at once. The data stored in the read register is transmitted to an output means 123 through read data buses RD, /RD. The data stored in the write register is transmitted to the output means 123 through write data buses WD,/WD, an input/output means 122, and the second read data buses RD2, /RD2. The output means 123 compares the data transmitted from the read data buses RD, /RD with the data transmitted from second data buses RD2, /RD2.

Abstract: A video graphics system wherein a large quantity of video data is independently and selectively made available to plural video display devices. The large quantity of video data can be contributed to by plural sources of video data of differing formats. Further, the display devices can also be of varying types, each requiring a different input data format. A multi-sourced video distribution element, also referred to as a hub, serves as an interface between one or more sources of video display data and one or more video display devices. One source of data can be identified as a base image, and other sources of data can be utilized for overlay images integrated into the base image. The base image and any integrated overlay images are provided on a pixel bus internal to the hub. The hub can then be configured as an interface to one or more types of video display devices and/or to another hub.

Abstract: The present invention provides a graphics memory system of a computer graphics display system which utilizes a batching architecture in conjunction with detached Z buffering for minimizing paging overhead. The graphics memory system comprises a memory controller which receives a batch of pixels from a host CPU of the computer graphics display system when a 3D rendering mode is in effect. Each pixel has a pixel color and corresponding Z coordinate associated with it. The memory controller then performs a Z comparison test wherein Z coordinates of the batch are compared with existing Z coordinates read out of a frame buffer memory to determine whether or not each new color of the batch associated with the Z coordinate being compared should be written into the frame buffer memory. If the results of a Z comparison test pass, the new pixel color and Z coordinate are queued for writing into the frame buffer memory.

Abstract: A volume rendering process is disclosed. Data including a plurality of voxels are recorded. Each voxel includes an opacity-adjusted value representative of a value of a parameter at a location within the volume adjusted by applying an opacity curve to the value. A computer is used to process such data. The process includes partitioning the plurality of voxels among a plurality of slices. Each slice corresponds to a respective region of the volume. For each slice, the process apportions the plurality of voxels associated with that slice among a plurality of cells associated with that slice. Each cell corresponds to a respective sub-region of the region associated with that slice. For each cell, the process determines that the cell is nontransparent if more than a predetermined number of the voxels associated with that cell have an opacity-adjusted value greater than a predetermined value. Otherwise the cell is determined to be transparent.

Abstract: A data table includes a source pointer indicating a starting address of drawing data, a destination pointer indicating a destination of drawing data to be transferred, and a data length indicating a data length of drawing data to be transferred. Data table may indicate drawing data to be drawn. Thus frames may share drawing data. As such the amount of drawing data can be reduced.

Abstract: The present invention provides a graphics memory system of a computer graphics display system which utilizes a batching architecture in conjunction with detached Z buffering for minimizing paging overhead. The graphics memory system comprises a memory controller which receives a batch of pixels from a host CPU of the computer graphics display system when a 3D rendering mode is in effect. Each pixel has a pixel color and corresponding Z coordinate associated with it. The memory controller then performs a Z comparison test wherein Z coordinates of the batch are compared with existing Z coordinates read out of a frame buffer memory to determine whether or not each new color of the batch associated with the Z coordinate being compared should be written into the frame buffer memory. If the results of a Z comparison test pass, the new pixel color and Z coordinate are queued for writing into the frame buffer memory.

Abstract: In an image processing apparatus, a figure data storage unit stores a figure data for a figure, and pixels of the figure data are allocated with figure data addresses. A display buffer unit stores a display figure data, and an object table unit stores an object table which storing a set of display parameters for a deformed figure of the figure. The object table unit outputs the set of display parameters in response to an object designating instruction. An address generating unit stores at least a form table which stores ones of the figure data addresses for the deformed figure as deformed figure addresses. The address generating unit outputs, as read addresses, addresses including the deformed figure addresses to the figure data storage unit based on the set of display parameters supplied from the object table unit to read out at least a portion of the figure data from the figure data storage unit, and stores the read out figure data portion in the display buffer unit as the display figure data.

Abstract: A data processing device and a method by which image data inputted line by line can be distributed as image data of the plural lines, and processing of the image data and converting the image data to a multiple beam image data can be performed by use of separate memories.

Abstract: An image processing system is described in which a data buffer memory 4 is provided between an image processor 2 and an image frame memory 8. The data buffer memory 4 stores a sub-set of the raster lines stored within the image frame memory 8. This data can be read in either an intra-raster-line mode from adjacent memory cells within a bank or in an inter-raster-line mode from memory cell locations at corresponding positions within different banks. The data may be 8-bit pixel data or 16-bit pixel data. In the case of 8-bit pixel data a single bank contains a full raster line whereas in the case of 16-bit pixel data a single raster line extends over two banks.

Abstract: A test pattern which has an outputted image obtained by said image processing executing normal image processing is used to self-judge an image processor. Namely, image data of the above described test pattern is transmitted to the image processor and image processing is effected by the image processor. The image outputted (the results of the image processing) from this image processing and the original image are compared to each other. When they do not correspond to each other, the image processing by the current image processor is judged to be abnormal. In this case, the image processing using the image processor (hard ware process) is switched promptly and automatically to be emulated by an auto set-up engine (soft ware process). Further, in the image processor section, ordinarily, all of the three frame memories are used to effect processes including reading of image data, image processing, and outputting of image data at the same time and in parallel.