Abstract: An interface unit 20 assigns different SDRAMs 1 and 2 to adjacent drawing blocks in a frame-buffer area. In processing that extends across the adjacent drawing blocks, active commands, for example, are issued alternately to the SDRAMs 1 and 2 to reduce waiting cycles resulting from the issue interval restriction. Furthermore, since individual clock enable signals CKE1 and CKE2 are output to the SDRAMs 1 and 2 so that burst transfers of the SDRAMs 1 and 2 can be stopped individually, no cycle is necessary to stop the burst transfers.

Abstract: A system and method for efficiently linking together replicas of a storage object. The location of a first replica of the storage object may be stored on a node in a network. When new replicas of the storage object are created, the node that stores the new replica may efficiently lookup the location of the first replica and utilize the location information to perform an efficient process to link the new replica to the first replica and any other existing replicas by causing routing information to be created on various nodes.

Abstract: Embodiments of methods and apparatus for memory training concurrent with data transfers are disclosed. For an example embodiment, data may be transferred from a first memory device to a first partition of a memory controller, and a training operation may be performed for a second partition of the memory controller coupled to a second memory device while the first partition of the memory controller is transferring data from the first memory device.

Abstract: A controller driver includes a color palette circuit configured to hold color palette data indicating a relation of a color reference numbers corresponding to a color and RGB data corresponding to the color, a first memory section configured to hold first layer data containing first RGB data specifying a color of each of pixels of a first layer image; a second memory section configured to hold second layer data containing a color reference number specifying a color of each of pixels of a second layer image; a calculating circuit configured to generate synthetic image data of the first layer data and the second layer data; and a driving circuit configured to drive a display panel based on the synthetic image data.

Abstract: A display device includes a plurality of electronic papers that are each provided with a display surface outputting a piece of display data, a binding member that binds together the plurality of electronic papers, and an output device that controls output of the piece of display data to each of the plurality of electronic papers, a first storage device that stores rewrite information, a second storage device that stores a plurality of pieces of display data to be displayed on the plurality of electronic papers, an allocation device that respectively allocates the plurality of pieces of display data stored in the second storage device to a consecutive series of electronic papers for which the rewrite information permits rewriting, and a display control device that respectively displays the plurality of pieces of display data allocated by the allocation device on the consecutive series of electronic papers.

Abstract: Circuits, methods, and apparatus for efficiently storing page characteristics. Page characteristics for memory pages are stored post address translation using addresses for physical locations in memory, for example, in a bit vector. The characteristics may include access or dirty bits, as well as other types of information. These bit vectors can also be stored and accumulated to generate histogram data. Two bit vectors may be included, while a first bit vector is written to, another is used. After data has been written to the first, the bit vectors are flipped, and data is written to the second while the first is used.

Abstract: The proposed technique provides simultaneous read and writes from a display controller using low-cost SDRAMs. This is achieved, in one example embodiment, by receiving a sequence of video frames at a first variable frame rate. A first video frame is then written in a first single-ported memory. The first video frame is then read from the first single-ported memory upon completing the writing of the first video frame in the first single-ported memory. The reading of the first video frame is then repeated from the first single-ported memory to maintain a second frame rate. The second frame rate is higher than the first variable frame rate. A second video frame is then written in a second single-ported memory upon completing the writing of the first video frame in the first single-ported memory such that the writing of the first video frame and the second video frame is at the first variable frame rate.

Abstract: The present invention provides a data processing apparatus and method for merging secure and non-secure data. The apparatus comprises at least one processor operable to execute a non-secure process to produce non-secure data to be included in an output data stream, and to execute a secure process to produce secure data to be included in the output data stream. A non-secure buffer is provided for receiving the non-secure data produced by the non-secure process, and in addition a secure buffer is provided for receiving the secure data produced by the secure process, the secure buffer not being accessible by the non-secure process. An output controller is then arranged to read the non-secure data from the non-secure buffer and the secure data from the secure buffer, and to merge the non-secure data and the secure data in order to produce a combined data stream, the output data stream then being derivable from the combined data stream.

Abstract: A binning architecture that allows opaque and transparent primitives to be segregated automatically into pairs of bins covering the same bin rectangle on the screen. When the frame is complete, the opaque bin will be rendered first and then the transparent bin will be rendered repeatedly using the depth peeling algorithm until all the layers have been resolved. This will happen automatically without requiring the application to isolate and store the transparent primitives until all of the opaque primitives have been rendered or submit the transparent primitives repeated until all of the transparent layers have been resolved.

Abstract: A display memory circuit includes a drawing memory and a dynamic display memory. The drawing memory stores data and at least a portion of the data are possibly rewritten into a new data at a third timing, the third timing being optional between a first timing and a second timing. The dynamic display memory is connected with the drawing memory, which latches the data in response to the first timing and continues to hold the data between the first timing and the second timing. The drawing memory is partially disconnected from the dynamic display memory in the rewritten portion when the portion is rewritten in the drawing memory.

Abstract: A graphics chip is described for performing operations required by a display device to generate display images. The graphics chip includes a display controller and an internal frame buffer coupled to the display controller, which is used to store display data. The graphics chip further includes a data copy logic to copy display data from an external frame buffer to the internal frame buffer as the display controller reads the display data from the external frame buffer.

Abstract: Systems and methods for converting graphics data represented in a hexadecimal form into a quad form may be used to reorganize the graphics data for performing raster operations. Prior to performing raster operations the graphics data received for each component is assembled to interleave the components for each pixel as needed to perform the raster operations. The assembly process varies depending on the number of bits per component, the number of components to be processed, and the memory format of the render target used to store the processed graphics data.

Abstract: The present invention provides a method and apparatus for image processing using a graphics processor in a handheld device including a first memory device receiving a video input signal containing encoded video frame having a plurality of portions of encoded video frame data. The first memory device has a storage capacity less than all of the plurality portions of the encoded video frame data. The method and apparatus further includes the graphics processor coupled to the first memory device, wherein the graphics processor receives the first portion of the encoded video frame data and generates a first graphics portion. A second memory device receives the first graphics portion and stores the first graphics portion therein. As such, the encoded video frame is processed on a portion-by-portion basis using the first memory device and the second memory device in conjunction with the graphics processor.

Abstract: Circuits, methods, and apparatus that allow the elimination of a frame buffer connected directly to a graphics processing unit. The graphics processing unit includes an on-chip memory. Following system power-up or reset, the GPU initially renders comparatively low-resolution images to the on-chip memory for display. Afterward, the GPU renders images, which are typically higher resolution, and stores them in a system memory, apart from the graphics processing unit. The on-chip memory, which is no longer needed for image storage, instead stores address information, referred to as page tables, identifying the location of data stored by the GPU in the separate system memory.

Abstract: A data distribution device includes a pair of first storage units, a second storage unit which includes a dual-port memory, a write unit which repeatedly writes drive data into one of the pair of first storage units and thereafter writes the remaining drive data and a read output unit which outputs the respective concurrently read drive data to the k corresponding drive circuits concurrently, where read addresses read from the dual-port memory are not overtaken by write addresses written to the dual-port memory during the period in which reading and writing of the drive data are being simultaneously performed with respect to the dual-port memory of the second storage unit.

Abstract: Circuits, methods, and apparatus that reduce the amount of data transferred between a graphics processor integrated circuit and graphics memory. Various embodiments of the present invention further improve the efficiency of blenders that are included on a graphics processor. One embodiment provides for the storage of a reduced number of subsamples of a pixel when the storage of a larger number of subsamples would be redundant. The number of subsamples that are blended with source data are compressed, thereby reducing the task load on the blenders increasing their efficiency. These methods can be disabled to avoid errors that may arise in certain applications.

Abstract: A computer graphics method and apparatus allows designer control over the rendering of objects and scenes, in a rendering system using ray tracing for example. A modeling system is adapted to accept rules for controlling how certain objects affect the appearance of certain other objects. In a ray tracing implementation, rules are specified by ray type and can be specified as either “including” all but certain objects or “excluding” specific objects for any given object. A rendering system extracts these rules from a bytestream or other input including other graphics data and instructions, and populates lists for internal use by other components of the rendering system. A ray tracer in the rendering system is adapted to consult the list when performing ray tracing, so as to enforce the rendering control specified by the content creator when the objects and scene are rendered.

Abstract: A system of processing data in a graphics processing unit having a core configured to process data in hexadecimal form and other graphics modules configured to process data in quads includes a transpose buffer with a crossbar to reorganize incoming data, several memory banks to store the reorganized data over a period of several clock cycles, and a second crossbar for reorganizing the stored data after it is read from the bank of memories in one clock cycle. The method for converting between data in hexadecimal form and data in quads includes providing data in hexadecimal form, reorganizing the data provided in hexadecimal form, storing the reorganized data in several memories, and reading several of the memory locations, which contain all of the elements of the quad, in one clock cycle.

Abstract: A memory hub permits a graphics processor to access random access memories, such as dynamic random access memories (DRAMs). In one implementation, the memory hub permits an increase in effective memory bandwidth by aggregating the memory of two or more memories. In another implementation, the memory hub permits a graphics processor to offload memory access interfacing operations to the memory hub.

Abstract: An apparatus comprising a memory and a coder/decoder circuit. The memory may have a first memory portion and a second memory portion. The coder/decoder circuit may be configured to (i) position a set of atoms across the memory, (ii) define a strip across a portion of the atoms, (iii) designate a first atom within the strip, (iv) locate one or more second atoms to be paired with the first atom, (v) determine whether the one or more second atoms when paired with the first atom forms a legitimate pair, and (vi) read the legitimate pair from the first memory portion and the second memory portion.

Abstract: A display control apparatus has a synchronizing signal generating section which generates a display synchronizing signal, a bus access control section which reads out video data for a plurality of system, one system at a time, from a local memory, a screen combining section which processes to combine video data which was readout, and video data for use in combining, sequentially, a buffer section which stores video data which was processed to be combined, and the video data for use in combining, a buffer control section which controls an access to the buffer section, a display IF section which reads out video data that the buffer section stores, and outputs the video data to each of display monitors in accordance with a display synchronizing signal, and display output selecting means which selects an output destination of video data for plural systems, which the display IF section outputs.

Abstract: An information storage medium including graphic data and presentation information, and an apparatus and method of processing the graphic data are provided. The information storage medium includes the graphic data, page composition information which defines page composition of the graphic data, and the presentation information indicating when graphic screen data, which is composed with reference to the page composition information of the graphic data, is output to a display screen. Therefore, a graphic object is reusable in graphic data processing, and accordingly, a time taken to process the graphic data is reducible and memory area may be saved.

Abstract: A memory controller that includes a write first in first out (FIFO) region of the memory for receiving pixel data and a read FIFO region of the memory for accessing the pixel data received through the write FIFO is provided. The memory controller is configured to rearrange the pixel data received by the write FIFO for storage in the memory by writing data representing a first pixel and a second pixel across a plurality of registers in the memory, wherein corresponding bit locations for the data representing the first pixel and the data representing the second pixel are stored within a same one of the plurality of registers. The memory controller is configured to grant access to one of multiple requests for access to the memory based on corresponding bit locations associated with the multiple requests. A graphics controller and a method for prioritizing access to a memory are provided.

Abstract: A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.

Abstract: Apparatus includes unit storing CG data containing data about coordinate transformation, camera, geometry, light source, and texture, unit transforming coordinate system of CG data into camera-coordinate system, unit calculating intersections of object and ray vectors passing through sampled points, unit calculating 3D motion vectors, unit calculating color values at intersections, unit assigning object IDs of intersections at 3D coordinates to intersections, unit projecting intersections and 3D motion vectors onto plane, and calculating 2D coordinates at intersections and 2D motion vectors at intersections, unit storing 2D coordinates, 2D motion vectors, color values, and object IDs together as low-resolution video data, unit calculating intermediate-resolution video data by superimposing low-resolution video data of current frame onto low-resolution video data of frames temporally different from current frame, unit calculating high-resolution video data by filtering intermediate-resolution video data, unit

Abstract: A method of storing an array of digital data into a memory. The memory includes a plurality of memory pages, and each memory page has a first memory section and a second memory section. The method includes a first step of dividing the array of digital data into a plurality of block units, while each of the block units has a plurality of odd rows and a plurality of even rows, and each of the odd rows and the even rows has at least one byte. The method further includes a second step of storing subsequent odd rows of at least one of the block units into consecutive storage locations in the first memory section, and storing subsequent even rows of at least one of the block units into consecutive storage locations in the second memory section. In this way, the memory bandwidth can be used more efficiently.

Abstract: A control method to control a display unit in which a video signal is supplied by an external device to display the video signal, the control method including: dividing EDID information of the display unit in essential EDID information that is required to display the video signal and non-essential EDID information excluding the essential EDID information; and storing the essential EDID information in a non-changeable memory and at least a part of the non-essential EDID information in the changeable memory.

Abstract: A method, apparatus, and system are described in which a signal is generated to inhibit the execution of flip commands that cause a flip between buffers of a frame buffer. One or more of the flip commands and their associated instruction pointers may be preloaded into a frame buffer flip queue prior to removing the signal inhibiting the execution of the flip commands.

Abstract: In response to a requirement of transferring a file from a personal computer PC to a projector 10 that is output by dragging and dropping a corresponding file icon onto a projector icon, a CPU 50 requires setting of a password. The CPU 50 maps the preset password to a file and transfers the file with the password to an external storage device of the projector 10. The projector 10 requires input of a password, which is expected to be assigned to the file, and allows reproduction of the file when the input password is coincident with the preset password.

Abstract: Methods and apparatus for storing and retrieving data using two-dimensional arrays. In one implementation, a checkerboard buffer page system includes: a data source, providing data elements in a first order; a data destination, receiving data elements in a second order; memory devices having memory pages, data elements stored and retrieved in parallel to and from the memory devices; each buffer page having entries along a first dimension corresponding to the first order and along a second dimension corresponding to the second order, data elements stored in the first order and retrieved in the second order, at least one memory page stores data elements in multiple locations according to the first and second orders, at least two data elements consecutive in the first order are stored in parallel to the memory devices, and where at least two data elements consecutive in the second order are retrieved in parallel from the memories.

Abstract: A system and method for processing graphics data which improves utilization of read and write bandwidth of a graphics processing system. The graphics processing system includes an embedded memory array having at least three separate banks of single ported memory in which graphics data are stored in memory page format. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory concurrently with reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to the bank of memory from which the pre-processed data was read. The processing pipeline is capable of concurrently processing an amount of graphics data at least equal to the amount of graphics data included in a page of memory.

Abstract: An accelerator system is implemented on an expansion card comprising a printed circuit board having (a) one or more graphics processing units (GPU), (b) two or more associated memory banks (logically or physically partitioned), (c) a specialized controller, and (d) a local bus providing signal coupling compatible with the PCI industry standards (this includes but is not limited to PCI-Express, PCI-X, USB 2.0, or functionally similar technologies). The controller handles most of the primitive operations needed to set up and control GPU computation. As a result, the computer's central processing unit (CPU) is freed from this function and is dedicated to other tasks. In this case a few controls (simulation start and stop signals from the CPU and the simulation completion signal back to CPU), GPU programs and input/output data are the information exchanged between CPU and the expansion card.

Abstract: A multi-display system and a method thereof which solves an overloading problem on a memory bus. The multi-display system includes displays which independently display separate images, a main memory which stores input image signals, image signal process units which are disposed corresponding to the displays and process the image signals according to the corresponding displays, a secondary memory which stores the image signals processed by the image signal process units, and a controller which controls the image signal process units to display the image signals stored in the main memory on each of the corresponding displays. The controller controls the image signal process units to display the image signals stored in the secondary memory on some of the displays in response to overloading of the image signals on the memory bus, through which the image signals are retrieved from, where the image signals are displayed on more than two displays.

Abstract: A method for reading atoms positioned within a memory having a first memory portion and a second memory portions, comprising the steps of (a) positioning the atoms having memory addresses across the memory, (b) defining a strip across a portion of the atoms, (c) designating a first atom within the strip, (d) locating one or more second atoms to be paired with the first atom, (e) determining whether the one or more second atoms when paired with the first atom forms a legitimate pair, and (f) reading the legitimate pair from the first memory portion and the second memory portion.

Abstract: Methods to manipulate the mobile wireless device screen more efficiently are provided. The method and devices allow a graphical user interface to be used more efficiently on a mobile handset with limited processing ability. A graphical user interface can be implemented on a mobile wireless device efficiently by limiting processing to only the areas of the display screen on the mobile wireless device that is changing. For example, if a graphical item is to be displayed on the display screen the value in the display screen memory location that will be covered by the graphical item can be stored for future use. If the graphical item is later moved the stored value can be retrieved and efficiently written to the display without the need to recalculate what was behind the graphical item.

Abstract: A memory card is connected to a host using a NAND flash memory interface mode. In addition, the memory card further includes the NAND flash memory as well as a controller. The NAND flash memory uses an interface mode different from that supported by the host. The controller converts the interface mode of the host to the interface mode of the NAND flash memory. Thus a memory card can be made compatible with a host using another interface mode.

Abstract: A system and method for managing graphical information are disclosed. The system includes a processing device, first and second memory portions within at least one memory device coupled to the processing device. The first memory portion stores a first plurality of files having a first type of information relating to graphical entities, and a second plurality of files having a second type of information relating to graphical entities, where each of the second plurality of files references at least one of the first plurality of files. The second memory portion duplicatively stores a first subset of the first plurality of files and a second subset of the second plurality of files, where each of the files of the first subset are referenced by at least one of the files of the second subset, and where the first and second subsets have information relating to a first project.

Abstract: An apparatus and method for simulating a multiported memory using lower port count memories as banks. A portion of memory is allocated for storing data associated with a thread. The portion of memory allocated to a thread may be stored in a single bank or in multiple banks. A collector unit coupled to each bank gathers source operands needed to process a program instruction as the source operands output from one or more banks. The collector unit outputs the source operands to an execution unit when all of the source operands needed to process the program instruction have been gathered.

Abstract: Apparatus and method for accessing image data in reduced transfer cycles. The image data access apparatus has: a plurality of external memories in which a plurality of parallel pixel data that are adjacent to each other in a prescribed block area of the image data are separately stored at assigned addresses; a determination circuit for outputting, based on the coordinate of at least one pixel data out of a plurality of parallel data, a memory selection signal for selecting an access route to an external memory storing the one pixel data, the coordinate obtained by raster scanning; and a memory selector for selecting access routes to the plurality of external memories based on the received memory selection signal, and accessing the plurality of parallel pixel data in the same cycle. This can realize accessing the pixel data in the external memories in reduced transfer cycles.

Abstract: In one embodiment, the invention is an apparatus. The apparatus includes a Z-buffer memory. The apparatus also includes a set of bits, each of which corresponds to a block of the Z-buffer memory. The apparatus also includes an initialization (init) register. The apparatus also includes control logic coupled to the Z-buffer memory, the set of bits, and the init register. The control logic sets the set of bits upon receipt of an initialization request. The control logic retrieves a Z value from either the init register or from the Z-buffer memory according to the states of the set of bits.

Abstract: Methods and apparatuses for dynamic virtual frame buffer management. At least one embodiment of the present invention dynamically enables or disables the use of a virtual frame buffer, which is not under control of graphics hardware of a data processing system, without restarting the graphical user interface system (e.g., the window system) of the data processing system. For example, in response to the addition or removing of a frame buffer that is under control of a graphics controller (e.g., due to the activation or deactivation of the graphics controller, or the hot plug-in or hot disconnection of the graphics controller), the virtual frame buffer is disabled or enabled respectively.

Abstract: A system which utilizes the processing capabilities of the graphics processing unit (GPU) in the graphics controller. Each frame of each video stream or track is decoded into a buffer and a color profile indicating parameters of the color space of the video source is associated with the buffer. The compositor uses the color profile to convert each buffer to a defined working color space from the source color space. This conversion and rendering of the buffer is performed using the fragment processing capabilities of the GPU. The compositor then instructs the GPU to convert the buffer to the final color space of the display device and the frame is rendered to the frame buffer for final display. Each of these operations is done in real time for each frame of the video.

Abstract: A secondary frame buffer is provided for use by classic applications designed to paint directly to a frame buffer. Classic applications paint their windows to the secondary frame buffer, not to the primary frame buffer. A compositor reads window data from the secondary frame buffer and paints it to the primary frame buffer. The compositor also reads window data written to back buffers by other applications and paints that data to the primary frame buffer. Since the compositor maintains visible region data for all windows, the windows are correctly painted to the primary frame buffer whether they are from the back-buffered windows or from classic applications. In addition, optimizations in classic applications that cause classic windows to be inappropriately painted over newer style windows no longer have this effect, since the compositor is responsible for painting legacy windows to the frame buffer, not the applications themselves.

Abstract: A system for processing graphics data for a stream of graphics primitives, such as triangles. The system has a plurality of memories each for storing an index of the primitive. A controller selects a memory to store the index and assigns a thread id to the index, the thread id indicating in which memory the index is stored. The thread id is stored in both a HEAD ID FIFO and a DATA ID FIFO, to maintain the order of the primitives during processing. A first multiplexer accesses a selected memory based on a thread id provided by the HEAD ID FIFO and a second multiplexer accesses a selected memory based on a thread id provided by the DATA ID FIFO. For each of the vertices of the graphics primitive, the first multiplexer provides a pointer for accessing coordinate information and the second multiplexer provides a pointer for accessing attribute information.

Abstract: A video and graphics system includes a video decoding system for processing compressed video data. The compressed video data includes MPEG-2 video data containing SDTV video data or HDTV video data. The video decoding system includes a video decoder for processing the compressed video data to generate displayable video, and a memory controller for transferring the compressed video data to and from an external memory. The video decoder requests to the memory controller to transfer the compressed video data using one of predetermined addressing patterns. The predetermined addressing patterns allow for more efficient transferring of the compressed video data to and from the external memory when compared to sequentially transferring a fixed number of data bytes starting at a fixed address. The use of the predetermined addressing patterns results in reading the compressed video data from the external memory in a predetermined order in a less number of clock cycles.

Abstract: An image processing device comprises a decoder, a sprite buffer interface, and a sprite buffer as well as a rendering engine, a frame buffer interface, and a frame buffer, which is characterized by synchronizing the write timing for the sprite buffer with the read timing for the frame buffer. That is, the decoder decodes compressed image data to restore original image data before compression. The sprite buffer interface writes the decoded data (i.e., sprite pattern data) into the sprite buffer, from which the sprite pattern data are read and supplied to the rendering engine. The rendering engine performs a prescribed rendering process (e.g., magnification, reduction, rotation, deformation, etc.) on the sprite pattern data, which are then written into the frame buffer. A display controller reads rendering-completed data (i.e., display data) from the frame buffer so as to output them to a display.

Abstract: A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients. A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory.

Abstract: Disclosed is a system and method for processing graphic operations on a plurality of data structures of an image with a graphics processing unit and memory. The disclosed techniques of the system and method create an accumulation buffer of the data structures for accumulating changes to the data structures. A separate buffer is then created from at least a portion of the data structures of the accumulation buffer. The disclosed techniques read the data structures from the separate buffer with the graphics processing unit. The graphics processing unit operates on the data structures read from the separate buffer with the operation. Then, the disclosed techniques write the results of the operation onto the portion of the accumulation buffer corresponding to the separate buffer.

Abstract: A video decoder organizes and stores pixel lines of a reference picture into first and second memory devices. The video decoder then reads portions of a pixel block from the first and second memory devices and processes such a pixel block for generating a subsequent picture. By reading from the first and second memory device with time overlap, latency is minimized for faster video decoding.

Abstract: The invention relates to a display apparatus and related method thereof capable of preventing firmware updating failure. The display apparatus includes a first memory block for storing a first firmware; a second memory block for storing a second firmware; and a micro controller unit coupled to the first memory block and the second memory block for accessing and executing the first firmware or the second firmware to control the operation of the display apparatus.