Abstract: A data buffering apparatus comprises a plurality of sessions and buffer logic. The plurality of session are respectively associated with session identifiers. Each of the sessions is configured to identify entries in a queue having the session's associated identifier and to pull, from the queue, the identified entries. Each of the sessions is further configured to retrieve data from the buffers pointed to by the identified entries that have the session's associated identifier. The buffer logic is configured to store a set of data to one of a plurality of buffers. The buffer logic is further configured to store, in the queue, for each expected retrieval of the set of data from the one buffer by the sessions, an entry that points to the one buffer and has a different session identifier associated with a different one of the sessions.

Abstract: Tile buffers in a graphics processing system are managed use “copy-on-write” semantics, in which tile data stored in a memory location is not transferred to another location until the tile data for one of the buffers is modified. Two memory spaces store tile data, and two logical buffers are used to access the memory spaces. For each tile, a tile association is maintained, indicating which of the two memory spaces is associated with each of the two logical buffers. To copy a tile of the first logical buffer to the second logical buffer, the tile association for the tile being copied is modified. Data for a tile is written to the memory space associated with a target logical buffer after ensuring that the tile association for the tile associates the target logical buffer with a different one of the two memory spaces from the other logical buffer.

Abstract: Tile data for drawing and desktop buffers in a desktop compositor system is managed using “copy-on-write” semantics, in which tile data stored in a memory location is not transferred to another location until the tile data for one of the buffers is modified. For each tile in drawing buffers and desktop buffers, an association is maintained with a location in a tile memory, and the number of buffer tiles associated with each location is tracked. To copy a tile from one buffer to another, the tile association for the tile in the destination buffer is modified. New data for a tile of a buffer is written to the tile memory location associated with the buffer after ensuring that the tile memory location is not associated with any other tiles of any of the buffers. As a result, memory bandwidth can be considerably reduced.

Abstract: Image display apparatus and image display method which realize smooth scroll-display of image data and enlargement/reduction display, and attain cost reduction by reducing the capacity of local memory for temporarily storing image data. In the image display apparatus, compressed image data is stored in an image memory 52, and partial image data of the compressed image data within a display range of monitor screen 56 and its peripheral compressed image data are transferred to a local image memory 59. in the local image memory 59, the partial image data and the peripheral image data are expanded and stored. Further, compressed image data further surrounding these data is stored. Then, compressed image data in a designated scroll direction is expanded by an image expansion unit 60.

Abstract: An image display device comprises a first storage device (4) for storing an image data, an image processor (8) for reducing the number of bits of the image data, a second storage device (10) for storing the image data after being processed, a display device (12) for displaying the image data after being processed, a driver (14) for driving the display device (12) and a controller (16) for controlling the operation of the driver (14). The controller (16) determines whether the image data stored in the first storage device (4) is dynamic or static, and, in the case of a static image, after storing the signals corresponding to one frame of the image data in the second storage device (10), operates only the second storage device (10), the driver (14) and the display device (12). Thereby, reduction of power consumption can be achieved while maintaining high image quality.

Abstract: A sliding window (block) system incorporating a methodology for providing a processor access to image data is described. In an exemplary embodiment, the system operates as follows. An image is received for processing that has a size that is too large for the processor to access directly. As a result, the sliding window system creates first, second, and third swappable windows (blocks) for accessing image data from the image; each windows is swappable so that any two are available within the memory space of the processor while a third is being loaded in a background memory. The system cycles through the three windows such that, at any given point in time, two of the three windows are affixed in the memory space of the processor as left and right adjacent windows, while the remaining or third window is being loaded in the background (e.g., in a DRAM) as a temporary shadow or background window. After the shadow window is loaded with appropriate image data, it is brought into the foreground (i.e.

Abstract: A display control apparatus contains a video memory, a video memory controller, a color palette memory and a color palette replacer signal generator. The video memory stores display data that are read from a CD-ROM and contain header data (HA-HD), palette data (P0-P2) and bitmap data (BA-BD) in connection with four planes which are combined together to form one frame of picture. The header data contain a color palette pointer (CPP) and a color palette replacer instruction (CPP31) with respect to each of the planes. The video memory controller reads the palette data and bitmap data from the video memory in accordance with addresses designated by the header data. The color palette replacer signal generator generates a color palette replacer signal (COL) based on the header data so as to make determination whether to replace contents of color palettes with respect to the planes respectively.

Abstract: A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A time allocator arbitrates the concurrent use of the graphics-rendering engine between each independent image being rendered.

Abstract: A method and a system for stalling large pipelined designs. A computational pipeline may comprise a first module and a second module coupled together. The first module may propagate one or more signals to the second module. A stall-signal may be asserted in order to stall the computational pipeline if the second module is not ready to receive the one or more signals from the first module. The one or more signals propagated from the first module and the asserted stall-signal may be buffered in a stall-buffer. The asserted stall-signal may be propagated to the first module in a next cycle. The first module may be stalled in response to the first module receiving the propagated asserted stall-signal. Next, the asserted stall-signal may be propagated up the computational pipeline.

Abstract: An input digital video signal is allotted by a first multiplexer (310) between regions of a display area to be driven in a dividing manner and is sequentially input to a first memory portion (30A) or a second memory portion (30B). Each of the first and second memory portions (30A and 30B) comprises an input-side line memory (32) composed of, for example, 400-stage input side shift register to which said digital video signal is sequentially input, and an output-side line memory (34) for receiving the data transferred in parallel from the input line memory (32) to serially output the stored data from a selected one of output portions (Out1-4) provided at the 320th, 256th or first stage FF34. The output portion of the memory (34) is thus selected by selectors (380A, 380B) in accordance with the number of pixels in the horizontal direction of the LCD panel, such that LCD panels having the different numbers of pixels can be driven with the same structure.

Abstract: A data table includes a source pointer indicating a starting address of drawing data, a destination pointer indicating a destination of drawing data to be transferred, and a data length indicating a data length of drawing data to be transferred. Data table may indicate drawing data to be drawn. Thus frames may share drawing data. As such the amount of drawing data can be reduced.

Abstract: Methods and apparatus for implementing a pixel page system providing swapped pixel pages for use with a GLV (grating light valve).

Abstract: A system and method are disclosed for rendering polygons. In some embodiments, parameter values may be rendered for only one sample position of multiple neighboring sample positions. The parameter values rendered for the one sample position may then be stored in multiple memory locations that correspond to the multiple neighboring sample positions. In some embodiments, storing parameter values in multiple memory locations may be achieved in a single write transaction. In some embodiments, utilization of a method for storage of a rendered sample to multiple memory locations may be subject to a specified test. The method may calculate a value needed for the specified test from vertex data and compare the calculated value with a specified limit. In some embodiments, a multiple storage mode may only be utilized for polygons greater than a certain size.

Abstract: A CPU of an image display apparatus transmits user manipulation to an input unit to a wireless unit of a data processing apparatus through a wireless unit, and a CPU of the data processing apparatus processes corresponding to the user manipulation. The CPU of the data processing apparatus generates image data, and transmits to the wireless unit of the image display apparatus through its own wireless unit, and the CPU of the image display apparatus displays this image data in its display unit. Accordingly, the information processing system divided into the data processing apparatus and image display apparatus, and capable of carrying easily the image display apparatus can be presented.

Abstract: A method of correcting a video signal includes retrieving a correction data from a respective one multiple memory devices; reordering the correction data to a predetermined order for a particular segment; and interpolating multiple correction data so that all pixels in the particular segment have a corresponding one of the correction data. An apparatus for correcting video comprises multiple memory devices, each having multiple correction data; a cross-bar switch that reorders at least some of the data to a predetermined order for a particular segment; and an interpolator that calculates multiple interpolated correction data. One of the correction data corresponds to one of multiple pixels in the segment.

Abstract: A feedback path to the processor for a video signal in a computer. The video image data is not normally subjected to benchmark testing because it would make it susceptible to illegal copying. The digital video output signal is sent back to the processor one pixel at a time, with a delay between pixels equivalent to one line time. The result is that the pixel feed is so slow that digital copying is impractical. A lockout timer allows the pixel data to be sent to the processor only at intervals.

Abstract: In accordance with a specific implementation of the present invention, the control portion of a graphics processor receives a command having both a data portion and a data duration portion. When the data duration portion indicates the data is transient data for short-term use, the control portion stores the data associated with the data portion at the first memory partition. When the data duration portion indicates the data is persistent data for long-term use, the control portion stores the data associated with the data portion at a second memory partition. In a multiple processor system, transient data may be stored only in a memory partition associated with a first processor, while persistent data may be stored in multiple memory partitions, one for each graphics processor.

Abstract: Methods and apparatus for implementing a pixel page system providing swapped pixel pages for use with a GLV (grating light valve).

Abstract: An effective structure of a pixel cache for use in a three-dimensional (3D) graphics accelerator is provided. The pixel cache includes a z-data storage unit that reads z-data from a frame memory and provides the read z-data to a pixel rasterization pipeline; and a color data storage unit that in advance reads and stores color data from the frame memory at the same time when the z-data storage unit reads the z-data from the frame memory, and provides the color data to the pixel rasterization pipeline only when the result of predetermined z-test is determined to be a success in the pixel rasterization pipeline. Accordingly, the pixel cache structure enables only color data required to be read and stored in advance before processing of the color data, thereby preventing access latency, increasing the efficiency of a color cache, and reducing power consumption.

Abstract: An image processing apparatus has interpolation calculation means which outputs, based on an input image signal P7, a binary signal P8=0 or 1 by calculating a formula, P8=S[i](xl,yl) EXOR (DF(xl,yl) AND IP(xl,yl)), using a screen pattern S[i](xl,yl), a difference pattern DF(xla,yla) based on screen patterns S[i] and S[i+1], and an interpolation pattern IP(xla,yla).

Abstract: An object of the present invention is to provide a display device in which a frame frequency does not decrease even in the case of employing a method for driving having little difference between reading time of a memory and writing time of a memory. According to the present invention, a reading device and a writing device are synchronized by determining allotment of two memories every cycle of a writing signal and by determining a start of reading through a start signal for writing and horizontal synchronizing signals.

Abstract: A graphics system and method for processing geometry compressed, three-dimensional graphics data are disclosed. After transforming and lighting each vertex, a vertex data stream is decompressed using connectivity information, and vertexes are reassembled into geometric primitives. The connectivity information may include mesh buffer references, vertex tags, or other types of information. Independent buffers, queues, and/or caches are used to simultaneously store: (a) vertex data for the next several primitives, (b) vertex data that will be reused, (c) vertex tags, (d) control tags, (e) vertex data being assembled into a primitive, and (f) an assembled primitive ready to be launched. The assembled primitive may be clip tested for visibility in a defined viewport, before investing time to have the primitive processed into pixel data for display. The independent buffers, queues, and/or caches may also enable the vertex processing steps to be performed in parallel and at different rates.

Abstract: Systems and methods are disclosed for providing interactive displays of complex virtual environments. Systems and methods consistent with embodiments of the invention may be implemented to generate virtual reality (VR) file(s) from a 3D model of the complex environment. The VR file(s) may include octree and collision detection information that is used to simulate and render frames of the complex environment. During simulation, moving objects may be evaluated to detect for collisions with other objects. Further, during rendering, objects or elements may be dynamically tessellated during run-time operations to actively control their appearance when displayed to a user. Memory management operations for facilitating the display of complex virtual environments are also disclosed, consistent with embodiments of the invention.

Abstract: The image formation apparatus comprises a plurality of hard disk drives which store image data and a hard disk drive array control integrated circuit which controls reading/writing of image data from/into the hard disk drives. The hard disk drive array control integrated circuit executes setting of parameters, issuance of commands, and reading of statuses for all the hard disk drives substantially at the same time, divides the image data into pieces, and executes direct memory access transfer of the pieces of the image data to the hard disk drives substantially at the same time.

Abstract: Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer.

Abstract: In a method and apparatus for displaying data on a video display that is controlled by a video controller, the video controller is coupled to a high-speed memory and a low-speed memory. The memories have separate data paths. A video address corresponding to a location on the video display is received. If a specified address bit is in a first state, then data is displayed from the high-speed memory. If the specified address bit is in a second state, then data is displayed from the low-speed memory. The specified address bit may be a high order address bit that is not utilized by a conventional VGA controller to transmit address information.

Abstract: Systems and methods for managing window transparency for a computer display, making windows wholly transparent or semi-transparent, on a window-by-window basis. Window transparency is triggered by monitoring messages exchanged between a program and an operating system, or by a user action. Upon detection of a first message indicating that a window of the display should be transparent, a layered display mode for the window is initiated. Upon detection of a second message indicating that the window should no longer be transparent, the layered display mode for the window is terminated. The layered mode can be controlled by the operating system or by a graphics processor.

Abstract: Tile data for drawing and desktop buffers in a desktop compositor system is managed using “copy-on-write” semantics, in which tile data stored in a memory location is not transferred to another location until the tile data for one of the buffers is modified. For each tile in drawing buffers and desktop buffers, an association is maintained with a location in a tile memory, and the number of buffer tiles associated with each location is tracked. To copy a tile from one buffer to another, the tile association for the tile in the destination buffer is modified. New data for a tile of a buffer is written to the tile memory location associated with the buffer after ensuring that the tile memory location is not associated with any other tiles of any of the buffers. As a result, memory bandwidth can be considerably reduced.

Abstract: A microprocessor for processing a large quantity of graphics data. The microprocessor independent of a CPU has two ports, and performs an instruction fetch and a data access or a memory access simultaneously to two memories mounted on separate buses. A graphics processing apparatus provided by the microprocessor transfers graphics data between a system memory and a frame memory at high speeds.

Abstract: A liquid crystal driving device of the present invention is provided with a display data memory of a capacity that can be divided into two parts, and a switch circuit that is used to switch an addressing method of the display data memory between multi-tone display in a dual-scan and simple-tone display in a single-scan, so as to enable a driving IC to be shared between liquid crystal display devices that are used to display high-quality and multi-tone images and liquid crystal display devices that require less tone. Such a liquid crystal driving device can be used to reduce production cost of various types of liquid crystal display devices.

Abstract: An on-screen display unit includes OSD (on-screen display) RAMs each for storing data on one of OSD blocks to be subjected to OSD; a memory bus for transferring data to be stored to the OSD RAMs from a CPU; and an OSD local bus for transferring the data stored in the OSD RAMs to make the OSD. The OSD RAMs are supplied with the data to be stored through the control of switches alternately, and transfer the stored data to the OSD local bus 12 alternately. The on-screen display unit can cope with a high frequency OSD clock signal, and carry out the OSD normally.

Abstract: By using an dictionary for non-disclosure which manages non-disclosure character strings and non-disclosure reasons, and a forced disclosing dictionary for managing forcedly the disclosed character strings and forcedly disclosing reasons, disclosing tags, disclosing reasons, non-disclosure tags, reasons for disclosing, forcedly disclosing tags, and forcedly disclosing reasons are embedded in a document, and a character string assigned with an disclosing tag is replaced with a meaningless character string.

Abstract: A system and method for reordering data fragments to facilitate reads from a DDR SDRAM where the fragments are placed into a first and second data fragment buffer such that the data fragments are in sequential addresses whereby the second data read on the trailing edge of the clock cycle will read the proper data fragment.

Abstract: Methods and apparatus for implementing a pixel page system providing pixel pages using combined addressing. In alternative implementations, the system stores and retrieves data other than pixel data.

Abstract: The present invention can be introduced to an architecture such as a personal computer or an amusement equipment for realizing a high-speed graphic processing. In the case where a frame buffer, a command memory and an image processor are integrated in one chip in order to improve the drawing performance of an image processing device, each of the frame buffer and the command memory is constructed by a plurality of identical memory modules and the same row address is allotted to each memory module, thereby increasing the memory address depth. Thereby, it is possible to realize an incorporated frame buffer and an incorporated command memory each of which has a large capacity when seen from the image processor.

Abstract: An apparatus and method for storing image data comprising a first storage device and a second storage device. The first storage device may be configured to store at least one first pixel from a first field of a frame of the image at a first physical address in the first storage device. The second storage device may be configured to store a second pixel from a second field of the frame of the image at a second physical address in the second storage device. The first and second physical addresses may have the same relative position in an address space of the respective storage devices.

Abstract: Disclosed are an image data processing method and apparatus for reading image data out of a memory and processing the image data, in which the memory stores image data representing an image as a collection of a plurality of partial images and from which the image data can be read out upon specifying image data in units of the partial images. If sequence information indicating the display sequence of the plurality of partial images of the image is stored in association with the image, then the partial images can be read out and displayed in accordance with the sequence information. By displaying completed partial images upon appending specific information thereto, it is possible to distinguish partial images whose display has been completed on a screen from partial images whose display has not been completed on the screen.

Abstract: A system for rendering graphical data utilizes a plurality of frame buffers, a plurality of graphics pipelines, a compositor, and logic. The plurality of graphics pipelines are configured to receive graphics commands and to render graphical data to each of the plurality of frame buffers based on the received graphics commands. The compositor is configured to receive a control signal and to interface the graphical data with a display device based on the control signal. The logic is configured to analyze the graphics commands and to make a determination, based on the graphics commands, as to which pixels defined by the graphical data are associated with three-dimensional (3D) regions. The logic is further configured to transmit the control signal to the compositor, wherein the control signal is based on the determination.

Abstract: An image processing apparatus is composed of a plurality of function processing units for performing image processing, a high priority function selection part for selecting functions, execution of each of which is required by a corresponding one of the function processing units, based on the predetermined priority for each of the functions; and a data control unit including a data transfer part for preferentially accessing the shared memory which the function selected by the high priority function selection part requires, and a plurality of data holding parts, each of the data holding parts holding a predetermined amount of data transmitted with each of the plurality of function processing units, wherein the data transfer part controls the bus connecting the CPU and the shared memory based on requirement sent from each of the function processing units, and each of the plurality of function processing units transmits data with the data control unit separately from the others of the plurality of function proces

Abstract: The present invention relates generally to an optimized memory architecture for computer systems and, more particularly, to integrated circuits that implement a memory subsystem that is comprised of internal memory and control for external memory. The invention includes one or more shared high-bandwidth memory subsystems, each coupled over a plurality of buses to a display subsystem, a central processing unit (CPU) subsystem, input/output (I/O) buses and other controllers. Additional buffers and multiplexers are used for the subsystems to further optimize system performance.

Abstract: An overlay frame processing method and device are used for showing a display frame and an overlay frame outputted by a digital image processing device on a display. The display frame and the overlay frame respectively consist of display frame pixel data and overlay frame pixel data at corresponding positions. A display controller and an overlay engine read and transmit the display frame pixel data and the overlay frame pixel data out, respectively. An alpha-blending engine receives and performs an alpha-blending operation on the display frame pixel data and the overlay frame pixel data to obtain an alpha-blended pixel data. A digital-to-analog converter converts the alpha-blended pixel data into an analog signal and transmits the analog signal to the display to be displayed.

Abstract: A method for caching graphics-related data in one or more graphics request buffers wherein duplicative graphics-related data is not written to the graphics request buffers. In the preferred method the graphics-related data is sent in frames, and each frame contains frame setup data and graphical model data, and the model data is compared between the stored frame and the new frame to determine if there is new model data to be written to the graphics request buffers.

Abstract: An object of the invention is to provide an image memory system capable of efficiently reading out image data also in case of consecutively reading out image data from an image memory along a direction other than the direction in which a burst access can be performed. In case that a bit-map image is partitioned into square or rectangular blocks and image data of pixels contained in one block are made to correspond to one row space, row spaces respectively corresponding to two blocks being adjacent to each other with a common side between them are made to belong to different synchronous DRAMs without fail and all of row spaces respectively corresponding to four blocks having commonly one vertex are made to belong to different banks.

Abstract: A graphics processing system performs filtering of oversampled data during a scanout operation. Sample values are read from an oversampled frame buffer and filtered during scanout; the filtered color values (one per pixel) are provided to a display device without an intervening step of storing the filtered data in a frame buffer. In one embodiment, the filtering circuit includes a memory interface configured to read data values corresponding to sample points from a frame buffer containing the oversampled data; and a filter configured to receive the data values provided by the memory interface, to compute a pixel value from the data values, and to transmit the pixel value for displaying by a display device, wherein the filter computes the pixel value during a scanout operation.

Abstract: The monitor system comprises the display device which has a screen having a display area virtually divided into a plurality of sub-screens. Provided are graphics adapters, each of which has two frame buffers, so as to correspond to the sub-screens of the display device.

Abstract: A memory management circuit manages frame data for a display system such as used in a projection television system or cellular phone. The frame data includes frames corresponding to a series of images for viewing by a user. The memory manager includes an input buffer to receive the frame data, a memory interface coupled to receive the frame data from the input buffer, and an output buffer coupled to receive the frame data from the memory interface and output the frame data to a display such as a liquid crystal (LCD) micro-display. The memory interface sends and receives the frame data as packets, with each packet having a size less than a full frame, to and from an external memory able to store at least one full frame of data.

Abstract: The present invention includes pluralities of memory card slots incorporated therein for connecting various types of memory card and reading the information therein. At least one transmission interface port is used to connect the means that provides the function to store and provide the digital image. A power source is used to provide the power and a signal process controller is used to process the input image. A display is used to display the image and a display module is coupled to the signal process controller to send the signal processed by the signal process controller to the display.

Abstract: A method and apparatus for implementing a dynamic display memory is provided. A memory control hub suitable for interposition between a central processor and a memory includes a graphics memory control component. The graphics memory control component determines whether operands accessed by the central processor are graphics operands. If so, the graphics memory control component transforms the virtual address supplied by the central processor to a system address suitable for use in locating the graphics operand in the memory. In one embodiment, the graphics control component maintains a graphics translation table in the memory and utilizes the graphics translation table in transforming virtual addresses to system addresses. Furthermore, in one embodiment, the graphics control component reorders the addresses of the graphics operands to optimize for performance memory accesses by a graphics device.

Abstract: A method for displaying color values in a plurality of images on a display screen in a computer graphics system, wherein the images correspond to a plurality of applications. The graphics system includes a primary frame buffer for pixel values to be displayed in the images, and a plurality of colormap tables related to the images for providing color values to be displayed in the images. A pseudo frame buffer is provided for the applications to store source pixel values for display in the corresponding images. To display the source pixel values in the pseudo frame buffer, for each source pixel the graphics system performs the steps of: identifying the image corresponding to the source pixel value; selecting a colormap table corresponding to the identified image; using the source pixel value as an index to select a color value from the selected colormap table; and storing the selected color value as a pixel value in the primary frame buffer to be displayed.

Abstract: A polygon rendering system for receiving geometric data defining a polygon in an image being generated. The polygon rendering system renders the geometric data as pixel data. The pixel data defines pixels used to display the image. The system comprises a first memory buffer for storing the pixel data. It also comprises a second memory buffer for storing additional pixel data used to render edge pixels at a higher resolution than pixels that are not the edge pixels. Edge pixels are pixels that are located on an edge of the polygon in the image. The system also comprises a display controller for outputting the pixel data in the first memory buffer to output circuitry. The polygon rendering system identifies which of the pixels are the edge pixels and the display controller updates contents of the first buffer with data based on contents of the second buffer.