Abstract: A method, system, and computer program product sends scene data to a geometry engine, wherein a processor generates scene data for a frame in accordance with an application program, and writes the scene data to a first memory location, known hereinafter as an intermediate buffer. Scene data for the next frame is then generated and written to a second intermediate buffer, while a geometry engine reads and renders the scene data in the first intermediate buffer. Scene data for the following frame is then generated and written to the first intermediate buffer, while a geometry engine reads and renders the scene data in the second intermediate buffer. The process continues in this manner until the application program is finished executing.

Abstract: A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. A reconfigurable graphics pipeline has a hidden surface removal stage that may be placed at different locations within the pipeline depending on pipeline rendering mode. When the pipeline operates in certain rendering modes, the hidden surface removal operation can be performed early in the pipeline—allowing the pipeline to avoid wasting its time imaging obstructed surfaces. For other (e.g., alpha based) rendering modes, the hidden surface removal operation is performed near the end of the pipeline—when the pipeline has developed sufficient additional information required by the particular rendering mode to resolve depth comparisons.

Abstract: By making it possible to freely change calculations of as well as variables that are input into the same calculation circuits, dedicated circuits corresponding to rendering functions become unnecessary, and in order to realize multi-functional rendering with circuitry of a small scale, a graphic image rendering apparatus includes a rendering information generation portion that generates rendering parameters corresponding to X and Y coordinates of pixels constituting a graphic image, a pixel calculation portion that, for each pixel, makes a selection as appropriate from the rendering parameters and a constant and performs a calculation, and a memory interface portion that writes a calculation result of the pixel calculation portion into a frame memory.

Abstract: A graphics drawing device capable of reducing the amount of information transferred. In the graphics drawing device for drawing graphics, a first storage circuit stores coordinate information and attribute information about a main graphic which is an original graphic. A second storage circuit stores coordinate information and attribute information about one or two or more derivative graphics derived from the main graphic. A drawing circuit draws the main and derivative graphics in accordance with the information stored in the first and second storage circuits, and a control circuit controls the drawing process performed by the drawing circuit.

Abstract: A format varying computing system including a computer linked to a display and input device, the computer including memory devices linked to a processing unit and a set of counters residing in the processing unit and linked to the memory devices, the set of counters defining a symbol residing in the memory devices.

Abstract: A graphics system may include a frame buffer, a processing device coupled to output data, a multipurpose memory device that includes a plurality of storage locations and is coupled to store data output from the processing device, and a multipurpose memory controller coupled to the multipurpose memory device. The multipurpose memory controller may be configured to allocate a first plurality of the storage locations to a first image buffer configured to store image data, a second plurality of the storage locations to a first texture buffer configured to store texture data, and a third plurality of the storage locations to a first accumulation buffer configured to store accumulation buffer data. The multipurpose memory device may be configured to include a first image buffer, a first texture buffer, and a first accumulation buffer at the same time.

Abstract: A reconfigurable system for performing a set of arithmetic operations. The reconfigurable system may have a frame buffer, an accumulation buffer and a pixel computation unit. The pixel computation unit includes a control unit and one or more copies of a reconfigurable circuit. The reconfigurable circuit may include a subtractor, a multiplier, an adder, and a set of multiplexors. The control logic drives selects lines of the set of multiplexors in the one or more circuit copies through one or more computational cycles in order to implement a programmable operation (such as scale and/or bias, accumulate, dynamic blend and matrix multiply). The pixel computation unit may receive pixels values from one or more sources including the frame buffer and the texture buffer, and operate on the pixels using the one or more circuit copies to generate a stream of output pixels.

Abstract: An image processing system comprises a plurality of memories to which image data is input, a control circuit for selecting areas for image processing from the image data input to the memories, and a plurality of DSPs connected to the memories and performing image processing of the selected image data selected by the control circuit.

Abstract: A system for rendering graphical data utilizes a plurality of graphics pipelines, a first process, and a second process. Each of the plurality of graphics pipelines is configured to render graphical data. The first process is configured to receive three-dimensional (3D) graphics commands from a graphics application and to receive input commands from a user input device. The first process is configured to buffer the received 3D graphics commands and to execute the received input commands, and the first process, for each of the buffered 3D graphics commands, is configured to begin processing a newly received command upon buffering the 3D graphics command. The second process is configured to interface the buffered graphics commands with each of the plurality of pipelines, wherein execution of the user input command affects an object defined by the graphics application.

Abstract: A system rendering graphical data from a graphics application utilizes a plurality of frame buffers, a plurality of graphics pipelines, and logic. Each of the graphics pipelines is configured to render graphical data to a different one of the frame buffers. The logic is configured to determine a mode of operation of the graphics application and to prevent, based on the mode of operation of the graphics application, at least one of the graphics pipelines from rendering the graphical data from the graphics application.

Abstract: A system for rendering graphical data utilizes a plurality of frame buffers, a plurality of graphics pipelines, a compositor, and logic. The plurality of graphics pipelines are configured to receive graphics commands and to render graphical data to each of the plurality of frame buffers based on the received graphics commands. The compositor is configured to receive a control signal and to interface the graphical data with a display device based on the control signal. The logic is configured to analyze the graphics commands and to make a determination, based on the graphics commands, as to which pixels defined by the graphical data are associated with three-dimensional (3D) regions. The logic is further configured to transmit the control signal to the compositor, wherein the control signal is based on the determination.

Abstract: A graphical display system utilizes a plurality of graphics pipelines, a compositor, and application interface logic. The plurality of graphics pipelines are configured to render graphical data in parallel. The compositor is configured to define a composite data signal that is based on the graphical data rendered by each of the pipelines. The application interface logic is configured to retrieve configuration data indicative of a configuration of the compositor. The application interface logic is further configured to provide the configuration data to a graphics application, wherein the graphics application is configured to provide graphical data to the plurality of pipelines based on the configuration data.

Abstract: A method of testing a plurality of registers in a RAMDAC, each of the registers having a plurality of bits. First, the bits of the registers are all reset to a first logic state. Then, one logic pattern is written to the registers so as to convert one bit of one of the registers into a second logic state and immediately read out. If the read logic pattern differs from the written logic pattern, an error message will be prompted. The steps are repeated until the testing of each of the bits of the registers is completed.

Abstract: An image processing apparatus capable of achieving an increase of capacity and consequently capable of achieving an improvement of processing capability without causing a drop in performance and an increase of the cost.

Abstract: An apparatus and a method for determining a type of DVI (Digital Visual Interface) connector connected to a digital video display device, wherein the apparatus utilizes a first resistor connected between a voltage source and a node; a second resistor connected between the node and a ground terminal; a DVI receptacle connected to the DVI connector, the DVI receptacle having a plurality of digital signal sockets connected to receive digital signals output from a host and a plurality of analog signal sockets connected to receive analog signals output from the host, the node being connected to a predetermined one of the analog signal sockets; and a controller connected to the node, the controller determining the DVI connector to be a DVI-D (digital only) type connector when a low voltage is detected at the node, and determining the DVI connector to be a DVI-I (digital and analog) type connector when a high voltage is detected at the node.

Abstract: A method for storing video data files upon an array of multiple storage devices on a frame-by-frame basis, with the larger video frames placed upon devices having more free storage capacity, so as to preserve the video data stream continuity, optimize the capacity of the storage devices within the array, minimize or negate the need for any redundant storage, and at the same time, provide a means for easily expanding the overall storage capacity of the array.

Abstract: According to one embodiment, a computer system includes a memory and a central processing unit (graphics accelerator) coupled to the memory. The graphics accelerator is adaptable to process three-dimensional (3D) graphics primitives stored in the memory according to an inline streaming mode and an indirect streaming mode.

Abstract: An on-screen display (OSD) processor, processing method and article of manufacture are provided having a color mapped mode, direct color mode, and 4:2:2 profile mode. The OSD processor implements both color mapped OSD region processing capability and direct color OSD region processing capability, along with an ability to store quantizer coefficients for the 4:2:2 profile mode of a video decoder coupled to the OSD processor. The capabilities of the OSD processor are implemented using a common embedded memory within the processor. During color mapped OSD region processing, color table data is temporarily stored within the embedded memory, while in direct color OSD region processing, direct color descriptions are stored within the embedded memory. When the video decoder is decoding a 4:2:2 formatted image, the embedded memory of the OSD processor is used to temporarily store inverse quantization data for the decode function.

Abstract: An object is to provide a serial access memory and a data write/read method applicable thereto and capable of reducing the test time of the serial access memory. After transferring the data stored in the memory cells MC11 to MCm1 connected with a word line WL1 to the read registers Rreg-1 to Rreg-m all at once, the data stored in the memory cells MC12 to MCm2 connected with a word line WL2 is transferred to the write registers Wreg-1 to Wreg-m all at once. The data stored in the read register is transmitted to an output means 123 through read data buses RD, /RD. The data stored in the write register is transmitted to the output means 123 through write data buses WD, /WD, an input/output means 122, and the second read data buses RD2, /RD2. The output means 123 compares the data transmitted from the read data buses RD, /RD with the data transmitted from second data buses RD2, /RD2.

Abstract: A stereoscopic display device includes a pair of OLED microdisplays in a Head Mounted Display. An emulation video signal is provided to the display device. The emulation video signal includes alternating frames of left and right video data. An enable signal is provided to the left and right displays to control when image data in the display is updated so as to update data with corresponding frame data of the emulation signal. The updating of data in the combined display is at the standard rate while the updating of data in each display is at half the standard rate.

Abstract: The object is to increase the efficiency of processing by conferring the residual image function on hardware and to provide an image processing device wherein processing is implemented at higher speed. In an image processing device equipped with an image memory and a control section that writes generated image data to the image memory, there is provided a blend circuit that reads image memory or image data from image memory and attenuates the read image data and that writes this together with newly generated image data into another image memory, thereby producing a residual image effect.

Abstract: The object of the present invention is to provide an image display apparatus suited to display a video program or the like for advertisement purposes. The image display apparatus comprises a storage medium installation section (11), a memory section (13) storing image data read out from a storage medium (1) installed into the storage medium installation section (11), a display section (16) displaying the image data stored in the memory section (13) and a control section (19) for repeatedly executing display of the image data stored in the memory section (13) at the display section (16).

Abstract: The invention relates to a method for infecting equines with an equine infectious anemia virus (EIAV) in order to reproduce a natural infection challenge model. More specifically, the invention provides a multiple low dose equine EIA challenge model comprising administering at least 1 median horse infective dose to an equine using an intravenous route of administration. It is preferable that the EIAV be administered on a repeated basis. The multiple low dose EIA challenge model described herein can be used for testing efficacy of vaccines, treatments and diagnostic tests.

Abstract: A method and apparatus are provided for a lighting system for graphics processing. Included is a plurality of input buffers adapted for being coupled to a transform system for receiving vertex data therefrom. The input buffers include a first input buffer, a second input buffer and a third input buffer. An input of the first buffer, the second input buffer and the third input buffer are coupled to an output of the transform system. Further included is a multiplication logic unit having a first input coupled to an output of the first input buffer and a second input coupled to an output of the second input buffer. An arithmetic logic unit has a first input coupled to an output of the second input buffer. The arithmetic logic unit further has a second input coupled to an output of the multiplication logic unit. An output of the arithmetic logic unit is coupled to the output of the lighting system.

Abstract: The present invention can be introduced to an architecture such as a personal computer or an amusement equipment for realizing a high-speed graphic processing. In the case where a frame buffer, a command memory and an image processor are integrated in one chip in order to improve the drawing performance of an image processing device, each of the frame buffer and the command memory is constructed by a plurality of identical memory modules and the same row address is allotted to each memory module, thereby increasing the memory address depth. Thereby, it is possible to realize an incorporated frame buffer and an incorporated command memory each of which has a large capacity when seen from the image processor.

Abstract: An image processing apparatus which can effectively use a storage circuit provided together with a logic circuit, perform high speed processing, and reduce the power consumption without causing a decline in the performance. The image processing system includes a DRAM for storing image data and a logic circuit, which are provided together on a semiconductor chip. The DRAM is divided into a plurality of DRAM modules, and the divided plurality of DRAM modules are arranged around a logic circuit portion for carrying out graphic drawing processing etc. When the ratio of valid data occupying bit lines in one access increases, the distances from the DRAM modules to the logic circuit portion become uniform, the length of the longest path interconnection can be made shorter comparing with the case of arrangement fixed in one direction, and the overall operating speed can be improved.

Abstract: An image display device comprises a first storage device (4) for storing an image data, an image processor (8) for reducing the number of bits of the image data, a second storage device (10) for storing the image data after being processed, a display device (12) for displaying the image data after being processed, a driver (14) for driving the display device (12) and a controller (16) for controlling the operation of the driver (14). The controller (16) determines whether the image data stored in the first storage device (4) is dynamic or static, and, in the case of a static image, after storing the signals corresponding to one frame of the image data in the second storage device (10), operates only the second storage device (10), the driver (14) and the display device (12). Thereby, reduction of power consumption can be achieved while maintaining high image quality.

Abstract: An apparatus for displaying a polygon on a horizontal scan display device having a plurality of pixels includes first and second rasterizers that each process respective first and second sets of pixels. Each set of pixels includes vertical stripes that are transverse to the horizontal scan of the display. To that end, the first rasterizer has an input for receiving polygon data relating to the polygon. The first rasterizer determines a first set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the first set of pixels. In a similar manner, the second rasterizer also includes an input for receiving polygon data relating to the polygon. The second rasterizer similarly determines a second set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the second set of pixels.

Abstract: The Shadow Buffer method can be characterized as control of multiple reusable parallel buffers that have utility in mapping digital transformations to improve formation of composite images for single displays or multiple projected images. This method can be described analogously as innovative extensions to current software and hardware solutions that use multiple allocation of pixel memory space to color, alpha and Z-depth functions. The Shadow Buffers are additional pixel and sub-pixel memory maps of screen space and projector attributes (e.g., gamma, contrast, intensity, color, position, stretching, warping, soft-edge blending) that improve the final overall composite image.

Abstract: A graphic interface device produces a video signal for a display such that the user may select between landscape and portrait image display modes. The graphic interface device has a pixel data memory array from which a video output signal is derived. A primary graphics engine renders graphics in a landscape orientation in conjunction with a frame buffer. The primary landscape graphics engine stores rendered graphics to the pixel data memory array and also copies selected graphics in data blocks within the frame buffer called surfaces. In order to provide other display modes to display images in different physical orientations, a mode control is provided in conjunction with a rotated pixel data array buffer to facilitate the rendering of portrait oriented graphics by the primary landscape graphics engine. In addition, to facilitate the efficiency and speed of rendering portrait oriented graphics, a secondary portrait graphics engine is provided.

Abstract: A decoding section 111 decodes inputted coded data to image data and outputs it to an image data writing section 112 whenever necessary. The decoding section 111 outputs a decode completion notice signal to an image data reading section 114 and control signal generating section 115 every time when outputting a predetermined amount of image data (for example, an amount corresponding to one frame). The image data writing section 112 writes image data to the storing section 113 whenever necessary. An image data reading section 114 operates intermittently with timing when the decode completion notice signal is input thereto, and reads a predetermined amount of image data from the storage section 113. The control signal generating section 115 generates a control signal 206 that instructs a new portion in image data decoded by decoding means.

Abstract: A graphics controller which performs display list-based video refresh operations that enable objects with independent frame rates to be efficiently assembled is disclosed. The graphics controller maintains a virtual display refresh list (VDRL) comprising a plurality of pointers to scan line segments in memory. The graphics controller also creates, maintains, and deletes draw display lists (DDLs) that comprise pointers to object display list subroutines (ODLs) that independently draw objects in memory. The ODLs may allocated one or more buffers in memory into which different frames of the objects are drawn. When an ODL has completed executing, the corresponding pointer in the DDL may be updated to point to the buffer location in memory that stores the newly completed object frame. The VDRL is maintained independently (and may be doubled-buffered) and is updated using the DDLs.

Abstract: A system is described that is broadly directed to a system of integrated circuit components. The system comprises a plurality of nodes that are interconnected by communication links. A random access memory (RAM) is connected to each node. At least one functional unit is integrated into each node, and each functional unit is configured to carry out a predetermined processing function. Finally, each RAM includes a coherency mechanism configured to permit only read access to the RAM by other nodes, the coherency mechanism further configured to permit write access to the RAM only by functional units that are local to the node.

Abstract: A method and apparatus for storing data for a plurality of data blocks in a compressed format in memory is presented where the compression scheme used for compressing the data blocks may vary. For each data block included in the plurality of data blocks, the data block is compressed using a compression scheme that is included in a set of predetermined compression schemes. The resulting compressed data set is of a size included in a set of predetermined sizes that correspond to the particular compression scheme utilized. The compressed data set for each block is then stored in a compressed data set memory, where the compressed data sets are stored in groups. A descriptor data set corresponding to each group is then stored in a descriptor memory, where the descriptor data set includes an encoded compression descriptor for each data block included in the group. The data descriptor set also stores a base address that corresponds to a starting location for that group in the compressed data set memory.

Abstract: A method of extracting data for use in an interactive computer graphical environment. The graphical environment is generated by a computer responsive to software residing on a first removable memory having a predetermined data format. The method includes the steps of randomly selecting a second memory having a substantially similar data format to the predetermined data format; reading data signals from the selected second memory indicative of the content thereon; and processing the read data signals to represent parameter content in the graphical environment.

Abstract: This disclosure provides a system for efficiently processing a data set. More particularly, image data such as volumetric data are stored in a spread memory fashion, with image data subsets occupying only a fraction of each page. Each memory page is sized to roughly map to processor cache size (or a section thereof), such that image data is always mapped to one or more predetermined fractions of processor cache. By keeping processing parameters (e.g., look-up tables and buffers) in the remainder of cache, the system effectively locks those parameters against overwrite by the image data. This system facilitates the use of conventional workstations, laptops and other machines not enhanced for processing large or complicated data sets. It also extends capabilities of both un-enhanced and enhance machines, permitting them to process data more efficiently.

Abstract: A graphics display system has a graphics processor system for forming a color image on a display, the display being composed of an array of pixels. A memory system has a first memory for storing at least respective color data and respective Z data that is render from primitives of the image, and a second memory for storing respective display data, derived from the rendered color data and Z data, for each of the pixels. The graphics processor system has a memory interface operatively connected to the first and second memories. During formation of an image frame, the memory interface writes to and reads from a Z buffer, and only writes to a render target color buffer. After the image is rendered, image data is copied from the first memory to the second memory from which the image is displayed.

Abstract: Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels for one frame is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. While data is being stored, data for pixels from another frame is retrieved from another two memory devices. The banks of devices alternate between storing and retrieving with each frame.

Abstract: Methods and apparatus for storing and retrieving data. In one implementation, a system includes: a data source, providing data in a first order; a data destination, receiving data in a second order; memory devices having memory pages, data stored in parallel and retrieved in parallel; each buffer page having entries along a first dimension corresponding to the first order and entries along a second dimension corresponding to the second order, data stored according to the first order using blocks of buffer pages, each block having a number of pages equal to a power of 2, data stored in the first order and retrieved in the second order, at least one memory page stores data in multiple locations according to the first and second orders, data elements consecutive in the first order are stored in parallel, data elements consecutive in the second order are retrieved in parallel.

Abstract: Methods and apparatus for storing data using two-dimensional arrays mapped to memory locations.

Abstract: Methods and apparatus for adjusting the geometry of buffer pages.

Abstract: Methods and apparatus for storing and retrieving data using two-dimensional arrays. In one implementation, a checkerboard buffer page system includes: a data source, providing data elements in a first order; a data destination, receiving data elements in a second order; memory devices each having memory pages, data elements stored in parallel to and retrieved in parallel from the memory devices; each buffer page having entries along a first dimension corresponding to the first order and entries along a second dimension corresponding to the second order, data elements stored in the first order and retrieved in the second order, at least one memory page stores data elements in multiple locations according to the first and second orders, at least two data elements consecutive in the first order stored in parallel, and where at least two data elements consecutive in the second order retrieved in parallel.

Abstract: Methods and apparatus for storing and retrieving data. In one implementation, a system includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least four memories, each having memory pages, data stored to at least two memories and retrieved from at least two memories in parallel, each buffer page having entries along a first dimension corresponding to the first order and entries along a second dimension corresponding to the second order, data stored in the first order and retrieved in the second order, at least one memory page stores data in multiple locations according to the first and second orders, two data elements consecutive in the first order stored in parallel to the memories, at least two data elements consecutive in the second order retrieved in parallel from the memories.

Abstract: Methods and apparatus for storing and retrieving data using two-dimensional arrays. In one implementation, a checkerboard buffer page system includes: a data source, providing data elements in a first order; a data destination, receiving data elements in a second order; memory devices having memory pages, data elements stored and retrieved in parallel to and from the memory devices; each buffer page having entries along a first dimension corresponding to the first order and along a second dimension corresponding to the second order, data elements stored in the first order and retrieved in the second order, at least one memory page stores data elements in multiple locations according to the first and second orders, at least two data elements consecutive in the first order are stored in parallel to the memory devices, and where at least two data elements consecutive in the second order are retrieved in parallel from the memories.

Abstract: Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer.

Abstract: A method and apparatus for antialiasing in a video graphics system is accomplished by determining if a pixel sample set, which results from oversampling, can be reduced to a compressed sample set, where the compressed sample set contains information describing a corresponding pixel. When the pixel sample set can be reduced to a compressed sample set, the compressed sample set is stored in a frame buffer at a location corresponding to the particular pixel that the sample set describes. When the pixel sample set cannot be reduced to a compressed sample set, a pointer is stored at the frame buffer location corresponding to the particular pixel. The pointer points to a selected address in a sample memory at which the complete sample set for the pixel is stored.

Abstract: In an image processing system or method, an image element memorizing device memorizes image elements which are image data that are subjects of process. An image element processing state memorizing device memorizes present processing states of the image elements in the image element memorizing device. A detecting device detects, in response to the present processing states, a pointer of one of the image elements that is capable of being processed by the image processing system. A temporary pointer memorizing device memorizes the pointer from the detecting device. A calculating device reads the pointer from the temporary pointer memorizing device to process an image in response to the image element of the pointer which is read.

Abstract: A graphics processing apparatus includes a drawn field register which stores coordinate values of boundaries of a drawn field, and an end point coordinate register which stores coordinate values of end points of a graphical element of interest. A first comparator compares the coordinate values of the boundaries of the drawn field with the coordinate values of the end points of the graphical element of interest. A comparison result register stores comparison results output by the first comparator. A decoder determines, based on the comparison results, whether the graphical element of interest should be drawn in the drawn field.

Abstract: Incoming geometry data are buffered in one or more buffers. The data are written to the buffers in an order which is not necessarily the order in which a processor or processors that construct images from the data need the data for fast processing. The data are provided to the processors in the order needed for fast processing. In some embodiments, fast processing involves starting critical path computations early. Examples of critical path computations are lighting computations which take more time than position computations. At least one processor has a pipelined instruction execution unit. The processor executes critical path computation instructions as long as a critical path instruction can be started without causing a pipeline stall. When no critical path instructions can be started without causing a stall, the processor starts a non-critical path instruction.

Abstract: A graphics memory system for managing image data for a volumetric display that displays volumetric images, the system including a first buffer memory with a first predefined address space for holding image data for a three-dimensional image; a second buffer memory with as second predefined address space for holding image data for a three-dimensional image, wherein the first and second predefined address spaces are the same; and a voxel router in communication with both the first and second buffer memories, wherein the voxel router is configured to use a selectable one of the first and second buffer memories as an active memory out of which stored image data is to be read for display on the volumetric display and to use the other of the first and second buffer memories as an inactive memory into which image data is to be written.