Abstract: Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.

Abstract: The invention provides a map display unit including a first memory for storing map data and a drawing memory for drawing the map data and displaying display-area data and a display. The map display unit includes a unit to read and decompress compressed map data stored in blocks in a data storage medium and to store the decompressed map data in the first memory; a unit to draw the stored map data in the drawing memory; and a unit to determine the display area and to display the display-area data of the drawing area in the drawing memory on the display. When there is no display-area data in the first memory, compressed map data is read and decompressed from the data storage medium by the data decompression unit. The map display unit further includes an environmental change sensor and controllers to vary the color tone of the map data with the environmental change, thereby displaying easily viewable map data.

Abstract: Provided are a display device with low power consumption which enables reduction of an operation processing amount of a GPU and which does not require a storage device for storing image data corresponding to one screen, and a display system using the display device. The display device is constituted by pixels each including storage circuits, an operation processing circuit, and a display processing circuit and circuits each having a function of storing image data in arbitrary storage circuits. The display system is constituted by the display device and an image processing device including the GPU. Image data is formed for each structural component through operation processing in the GPU in the display system. The formed image data is stored in the corresponding storage circuit for each pixel. The stored image data is subjected to composition processing by the operation processing circuit for each pixel. Then, the image data is converted into an image signal in the display processing circuit.

Abstract: An apparatus and method for storing image data comprising a first storage device and a second storage device. The first storage device may be configured to store at least one first pixel from a first field of a frame of the image at a first physical address in the first storage device. The second storage device may be configured to store a second pixel from a second field of the frame of the image at a second physical address in the second storage device. The first and second physical addresses may have the same relative position in an address space of the respective storage devices.

Abstract: An image processing apparatus operates with a high-speed print engine. An ASIC is provided between a graphics port and a peripheral device interconnection port. The print engine is connected to the peripheral device interconnection port. A memory is provided on a side of the CPU with respect to the graphics port. A CPU processes image data and stores the image data in the memory. The CPU transfers the image data stored in the memory to the print engine directly through the graphics port, the ASIC and the peripheral device interconnection port.

Abstract: A distributed memory controller memory system for a graphics processing system having addressable memory areas each coupled to a respective memory controller. The memory controllers are further coupled to each other through a memory controller bus upon which a memory access request and data may be passed from one memory controller to other memory controller. A memory access request to a memory location in one addressable memory area, but received by a memory controller coupled to another addressable memory area, is passed through the memory controller bus from the receiving memory controller to the memory controller coupled to the addressable memory area in which the requested location is located in order to service the memory access request. Additional memory controllers coupled to a respective addressable memory area may be included in the memory system. The memory controllers are coupled to the memory controller bus in order to receive and pass memory access requests from the other memory controllers.

Abstract: The present invention provides a technology that enables projection images to be overlaid with embellishment effects without depending on the capabilities of the image supply apparatus. A projection display apparatus that projects images onto a screen responsive to given image data, comprises: an embellishment effect memory for storing embellishment effect data representing an embellishment effect image that can be used to embellish an arbitrary image; an image embellishment section that generates embellished image data by overlaying an original image represented by the given image data and the embellishment effect image; a light modulation unit that is driven responsive to the embellished image data pixel by pixel; and an optical system for projecting onto the screen the embellished image obtained by the light modulation unit. A projection display apparatus superimposes the embellishment effect on the projected image without having to rely on the capabilities of an image supply apparatus.

Abstract: A rotated representation of an image is printed by using a coordinate system to assign tile divisions to the image. The size of the tile divisions are selected to maintain their area equal to, or less, than a predetermined maximum. Each segment of the image, as defined by the tile delineations, is sent separately to a data processing unit for processing. The received tile is assigned new coordinate dictating its new target position on a printed page, and its relation to the other tiles. The tile is itself further rotated prior to being send to the printer.

Abstract: A method and system for monitoring frame flow in a Fiber Channel network is provided. The method includes, deleting fill words before any frame data is allowed to be stored in a buffer memory; storing only certain primitive signals and/or frame data in the buffer memory; reading the buffer memory without delay, if a primitive signal is stored in the buffer memory; and delaying reading the buffer memory if frame data is detected. The network includes, a host bus adapter that includes a fiber channel protocol manager that includes a receive logic that deletes fill words before any frame data is allowed to be stored in a buffer memory, wherein the buffer memory stores only certain primitive signals and/or frame data and the buffer memory is read without any delay, if a primitive signal is stored, while a read operation of the buffer memory involving frame data is delayed.

Abstract: The present invention provides a low cost OSD system with minimal ROM requirements, minimal computing power required from the microcontroller, and minimal I/O port requirements. The OSD system creates a fixed frame around a small set of programmable characters. The small set of programmable characters is used to create an icon within the OSD display. The icon is selected by sending minimal information to the microcontroller. In one particular example, four bits of information are sent to the microcontroller to select one of the available sixteen different icons. The OSD frame characters and OSD programmable area icon characters are stored in ROM and no RAM is used. The OSD silicon die size is reduced as compared to a traditional OSD silicon die size.

Abstract: Methods and apparatus for storing data using two-dimensional arrays mapped to memory locations.

Abstract: A system and method for parallel rendering of images are described. Image information is stored into at least one buffer for display on a plurality of display modules. A predetermined number of image units from said image information are mapped to each display module of said plurality of display modules.

Abstract: A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.

Abstract: The present invention discloses a portable digital graphic processing device having the required graphic processing capability by adopting the advanced multi-chip packaging technology and intelligent stick memory card packaging technology to integrate the graphic processing function into an intelligent stick for the portable purpose and integrate a portable device such as a PDA or a smart phone to enhance the digital graphic processing capability of portable devices.

Abstract: A video player includes a CPU adapted to receive video data from an external electronic apparatus, two memories, and a video encoder connected to a video output device. The CPU stores video data from the external electronic apparatus in a first memory at first, and then stores received video data in a second memory when the first memory fully occupied, and at the same time transfers storage video data from the first memory to the video output device through the video encoder, and then switches the storage path to store received video data in the first memory again when the second memory fully occupied, and at the same time, transfers storage video data from the second memory to the video output device through the video encoder, for enabling all received video data to be completely transmitted to the video output device for output in the form of a moving picture.

Abstract: A pixel load instruction for a programmable graphics processor. The pixel load instruction may be used during processing of graphics data to load graphics data from a writable output buffer into a local storage element. Using the pixel load instruction may ensure that the graphics data loaded is current, i.e., any pending writes to the location storing the graphics data are completed prior to loading the graphics data. Furthermore, the pixel load instruction may be enabled and disabled for one or more writable output buffers by setting or clearing bits in a pixel load enable register.

Abstract: Methods and apparatus for storing and retrieving data. In one implementation, a system includes: a data source, providing data in a first order; a data destination, receiving data in a second order; memory devices having memory pages, data stored in parallel and retrieved in parallel; each buffer page having entries along a first dimension corresponding to the first order and entries along a second dimension corresponding to the second order, data stored according to the first order using blocks of buffer pages, each block having a number of pages equal to a power of 2, data stored in the first order and retrieved in the second order, at least one memory page stores data in multiple locations according to the first and second orders, data elements consecutive in the first order are stored in parallel, data elements consecutive in the second order are retrieved in parallel.

Abstract: By making it possible to freely change calculations of as well as variables that are input into the same calculation circuits, dedicated circuits corresponding to rendering functions become unnecessary, and in order to realize multi-functional rendering with circuitry of a small scale, a graphic image rendering apparatus includes a rendering information generation portion that generates rendering parameters corresponding to X and Y coordinates of pixels constituting a graphic image, a pixel calculation portion that, for each pixel, makes a selection as appropriate from the rendering parameters and a constant and performs a calculation, and a memory interface portion that writes a calculation result of the pixel calculation portion into a frame memory.

Abstract: A data search apparatus searches a database in which data consisting of still image data and meta-data is registered. The data is searched based on a set search condition and the meta-data contained in each item of the data registered in the database. While conducting a search, if there is data which does not actually exist in a thumbnail list, that data is deleted from the database. If there is any data which is stored in a predetermined logical area and which is not registered in the database, that data is added to the data in the database.

Abstract: A high-resolution still picture decoding device is disclosed, which has a memory device, an image decoder, and a decoding controller. The memory device has a bit-stream buffer, a frame buffer and a temporary buffer. The image decoder and decoding controller decode the bit-stream data in the bit-stream buffer and store the decoded data in the frame buffer or temporary buffer. When a still picture is to be displayed, the frame buffer stores part of the frame data corresponding to the still picture and the temporary buffer is provided to store the other frame data which is decoded in real time as the still picture is displayed. The data in the frame buffer and temporary buffer is output for displaying a high-resolution still picture.

Abstract: Methods and apparatus for implementing a pixel page system providing pixel pages optimized for use with a GLV (grating light valve). In one implementation, a system includes: a data source, providing pixel data for pixels in a first order, each pixel in a frame having rows and columns of pixels; a data destination, receiving pixel data for pixels in a second order; at least one memory device including memory pages having memory locations; pixel data for each pixel corresponds to an entry in a pixel page, each pixel page having rows and columns and including pixels, the pixel pages optimized for use with a GLV. Pixel data is stored to memory in the first order and retrieved in the second order. And each memory page stores pixel data in multiple locations according to the first order and stores pixel data in multiple locations according to the second order.

Abstract: An apparatus and method for displaying a multimedia screen in a mobile terminal. A first memory selectively stores multimedia image data received at a service request of the mobile terminal or text data and background screen image data provided for a display service of the mobile terminal. A second memory stores the text data and the background screen image data. An image output processor reads data from the first memory and the second memory, and provides the read data to a display unit of the mobile terminal.

Abstract: A hot-plugging method for a display apparatus is disclosed which includes the steps of reading information pertaining to a display apparatus by a predetermined data communication upon recognizing that a display apparatus has been newly connected while a controller provided in a main body of a computer maintains judging of a new connection of display apparatus; judging whether the read information is identical to the previously stored information stored at a memory pertaining to the current display apparatus; and storing the newly read information the newly read information is not identical to the previously stored information, determining an optimal resolution corresponding to the newly connected display apparatus and transmitting the optimal resolution to a video card.

Abstract: A data transferring apparatus for transferring transfer packets each including one or more transfer data as objectives of transfer from a first apparatus to a second apparatus, each transfer data including commands indicating processes against a preliminarily assigned area, the first apparatus comprises a unit for merging a plurality of the transfer data meeting a certain requirement, a unit for generating transfer packets each including at least one of one or more the transfer data whose amount is within a certain predetermined range and one or more the merged transfer data, and a unit for transferring the generated transfer packets to the second apparatus.

Abstract: Methods and apparatus for implementing a pixel page system providing swapped pixel pages for use with a GLV (grating light valve).

Abstract: A programmable graphics processor for multithreaded execution of program instructions including a thread control unit. The programmable graphics processor is programmed with program instructions for processing primitive, pixel and vertex data. The thread control unit has a thread storage resource including locations allocated to store thread state data associated with samples of two or more types. Sample types include primitive, pixel and vertex. A number of threads allocated to processing a sample type may be dynamically modified.

Abstract: A method for an image reducing processing circuit includes the memory architecture of two FIFO units. The method includes the following steps of: providing an input processing unit receiving original image data and delivering the image data; providing a horizontal direction image processing unit receiving the image data from the input processing unit; providing a first step FIFO unit receiving the image data from the horizontal direction image processing unit to read and write the image data on the same access frequency; providing a vertical direction image processing unit receiving the image data from the first step FIFO unit; providing a second step FIFO unit receiving the image data from the vertical direction image processing unit and implementing the readout/writing of the image data on two access frequency, and providing an output processing unit receiving the image data from the second step FIFO unit and outputting reduced image.

Abstract: An image processing apparatus is provided that includes a primary memory unit to buffer image data, a secondary memory unit to store the image data transferred from the primary memory unit, and a memory control unit that controls both memory units. The memory control unit transfers, if a plurality of items of image data are to be transferred, at least one of the items of image data divisionally from the primary memory unit to the secondary memory unit. When image data are transferred from the primary memory unit to the secondary memory unit, the memory control unit transfers a unit image either in a block or divisionally in multiple parts, and the memory control unit simultaneously transfers a plurality of images divisionally, the images being divided into varying numbers of parts so that each input and output of an image can evenly share the time of the secondary memory unit and a plurality of images can be efficiently transferred in parallel in a short time.

Abstract: When a user pushes a scroll-direction key, an ECU obtains, from a memory, a division map corresponding to a division located in a direction designated by the scroll-direction key. The ECU then outputs the division map to a display controller. The display controller compresses the division map to store in a VRAM. At scrolling a displayed image, the display controller expands the compressed division map. It then outputs, to an image signal generator, only a necessary portion of the expanded division map. Thereby, the displayed image can be scrolled at high speed and easily recognizable for the user.

Abstract: The computer graphics system is configured to generate a shadow effect with a stencil shadow volume method using a combination of compressed and uncompressed stencil buffers in coordination with compressed and uncompressed depth data buffers. An uncompressed stencil buffer is capable of storing stencil shadow volume data for each pixel and a compressed stencil buffer is capable of storing stencil shadow volume data for a group of pixels.

Abstract: An improved raster engine adapted to render video data from a frame buffer to one of a plurality of disparate displays is disclosed which comprises an integral bounded video signature analyzer, a hardware cursor apparatus supporting dual scanned displays, programmatic support for multiple disparate display types, multi-mode programmable hardware blinking, programmable multiple color depth digital display interface, and programmable matrix controlled grayscale generation.

Abstract: A cache memory system is used in a motion estimation system. The system includes: a first cache memory defined in terms of a first width and a first height, and a second cache memory defined in terms of a second width and a second height, wherein said second height is less than said first height, the cache memory system being operable in one of two modes: the first mode being characterized by banks of memory from the second cache memory being concatenated vertically such that their concatenated height is at least equal to the first height, and said concatenated banks being arranged to be appended to the width of the first cache memory to form a single contiguous address space; and the second mode being characterized by banks of memory from the first and second cache being stacked vertically, and being arranged to be addressed as two separate address spaces.

Abstract: A communication method apparatus are disclosed, including a common bus; a plurality of multiplexers that communicate with the common bus; a plurality of memories, each in communication with a separate one of the plurality of multiplexers and each having a different storage capacity, that together form a hierarchical storage structure; a bus arbiter that controls access to the common bus; a first interface that communicates information with the common bus; and a second interface that communicates information with the common bus.

Abstract: A method of supporting all raster-based image manipulations described in vector-based terms. The present invention has the benefits of providing clean transformation that vector-based manipulations yields, and providing a broad selection of all image transformation operations that raster-based manipulations yield. In one aspect of the invention a vector-defined shape is drawn on top of a raster-based image by replacing the contents of the vector image with the bits from the raster image. In another aspect of the present invention, a copy of the portion of the raster image that overlaps with the vector-defined portion is made, the transformation operation is performed on the copy, and then the portion of the raster image is replaced with the transformed copy.

Abstract: A first image processing system, a second image processing system, a first storage system and a second storage system communicate over a high bandwidth switch. The switch connects the first processing system to the first storage system and also connects the second processing system to the second storage system. At the first image processing system, first location data is read to identify the location of frames on the first frame storage system. Similarly, at the second image processing system second location data is read to identify the location frames on the second frame storage system. In response to control commands issued to the switch, the first image processing system is disconnected from the first storage system and reconnected to the second storage system. Similarly, the second processing system is disconnected from the second storage system and reconnected to the first storage system.

Abstract: A computer system includes a monitor, a memory and a processing unit. The monitor includes a main area for displaying an image. The main area has a plurality of rows and a plurality of columns of tiles. Each tile has a plurality of rows and a plurality of columns of display units, and each display unit is for displaying a portion of the image according to corresponding pixel data. The memory includes a plurality of first sequential memory units and a plurality of second sequential memory units. The first sequential memory units are for storing pixel data of a first tile. The second sequential memory units are for storing pixel data of a second tile. The second tile is horizontally next to the first tile. The processing unit sequentially transmits pixel data of pixels in the first tile before transmitting pixel data of pixels in the second tile.

Abstract: By making it possible to freely change calculations of as well as variables that are input into the same calculation circuits, dedicated circuits corresponding to rendering functions become unnecessary, and in order to realize multi-functional rendering with circuitry of a small scale, a graphic image rendering apparatus includes a rendering information generation portion that generates rendering parameters corresponding to X and Y coordinates of pixels constituting a graphic image, a pixel calculation portion that, for each pixel, makes a selection as appropriate from the rendering parameters and a constant and performs a calculation, and a memory interface portion that writes a calculation result of the pixel calculation portion into a frame memory.

Abstract: A distributed memory controller memory system for a graphics processing system having addressable memory areas each coupled to a respective memory controller. The memory controllers are further coupled to each other through a memory controller bus upon which a memory access request and data may be passed from one memory controller to other memory controller. A memory access request to a memory location in one addressable memory area, but received by a memory controller coupled to another addressable memory area, is passed through the memory controller bus from the receiving memory controller to the memory controller coupled to the addressable memory area in which the requested location is located in order to service the memory access request. Additional memory controllers coupled to a respective addressable memory area may be included in the memory system. The memory controllers are coupled to the memory controller bus in order to receive and pass memory access requests from the other memory controllers.

Abstract: A graphics drawing device capable of reducing the amount of information transferred. In the graphics drawing device for drawing graphics, a first storage circuit stores coordinate information and attribute information about a main graphic which is an original graphic. A second storage circuit stores coordinate information and attribute information about one or two or more derivative graphics derived from the main graphic. A drawing circuit draws the main and derivative graphics in accordance with the information stored in the first and second storage circuits, and a control circuit controls the drawing process performed by the drawing circuit.

Abstract: An image processing system comprises a plurality of memories to which image data is input, a control circuit for selecting areas for image processing from the image data input to the memories, and a plurality of DSPs connected to the memories and performing image processing of the selected image data selected by the control circuit. The present invention provides a an image processing system and method where selected image data including overlap areas can be sent from memories to DSPs by entering the same image data into a plurality of memories, without requiring transfers of overlap areas between DSPs, such that the image processing speed is improved.

Abstract: Systems and methods for private addressing in a multi-processor graphics processing subsystem having a number of memories and a number of graphics processors. Each of the memories includes a number of addressable storage locations, and storage locations in different memories may share a common global address. Storage locations are uniquely identifiable by private addresses internal to the graphics processing subsystem. One of the graphics processors is able to access a location in a particular memory by referencing its private address.

Abstract: There is provided a segment-based pixel processing apparatus and method for effective use of memory. The method includes dividing pixel data within a frame into a plurality of segments in the vertical direction; sequentially pre-processing or post-processing pixel data in a segment among the plurality of segments in line units, and then, sequentially pre-processing or post-processing pixel data in a next segment in line units; and repeating pre-processing or post-processing on pixel data in the other segments in line units until reaching a segment of a predetermined number.

Abstract: An apparatus comprises two or more image processing units and a main merger unit. Each image processing unit comprises four information processing units and a sub merger unit for merging data output from the four information processing units. The main merger unit merges data output from multiple sub merger units. Data output from the information processing units are stored in parallel in a register on a unit length basis for serial transmission. Auxiliary data is added for identifying data that have been altered or modified. The serial data, with the auxiliary data added thereto, are output to the main merger unit.

Abstract: An electronic projector capable of saving and displaying a user-defined logo is provided. The electronic projector receives video signals from an image source device, such as a computer, a DVD, or a television for projecting the video signals onto a screen. The video signals from the image source device are converted to digital signals and then temporarily saved in a display buffer to speed up the display rate. The user-defined logo can be designed by a graphics application program or by freezing a static image from the video signals. After converting to digital signals, the user-defined logo is then saved in a non-volatile memory. A data access controller controls the display and update of the user-defined logo. When the user-defined logo is to be updated, the new user-defined logo is saved in the non-volatile memory to overwrite the previous logo.

Abstract: A system for performing interactive virtual reality sessions without constraining the mobility of a user is disclosed. The system allows a user to remain fully mobile while participating in an interactive virtual reality session. The system comprises a handheld computing device having a display, user input controls, a location sensing device and a user sensing device. To conduct a virtual reality session, a software application is loaded from a memory. Then, the computing device determines its position within a space using the location sensing device, and the user sensing device establishes a relationship between the user's eyes and display. This relationship is used to provide the user with the same perspective as would be achieved if viewing the simulated session in real life. User input controls allow the user to control aspects of the session to further enhance the user's experience.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: The present invention provides a system and method for checking authorization of remote configuration operations. The method comprises storing at least one image frame such that content of the image frame is stored in a plurality of memory pages in a memory. The method further comprises sending the image frame to the display one memory page at a time to refresh the display.

Abstract: A method and system are provided for executing SIMD instructions using graphics technology. A SIMD instruction is received and interpreted. The specific data needed for the SIMD instruction is identified. Texel addresses where the specific data are stored are recalled and frame buffer pixels to be used to support the SIMD instruction are selected. In an alternative embodiment, these texel addresses are stored in frame buffer pixel channels such that the pixel containing a particular address will be the pixel to hold the data stored at that address for the SIMD operation.

Abstract: A system and method are disclosed for utilizing a Z slope test to select polygons that may be candidates for multiple storage methods. The method may calculate the absolute Z slope from vertex data and compare the calculated value with a specified threshold value. In some embodiments, for polygons that have an absolute Z slope less than the threshold value, parameter values may be rendered for only one sample position of multiple neighboring sample positions. The parameter values rendered for the one sample position may then be stored in multiple memory locations that correspond to the multiple neighboring sample positions. In some embodiments, storing parameter values in multiple memory locations may be achieved in a single write transaction. In some embodiments, utilization of the Z slope test method may be subject to user input and in other embodiments may be a dynamic decision controlled by the graphics system.

Abstract: A method and system for optimizing the processing of graphics is disclosed. The system may comprise at least one geometry processor and at least one graphics processor. A communication channel permits communication between the geometry and graphics processors. A control processor may communicate with the geometry and graphics processor through the communications channel. A method of processing graphics data in a computer system is provided to determine whether the geometry and graphics processors are being efficiently utilized. If necessary, one or more of the geometry and graphics processors are selectively assigned or unassigned to improve the efficiency of the graphics processing circuitry in performing the graphics task.