Abstract: A system and method are disclosed for reproducing a pre-selected larger 2-D sample location pattern from a smaller one by means of X,Y address permutation. This method, for example, allows hardware to effectively reproduce a pre-selected set of sample locations for an array of 128×128 sample bins from a smaller set of pre-selected sample locations for an array of 2×2 sample bins. A permutation logic unit may use a first portion of an address for a sample bin B to identify a corresponding 2-D transformation, apply the inverse of the transformation to a second portion of the sample bin address to identify the corresponding bin of the 2×2 array of sample bins, and apply the transformation to the sample locations stored in the corresponding bin to reproduce the sample locations pre-selected for sample bin B.

Abstract: A data table includes a source pointer indicating a starting address of drawing data, a destination pointer indicating a destination of drawing data to be transferred, and a data length indicating a data length of drawing data to be transferred. Data table may indicate drawing data to be drawn. Thus frames may share drawing data. As such the amount of drawing data can be reduced.

Abstract: A graphics memory architecture in which row addresses are permuted, in a basically tile-oriented storage architecture, so that fast parallel access is provided both by scanlines (for video operations) and also by tiles (for graphics operations).

Abstract: A graphics system includes a frame buffer that includes one or more memory devices and a frame buffer interface coupled to the frame buffer. Each memory device in the frame buffer includes N banks. Each of the N banks includes multiple pages, and each page is configured to store data corresponding to a portion of a screen region. The frame buffer interface is configured to generate address used to store data corresponding to a frame of data in the frame buffer. The frame includes multiple screen regions. The frame buffer interface is configured to generate addresses corresponding to the data and to provide the addresses to the frame buffer. The addresses are generated such that each of the N banks stores data corresponding to a portion of one out of every N screen regions within a horizontal group of screen regions.

Abstract: An image rendering device holds a table which contains color and brightness values at positions specified by two-dimensional coordinates, where the color values are aligned so as to express a gradation of color tone along one coordinate axis of the two-dimensional coordinate, and the brightness values are aligned so as to express a gradation of brightness along the other coordinate axis. The image rendering device finds parameters corresponding to at least one of color and brightness of a polygon to be rendered, and generates an address for referencing a two-dimensional coordinate corresponding to each pixel composing the polygon based on the parameters. The image rendering device then acquires from the table color and/or brightness values corresponding to the address for referencing the two-dimensional coordinate. This successfully realizes natural expression by the image rendering device without preparing in advance a huge number of textures.

Abstract: Methods and apparatus for storing data using two-dimensional arrays mapped to memory locations.

Abstract: Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. In one implementation, a checkerboard buffer includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least two memory devices, each memory device having a plurality of memory locations, where data is stored in parallel to the memory devices and retrieved in parallel from the memory devices; a first data switch connected to the data source and each of the memory devices, where the first data switch controls which data is stored to which memory device; and a second data switch connected to the data destination and each of the memory devices, where the second data switch controls providing data to the data destination according to the second order.

Abstract: A graphics system and method for storing and accessing texture maps comprising texels. The graphics system may include a graphics processor and a texture memory comprising a plurality of memory devices for storing the texture maps. The texels (or portions of the texels) may be stored in the memory devices in an interleaved fashion. The texel data is interleaved in the memory devices to guarantee that, no matter which N×M array of texels is accessed, each texel in the array is present in a different memory device or chip and hence are concurrently available. Thus the N×M array of texels may be output concurrently or simultaneously, regardless of which array is accessed, i.e., regardless of which pixel is addressed. Embodiments are also described where the memory devices output arrays of texels for at least two respective neighboring pixels, or a 3D array of texels, in parallel in response to a single read transaction.

Abstract: Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels for one frame is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. While data is being stored, data for pixels from another frame is retrieved from another two memory devices. The banks of devices alternate between storing and retrieving with each frame.

Abstract: Flat panel displays, such as field emission displays (FEDs), plasma displays, liquid crystal displays (LCDs), and electroluminescent displays (ELs), are provided incorporating driver circuitry on the same substrate as the active display region of the display device and further reducing through-vacuum and substrate-to-substrate interconnects. In one implementation, an image display device comprises a substrate; an active display region formed on the substrate and including addressable rows and columns defining pixels; and one or more driver ICs on the substrate, respective outputs of each driver IC coupled to respective ones of the addressable rows and columns, the driver ICs adapted to drive the active display region to display an image. The device also comprises a wireless receiver coupled to the driver ICs, the wireless receiver adapted to wirelessly receive a wireless signal including an input video signal for display and couple the input video signal to the driver ICs.

Abstract: A video and graphics system has an input for receiving compressed video data and an input for receiving graphics data. The compressed video data may include HDTV video and/or SDTV video, and may be included in compressed data streams such as an MPEG-2 Transport stream. The video and graphics system also includes a video decoder for processing the compressed video data to generate a video for displaying, a display engine for processing the graphics data to generate graphics for displaying, and an overlaying system for compositing the video and the graphics to generate an output video. The display engine includes a memory used during conversion of a graphics format from a first format to a second format to be in a format compatible with a video format The memory may be implemented in a single-port SRAM configured to simulate a dual-port SRAM. The system may be integrated on an integrated circuit chip.

Abstract: A screen driver for a liquid crystal display screen includes an internal animation circuit for displacing data on a screen. The animation circuit also process data, such as modifying data between a source address and a destination address of a RAM memory. The RAM memory contains a screen memory and a buffer memory. The internal animation circuit allows relief of an external central microprocessor of equipment having the liquid crystal display screen from corresponding processes. Further, the number of data exchanges between the microprocessor and the screen driver is reduced and thus the power consumption of the equipment caused by the screen animations is also reduced.

Abstract: A vertex data access apparatus and method. The apparatus receives a vertex index, compares the vertex index with any vertices' indices used before, issues a request if necessary for fetching vertex data in system memory, stores the return vertex data in a vertex data queue and gets corresponding vertex data from the vertex data queue for further processing and, more particularly, if the vertex index is the same as one of those vertices' indices, the corresponding vertex data can be directly fetched from the vertex data queue. The vertex data queue performs the vertex cache function.

Abstract: A three dimensional parallax drawing system for use in three dimensional graphics or virtual reality is disclosed. The parallax drawing system includes a three dimensional address generator which generates the original X-axis, Y-axis and Z-axis addresses of an image, and an address correction circuit for producing a corrected X-axis address in response to the original X-axis and Z-axis address outputs from the address generator. Also included is an address selection circuit for selecting either the original X-axis address supplied from the three dimensional address generator or the corrected X-axis address from the address correction circuit as a resultant X-axis address in response to a stereo graphic mode request signal. A frame buffer address generator is provided for converting the resultant X-axis address received from the address selection means and the Y-axis address received from the three dimensional address generator into the frame buffer linear address.

Abstract: A system and method for reordering data fragments to facilitate reads from a DDR SDRAM where the fragments are placed into a first and second data fragment buffer such that the data fragments are in sequential addresses whereby the second data read on the trailing edge of the clock cycle will read the proper data fragment.

Abstract: Embodiments of the present invention provide a split vertex buffer where the data for each vertex is split between parallel vertex buffers. The first buffer contains vertex X and Y data, while the second parallel buffer contains the remainder of the vertex data. Given the split vertex buffers, the hardware binning-engine is now permitted to read and cache only vertex screen X and Y data. Especially given a typically high level of temporal coherency between indexed vertex references, the reading and caching of large parcels of vertex screen-space X and Y leads to lower and highly efficient utilization of memory bandwidth for hardware binning input. Embodiments of the present invention thus reduce the hardware binning memory bandwidth requirements and improve memory utilization.

Abstract: A method to perform image transformations that are simplistic, conducive to miniaturization, and inexpensive to implement is provided. Transformations of an image stored in system memory are carried out by copying the image data, transforming the image data to a selected orientation, and outputting the transformed image for display, printing, or others. Throughout the transformation process, the image stored in system memory remains unchanged in the original orientation (T0-normal transformation). The transformation process is carried out by accessing in predetermined orders/sequences the image data copied from system memory to a frame buffer that is made up of N memory modules and arranged such that image data are stored serially with the image scan lines running the length of the frame buffer like that of a traditional frame buffer but with each memory module capable of being individually accessed.

Abstract: An image data processing apparatus capable of performing processing at a high speed comprising a DRAM for storing display data including a plurality of first pixel data respectively indicating colors of a plurality of pixels arranged in a matrix and able to be simultaneously written with a plurality of first pixel data. Memory controllers are provided with a plurality of pixel data generation circuits provided corresponding to the plurality of first pixel data to be simultaneously written for performing color blending using the second pixel data and the third pixel data for blending a color indicated by corresponding second pixel data and a color indicated by third pixel data stored in the write address by a predetermined blending ratio to generate a new color so as to generate the first pixel data indicating the new color.

Abstract: A memory access method for video decoding is provided. More particularly, a method of storing pixel data of a reference picture and retrieving a prediction block of the reference picture from a memory is provided. The memory is divided into several pages. The reference picture consists of a top field and a bottom field, and is divided into several macroblocks. Each macroblock has a corresponding portion of the top field and the bottom field. The method includes the steps of: dividing each page into a top-section having one or more consecutive addressing area and a bottom-section having one or more consecutive addressing areas; storing the corresponding top field and corresponding bottom field of the macroblocks into the top-sections and bottom-sections, respectively; and then retrieving the pixel data of the prediction block stored in the memory in a page-by-page manner.

Abstract: A method and a system for buffer management is provided. The system includes a central processing unit, a multimedia chip, a buffer, a beginning register, an ending register, and a pause register. The beginning register is employed to store a beginning address of the buffer, and the ending register is used to storing an ending address of the buffer or buffer length. Content of the pause register is a data address associated with a command data. In addition, the pause register includes a pause code. When the pause code is equal to a first value, after the multimedia chip reads command data associated with the content of the pause register, reading is stopped, and the command data next to the command data are to be read in the next reading. When the pause code is equal to a second value, after the multimedia chip reads the command data associated with the content of the pause register, the multimedia chip continues to reads command data associated with the beginning register.

Abstract: A decoding system which is arranged to perform a plural-stage process in determining which of the driver lines to stimulate in response to each electrode address value supplied to the decoder. This enables the network configuration of the impedances to be machine generated, and also enables the decoder to calculate on the fly which driver lines to stimulate in response to each address value. Furthermore, different resolutions may be provided to enable groups of the electrodes to be addressed simultaneously. Such a decoder arrangement may also be used with an electrode arrangement in which each electrode is connected to only two of the driver lines, in order to achieve addressing schemes in which up to t consecutive electrodes can be driven simultaneously. The invention is applicable, for example, to liquid crystal displays, arrays of memory elements and arrays of sensors such as light-sensors.

Abstract: A method and software for remote control of computer apparatus is disclosed. The method and software use computer network communications to effect remote control of apparatus that are connected to a computer at a remote location.

Abstract: It is an object to provide a drive unit capable of properly responding to an access request from a microprocessor side and an access request from a display section side, and further of realizing a high-speed operation and a low power consumption operation. When an MPU access request from an MPU side and an LCD access request from an LCD side take place, an arbitration circuit (160) makes arbitration to start an access operation to a RAM (100) according to one of the access requests. Additionally, a memory access monitor signal /BUSY for monitoring an access state to the RAM is outputted to an external terminal to be inputted to a hardware wait control terminal of the MPU. The arbitration circuit starts the access operation on condition that a RAM precharge operation reaches completion. The MPU sets a start address and an end address on a column and a page and issues a writing start command, whereupon display data in a display area is rewritten automatically.

Abstract: A method for transferring data between an RGB color space and a YCrCb color space useful for a DCT block-computation engine significantly increases throughput and decreases processor overhead. According to one example embodiment, a DMA function is optimized to fetch data from an external memory representing a RGB color space and to provide the data for a JPEG conversion while performing YCrCb color space conversion on the fly. More specifically, data is transferred from the RGB color space memory to a DCT block-computation engine adapted to process a YCrCb color space memory. The method includes providing the data for an RGB display screen area as a tile array having C columns and R rows of tiles, where one tile corresponds to sufficient RGB data for a DCT of at least one of a Cr data array and a Cb data array. Data is fetched at addresses in the tile array by accessing the data one tile at a time, and both the row within each tile and the tile within the tile array are tracked.

Abstract: A relatively high speed circular memory device, in combination with other processes, improves image processing efficiency. To that end, a method and apparatus of processing image data stored in an initial memory logically divides the image into a plurality of contiguous strips. A first plurality of the strips are stored in a working memory having a circular addressing arrangement, where the working memory is faster than the initial memory and has a plurality of sequential address locations. The first plurality of strips are contiguous and have a start address. In addition, the first plurality of strips are stored in the working memory in a contiguous manner, and processed through the working memory relative to the start address.

Abstract: In a rendering apparatus for bitmapping object data into bitmap image data in accordance with a process list to generate rendering data, a plurality of addresses to the process list is designated. One of the plurality of designated addresses is selected. Object data is bitmapped into bitmap image data in accordance with the process list at the selected address to generate rendering data.

Abstract: The geometry processor includes mutually independent first and second external interface ports connected to a host processor, and a rendering processor, respectively, and a geometry calculation core which processes a geometry calculation applied through the first external interface port from the host processor. The geometry calculation core includes a plurality of SIMD type floating point calculating units, a floating point power computing unit, an integer calculating unit, a controller responsive to an instruction from the host processor which controls the plurality of floating point calculating units, the floating point power computing unit and the integer calculating unit to process data from the host processor, and an output controller which outputs the processed data to the rendering processor through the second external interface port.

Abstract: A display subsystem supports both normal mode and portrait mode displays. In normal mode, the scan starts at the upper left comer of the display. In portrait mode, the scan starts at the lower left comer of the display. The display subsystem includes a dual mapped display memory having a normal mode display area and a portrait mode display area. The portrait mode display area is defined by X-ofst(Virtual) and Y-ofst. X-ofst(Virtual) is a power of two that is greater than the real X-ofst supported by the display in portrait mode. Address requests from the CPU or software use high order bits to specify whether the address is in the normal or portrait mode display area. In addition, address requests to the portrait mode display area use the address space defined by X-ofst(Virtual) and Y-ofst. When the address request specifies the portrait mode display area, the address of the request is translated to account for the different mode of the display.

Abstract: An optimizing unit for use with an interleaved memory and suitable for use in a computer graphics system is described. The unit utilizes knowledge of the repetitive and predictable nature of texture buffer accesses to potentially reduce the number of memory fetches. The unit maintains a queue of pending requests for tiles of data from the memory, and predicts the retrieval of redundant data within short sequences of requests. The redundant data is retrieved from the memory once, and repeated as necessary from local temporary storage registers.

Abstract: On-screen-display graphics data is transmitted from a source device to a display device over an IEEE 1394-1995 serial bus network utilizing an isochronous data format. The on-screen-display graphics data is generated by the source device and transmitted to a display device, as a stream of isochronous data, separate from video data. Each packet of isochronous data within the stream of on-screen-display graphics data includes an address value corresponding to a memory address within the display device forming a buffer. When received by the display device the on-screen-display graphics data is loaded into the appropriate memory locations within the buffer corresponding to the address values. At the display device, an embedded stream processor is utilized to strip the header information from each packet and determine the appropriate memory location that the data is to be stored. A trigger packet is sent at the end of the data stream for a screen of on-screen-display graphics.

Abstract: A method, system, and computer program product is provided for managing the efficient transfer of graphics data to a graphics rendering system. A graphics application program writes graphics data to graphics buffers that are allocated in virtual memory. Each graphics buffer comprises a plurality of memory locations, followed by a sentinel page. While the application is writing graphics data to a graphics buffer, a sentinel page may be reached. If so, the operating system recognizes this condition as a graphics buffer page fault. In responding to this fault, the contents of the graphics buffer are transferred to the graphics rendering subsystem. In addition, the graphics data being output by the application is redirected to another graphics buffer.

Abstract: A system and method for packing pixels together to provide a increased fill rate in a frame buffer hardware in the graphics system. The graphics system may be configured to receive and rasterize graphics data at a faster cycle rate than the system's frame buffer memory fill rate. The output from the rasterization hardware may be stored in a FIFO memory that is configured to selectively shift pixels in order to improve fill rate performance. The FIFO memory may be configured to ensure that the pixels meet certain criteria in order to prevent page faults and interleave conflicts that could reduce the fill rate. The FIFO memory may also be configured to remove empty cycles that occur as a result of the pixel packing.

Abstract: A pixellated device (10), such as a display, has pixel row and column address lines (18,20) for addressing each pixel, thereby providing signal data to each pixel (12) or reading signal data from each pixel. An array of memory cells (22) is provided on the substrate interspersed with the pixel drive circuitry (16), wherein memory address circuitry (24,26,28,30) is provided enabling data to be written to each memory cell and enabling data to be read from each cell (22), independently of the signal data. Each memory cell (22) is thus addressable independently of the pixel data. Thus, the memory cells do not form part of the pixel circuitry, which allows the memory to be used in a flexible manner. For example, the memory may be used for purposes not directly associated with the driving or addressing of the pixels of the device.

Abstract: A graphics memory architecture in which row addresses are permuted, in a basically tile-oriented storage architecture, so that fast parallel access is provided both by scanlines (for video operations) and also by tiles (for graphics operations).

Abstract: A bit operation processor having a first address operation unit for updating the address of data in units of byte or multipled bytes for performing operation in units of byte or multiple of bytes, a second address operation unit for updating the address of data in units of bit or multiple of bits, an address control means operating on the first address operation unit to advance the address in response to the result of address advancement by the second address operation unit, and means for fetching byte-wide data for operation as addressed by the first address operation unit, whereby operation between data of any number of bits at any positions in byte blocks is controlled simply and fast.

Abstract: Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels for one frame is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. While data is being stored, data for pixels from another frame is retrieved from another two memory devices. The banks of devices alternate between storing and retrieving with each frame.

Abstract: Methods and apparatus for adjusting the geometry of buffer pages.

Abstract: Methods and apparatus for storing data using two-dimensional arrays mapped to memory locations.

Abstract: Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer.

Abstract: Methods and apparatus for storing and retrieving data. In one implementation, a system includes: a data source, providing data in a first order; a data destination, receiving data in a second order; memory devices having memory pages, data stored in parallel and retrieved in parallel; each buffer page having entries along a first dimension corresponding to the first order and entries along a second dimension corresponding to the second order, data stored according to the first order using blocks of buffer pages, each block having a number of pages equal to a power of 2, data stored in the first order and retrieved in the second order, at least one memory page stores data in multiple locations according to the first and second orders, data elements consecutive in the first order are stored in parallel, data elements consecutive in the second order are retrieved in parallel.

Abstract: Methods and apparatus for storing and retrieving data using two-dimensional arrays. In one implementation, a checkerboard buffer page system includes: a data source, providing data elements in a first order; a data destination, receiving data elements in a second order; memory devices having memory pages, data elements stored and retrieved in parallel to and from the memory devices; each buffer page having entries along a first dimension corresponding to the first order and along a second dimension corresponding to the second order, data elements stored in the first order and retrieved in the second order, at least one memory page stores data elements in multiple locations according to the first and second orders, at least two data elements consecutive in the first order are stored in parallel to the memory devices, and where at least two data elements consecutive in the second order are retrieved in parallel from the memories.

Abstract: Methods and apparatus for storing and retrieving data using two-dimensional arrays. In one implementation, a checkerboard buffer page system includes: a data source, providing data elements in a first order; a data destination, receiving data elements in a second order; memory devices each having memory pages, data elements stored in parallel to and retrieved in parallel from the memory devices; each buffer page having entries along a first dimension corresponding to the first order and entries along a second dimension corresponding to the second order, data elements stored in the first order and retrieved in the second order, at least one memory page stores data elements in multiple locations according to the first and second orders, at least two data elements consecutive in the first order stored in parallel, and where at least two data elements consecutive in the second order retrieved in parallel.

Abstract: Methods and apparatus for storing and retrieving data. In one implementation, a system includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least four memories, each having memory pages, data stored to at least two memories and retrieved from at least two memories in parallel, each buffer page having entries along a first dimension corresponding to the first order and entries along a second dimension corresponding to the second order, data stored in the first order and retrieved in the second order, at least one memory page stores data in multiple locations according to the first and second orders, two data elements consecutive in the first order stored in parallel to the memories, at least two data elements consecutive in the second order retrieved in parallel from the memories.

Abstract: Apparatus and methods for storing and retrieving images for transmission to an output device are disclosed. A cache comprising one or more bitmaps is examined to determine whether the image to be transmitted generates a match with a bitmap already stored on the cache. If a match is found, the bitmap matching the image to be transmitted is retrieved from the cache. If no match is found, a bitmap representing the image is stored in the cache.

Abstract: A Graphics Engine (GE) FIFO interface architecture that allows the transfers of reduced address information from the GE to the frame buffer is provided. The FIFO interface architecture further allows the GE to be isolated from the Memory Interface Unit (MIU) or the Central Processor Interface Unit (CIF) such that the GE can operate at a different frequency from the MIU and the CPU. Address information is provided using two flag bits End of Line (EOL) and Add One (AO). In write mode, flag bits EOL and AO are used to determine the next address in the frame buffer where processed data from the GE is to be stored. In line draw mode, flag bits EOL and AO are used to determine the address in the frame buffer for data retrieval. Such data retrieval allows a rendered line to perform background and foreground color ROP in line draw commands. Flag bit EOL indicates whether the GE needs to skip to the next scan line (e.g., the end of the current scan line has been reached).

Abstract: In a data transfer circuit, a hold signal generating circuit generates and outputs a hold signal Hold when transmission data is equal to transmission data one cycle before, and sets a 3-state output buffer for transmission data to high-impedance state, while, in a data reception circuit, when the hold signal Hold is valid, a data reception circuit outputs the reception data held, thereby power consumption in a data bus which is terminated with a terminal resistor is reduced.

Abstract: An interface for a graphics system includes simple yet powerful constructs that are easy for an application programmer to use and learn. Features include a unique vertex representation allowing the graphics pipeline to retain vertex state information and to mix indexed and direct vertex values and attributes; a projection matrix value set command; a display list call object command; and an embedded frame buffer clear/set command.

Abstract: A method and apparatus for transferring commands to a graphics processor is provided. The method and apparatus are intended for use in a host computer system having a memory that is addressable by a host processor and a graphics processor. One or more queues of packet descriptors are maintained in the memory of the host computer system. Each packet descriptor includes a pointer to a region of memory known as a packet buffer. Each packet descriptor also includes a ready variable. To pass commands to the graphics processor, a graphics process selects a packet buffer. The packet buffer must have a ready variable that is set to the value false. After selection of the appropriate packet descriptor, the graphics process writes the desired commands into the packet descriptor associated with the selected packet descriptor. The graphics process then sets the ready variable included in the selected packet descriptor to true. The graphics processor traverses the queues of packet descriptors.

Abstract: On storing two-dimensional arrangement data into a memory (1) having banks, 2n in number, each of which is individually assigned with a bank number B and includes row addresses identified by row address numbers A, an address converter (3) calculates, in response to a coordinate (X, Y) representing a particular data element of the data elements of the two-dimensional arrangement data, the bank number B of a particular bank of the banks where the particular data element is to be memorized. The bank number B is given by: B={Y×(2n×m+k)+X}mod 2n, where m is a positive integer, where k is a positive integer smaller than 2n and other than 1, and where mod is an operator for calculating a remainder. The address converter also calculates the row address number A of a particular address of the row addresses of the particular bank where the particular data element is to be memorized.

Abstract: The present invention provides a method for operating a core logic unit including an embedded graphics controller. This method facilitates high-bandwidth communications between the graphics controller and other computer system components, such as the processor and the system memory. Thus, one embodiment of the present invention provides a method for operating a core logic unit with an embedded graphics controller. This method includes receiving processor communications from a processor through a processor interface in the core logic unit, and transferring the processor communications through a switch to a graphics controller located in the core logic unit. It also includes receiving memory communications from a system memory through a memory interface in the core logic unit, and transferring the memory communications through the switch to the graphics controller. These processor communications and graphics communications are used to perform graphics computations in the graphics controller.