Abstract: Devices, methods, and other embodiments associated with processing rasterized data are described. In one embodiment, an apparatus includes translation logic for converting lines of rasterized pixel data of a compressed image to a plurality of two-dimensional data blocks. The lines of rasterized pixel data are stored in consecutive memory locations. Each data block is stored in a consecutive memory location. The apparatus includes decompression logic for at least partially decompressing the compressed image based, at least in part, on the two-dimensional data blocks.

Abstract: A digital image displaying system includes a DPF and an electronic device communicating with the DPF. The DPF has identification information. The electronic device includes a DPF detecting submodule, a image storing submodule for storing digital image files, a DPF managing submodule, and an information transmitting submodule. The DPF detecting submodule detects identification information of the at least one DPF, the DPF managing submodule stores the identification information therein, the information transmitting submodule transmits network location paths of the digital image files of the image storing submodule to the at least one DPF, the at least one DPF receives the network location paths and displays the digital image files stored in the image storing submodule according to the network location paths. A method for displaying digital image files is also provided.

Abstract: Systems and methods for addressing memory using non-power-of-two virtual memory page sizes improve graphics memory bandwidth by distributing graphics data for efficient access during rendering. Various partition strides may be selected for each virtual memory page to modify the number of sequential addresses mapped to each physical memory partition and change the interleaving granularity. The addressing scheme allows for modification of a bank interleave pattern for each virtual memory page to reduce bank conflicts and improve memory bandwidth utilization. The addressing scheme also allows for modification of a partition interleave pattern for each virtual memory page to distribute accesses amongst multiple partitions and improve memory bandwidth utilization.

Abstract: A method and system for performing texture mapping across adjacent texture maps. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of determining whether a texel crosses a boundary of a first texture map, examining a first texture state identifier associated with the first texture map, and requesting for a second texture state identifier associated with a second texture map that is adjacent to the first texture map to enable traversal to the second texture map to access the texel if the first texture state identifier includes a mode indicative of wrapping to an adjacent texture map and texture adjacency information that points to a second texture map.

Abstract: A method for processing display data includes: storing an image data in a plurality of first-type memories by taking scanning line data as a unit; providing one of the scanning line data stored in a particular memory of the first-type memories to one of a plurality of second-type memories, the particular memory being one of the first-type memories, which are not receiving and storing the image data; and outputting the scanning line data stored in the second-type memories. Time periods for outputting the scanning line data of the image data from the second-type memories are not overlapped.

Abstract: An image processing apparatus capable of performing flexible, high speed processing, wherein a memory region emptied due to a change of display resolution can be used as a texture memory, increase of an overhead such as switching pages can be prevented, and a decline in the performance is not caused. A built-in DRAM inside a semiconductor chip has a configuration for storing display data and the texture data required by at least one graphic element. The texture data can be stored in portions other than the display regions, so the built-in DRAM can be used efficiently and an image processing apparatus achieving both high speed operation and a reduction of power consumption can be realized.

Abstract: In systems and methods for graphic reproduction of an image including textural information, multiple rows or blocks of texture data can be retrieved from system memory in response to the single read command. In this manner, efficient use of system bus is achieved, and an increase in the texture cache hit ratio is realized, leading to more efficient system operation, and reduced system bus usage for texture data retrieval.

Abstract: A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.

Abstract: An apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a clipping unit, a read-only memory that is connected to the clipping unit, a read-write memory that is connected to the clipping unit, and an addressing unit that is connected to the read-only memory and the read-write memory. The read-only memory is configured to store a clipping program, and the read-write memory is configured to store a patch program. The addressing unit is configured to selectively address one of the read-only memory and the read-write memory based on a set of input conditions.

Abstract: Methods and computer readable media for generating displays of user-defined blocks of networking addresses on a map of an associated address space are provided. Each block of networking addresses is described in a user-defined table with a start address and a map size. The display for each block of network addresses may be rendered on the map at a location based on the relative position of the start address within the associated address space and of a size based on the mask size in relation to the associated address space.

Abstract: A reconfigurable address generation circuit for image processing is configured to an arbitrary state based on configuration data generates a read address for reading out image data of pixel units having a plurality of rows and columns from a memory which stores image data. As the configuration data, there are set a X, Y count end value of the read out pixel unit, a width value of the image in the memory, and edge information for clip processing. The address generation circuit has X counter; Y counter; an X, Y clip processing circuits which convert the count value of the X, Y counter according to the left, right top and bottom edge information; and an address calcuration circuit which generates the reading out address, based on the count values from the X and Y clip processing circuits and the width value.

Abstract: Methods, apparatuses, and systems are presented for modifying data in memory associated with an image, involving processing data operations in a pipelined process affecting data in memory corresponding to the image. The data operations include a first data operation involving a first read operation followed by a first write operation, and a second data operation involving a second read operation followed by a second write operation. After starting the first read operation, a determination is made whether data associated with the first data operation overlaps with data associated with the second data operation. If a data overlap occurs, the second read operation is started after the first write operation is completed, and if no data overlap occurs, the second read operation is started before the first write operation is completed.

Abstract: A method for circularly accessing a plurality of memory addresses, using a sequence of values comprises determining a plurality of values, the number of values in the plurality of values being m, each value being represented by a predefined number of bits n. The method further comprises identifying in a register (20) of a processor, comprising a plurality of addressable bits ordered by significance, a sequence of m times n consecutive bits, thus having defined a set of m units (21, 22, 23, 24) of n consecutive bits each. It involves initializing each unit of the set of units with the bits representing a different value of the plurality of values, and rotating the identified bits of the register (20) with a number of bits equal to an integer multiple of n. The method also comprises reading a unit for obtaining a value represented by the unit.

Abstract: A method to convert line-based pixel data from an imager, e.g. a video camera into block-based pixel data with a minimum of buffer memory size has been achieved. Key of the invention is that as soon pixel data are read-out of a buffer memory, pixel data of the next image are written to the same position of the buffer memory as the pixels, which have been just read-out have been located. While in prior art the buffer memory required a capacity to store two images is, using the method invented, only a capacity to store one image required. A method to convert line-based pixel data for an image application reading-out column-wise has been illustrated in detail. This general method can be used for a multitude of image transformations and image compression methods e.g. for compression of pixel data as JPEG, for mirroring, tilting, rotating etc. of line-based pixel data.

Abstract: An address processing section allocates addresses of desired data in a main memory, input from a control block, to any of three hit determination sections based on the type of the data. If the hit determination sections determine that the data stored in the allocated addresses does not exist in the corresponding cache memories, request issuing sections issue transfer requests for the data from the main memory to the cache memories, to a request arbitration section. The request arbitration section transmits the transfer requests to the main memory with priority given to data of greater sizes to transfer. The main memory transfers data to the cache memories in accordance with the transfer requests. A data synchronization section reads a plurality of read units of data from a plurality of cache memories, and generates a data stream for output by a stream sending section.

Abstract: A method and circuit for displaying an image by activation of pixels of an array screen based on an image stored in digital form in memory point rows of a frame memory, having a stand-by mode that provides, at a frequency proportional to the display frequency, a cyclic succession of offset values; and for each row address of the frame memory, activating pixels of a screen line associated with said address offset by a same offset value based on the read states of the row associated with the address, and/or activating pixels of a screen line associated with the row address based on the read states of the frame memory row associated with the address offset by a same offset value.

Abstract: A screen creating device includes a screen creating section and an address assigning section. The screen creating section forms a screen including a display element for showing a condition under which data is read out of or written in a region of a memory specified by an address. The address assigning section assigns a particular address to the display element so as to cause the display element to display a condition of read/write of data of the particular address. Further, the screen creating section displays an address list for showing a usage condition of the address, as well as a screen creating region for creating the screen.

Abstract: A color data signal (DATA) and the control signal (CTL) are supplied from a central processor to a display controller, and an address conversion parameter included in the control signal (CTL) is stored in a control register 5. In accordance with the address conversion parameter, display address generating means 6 performs address conversion to generate a display address, and in accordance with the display address, the color data signal (DATA) is stored in a primary storage means 7. Thereafter, an image signal is outputted via image signal outputting means 8 to a display panel. This makes it possible to provide the display controller which can reduce a mounting area and power consumption and reduce the load of a processing on the central processor which performs a processing for editing image data.

Abstract: A data processing system and method in which, by way of example, a memory system is coupled to a video game program processing system. The video game program processing system has a predetermined address space for executing programs stored in a program memory portion of the memory system. The contents of a plurality of storage locations determine a configuration of the memory system depending on which of a plurality of different game programs is to be executed by the video game program processing system.

Abstract: There are provided a drawing device and an information processing apparatus which are capable of reading out texture data from a memory at a high speed. A storage circuit stores respective information items of each of texture pixels constituting the texture data and at least one texture pixel in a vicinity of the each of the texture pixels, in a continuously-accessible region thereof. An address calculation circuit calculates, based on texture coordinates corresponding to each pixel of the polygons, an address where a corresponding set of the information items are stored. A readout circuit reads out the corresponding set of the information items from the address calculated by the address calculation circuit. A synthesis circuit synthesizes the corresponding set of the information items read out by the readout circuit. A drawing circuit draws, based on texture pixel information synthesized by the synthesis circuit, a corresponding pixel of the polygons.

Abstract: A system and method for decoding memory addresses for accessing a memory system having a plurality of blocks of memory for storing data at addressable memory locations. Memory addresses are decoded to access the addressable memory locations of a first block of memory in accordance with a first memory address allocation format and the memory addresses are decoded to access the addressable memory locations of a second block of memory in accordance with a second memory address allocation method different from the first memory address allocation format.

Abstract: A format conversion apparatus which converts image data of a band interleave format into image data of a band separate format is provided. The apparatus includes a memory which stores image data of a band interleave format; and a converting module which reads the memory by increasing a read address of the memory for each stride, and converts the image data of the band interleave format into image data of a band separate format.

Abstract: One embodiment relates to a method for dynamic tuning of a user-space process. The method attaches to the user-space process. Load-time and compile-time base addresses of a data section of an object to be tuned are read. An offset to a symbol to be tuned is determined, and an effective address of the symbol is computed. A new value of the symbol is then written. Other embodiments and features are also disclosed.

Abstract: Methods to manipulate the mobile wireless device screen more efficiently are provided. The method and devices allow a graphical user interface to be used more efficiently on a mobile handset with limited processing ability. A graphical user interface can be implemented on a mobile wireless device efficiently by limiting processing to only the areas of the display screen on the mobile wireless device that is changing. For example, if a graphical item is to be displayed on the display screen the value in the display screen memory location that will be covered by the graphical item can be stored for future use. If the graphical item is later moved the stored value can be retrieved and efficiently written to the display without the need to recalculate what was behind the graphical item.

Abstract: A display controller is provided. The display controller is configured to provide an indirect addressing mode to access a memory location within the display controller. The display controller includes a first pin configured to enable access to one of a register of the display controller or a memory region of the display controller based upon a logical level of a first signal received by the first pin. A second pin is included. The second pin is configured to define the access to the register or the memory region as one of address information or data based upon a logical level of a second signal received by the second pin. The display controller includes an extra pin mode module configured to enable the first signal to select the data to access memory without accessing a register block. A device and methods for implementing an indirect addressing mode is also provided.

Abstract: The scan converter comprises first and second memories 3, 7, a frame memory 5; having a write period and a read period, a video data input circuit 2 for writing data at a first transfer rate into the memory 3, a video data output circuit 8 for outputting the data from the memory 7 at a third transfer rate. The transfer rate between the memories 3, 7 and the memory 5 is twice as fast as the first or third transfer rate, whichever is faster, and the memories 3 has data storage capacities greater than an amount of the data to be written into the memory 5 in each write period, and the memories 7 has data storage capacities greater than an amount of the data to be read from the memory 5 in each read period.

Abstract: A method of and apparatus are provided for saving video data.

Abstract: intercepted in order to determine if the modification will result in an aperture memory address mapping to a region of trusted memory. If it is determined that the GART modification will not result in a mapping to a portion of trusted memory, then the GART modification is allowed. If it is determined that the GART modification will result in a mapping to a portion of trusted memory, then the modification is not allowed and an alarm is raised in the system.

Abstract: A graphics processing system has a cache which is partitionable into two or more slots. Once partitioned, the slots are dynamically allocatable to one or more texture maps. First, number of texture maps needed to render a given scene is determined. Then, available slots of the cache are allocated to the texture maps. Sometimes, more slots are allocated to the largest texture map. At other times, more slots are allocated to the texture map which is likely to be used most often. The slots can also be allocated equally to all of the texture maps needed.

Abstract: A method of addressing bistable nematic liquid crystal devices is provided. The method is suitable for implementation using commercially available STN drivers. The method involves applying one of at least two data waveforms simultaneously to each column electrode whilst an active row waveform is applied to an active row and a non active row waveform is applied to all other rows. The resultant waveform at the pixels on the active row comprises a blanking portion sufficient to cause the liquid crystal material to blank, irrespective of which data waveform is applied, immediately followed by a discriminating portion which allows for selective latching depending on the data waveform applied.

Abstract: Methods and apparatus for use with AGP-capable computer systems are disclosed. Since each AGP-capable chipset can have a unique range of graphics port aperture sizes that it supports, current graphics port aperture drivers are chipset-specific, with hard-coded tables of supported graphics aperture sizes. Described herein is a driver that dynamically ascertains the range of supported graphics aperture port sizes for an attached AGP-capable chipset, thus allowing this driver to be ported between different chipsets without manual reconfiguration and recompiling. The method employed in the driver sends one or more test aperture size values to a register resident in the chipset, and then reads what is written to see if the chipset changed any of the bits of the test value. The method infers supported sizes from examining which, if any bits, were changed by the chipset.

Abstract: A display control system includes multiple image signal sources and image display devices. At the time of performing control for displaying picture signals from the multiple signal sources connected on respective sending lines to respective multiple areas on screens of image display devices, image display attributes information for each display area is stored in a per-area display attributes information storing unit, and an identification number of input pictures is obtained by an input signal identification signal obtaining unit. Based on the obtained identification signals, display selection information for appropriating the picture signals to the multiple display areas is created at a display signal selecting unit. The stored image display attributes information and the created display selection information are notified to the multiple signal sources connected to the respective sending lines.

Abstract: A memory control unit adjusts and sets the address of an image data area in the memory space of a memory and the address of a window area adjacent to the memory area, using a memory controller. The memory control unit stores data, other than image data that is supplied, at a specified address location and, when a control signal is sent to the memory, reads out the image data, including data stored in the window area, from the memory. The data that is read out from the window area is inserted into a predetermined position during a blanking period.

Abstract: A deferred graphics pipeline processor comprising a texture unit and a texture memory associated with the texture unit. The texture unit applies texture maps stored in the texture memory, to pixel fragments. The textures are MIP-mapped and comprise a series of texture maps at different levels of detail, each map representing the appearance of the texture at a given distance from an eye point. The texture unit performs tri-linear interpolation from the texture maps to produce a texture value for a given pixel fragment that approximates the correct level of detail. The texture memory has texture data stored and accessed in a manner which reduces memory access conflicts and thus improves throughput of said texture unit.

Abstract: A three dimensional parallax drawing system for use in three dimensional graphics or virtual reality is disclosed. The parallax drawing system includes a three dimensional address generator which generates the original X-axis, Y-axis and Z-axis addresses of an image, and an address correction circuit for producing a corrected X-axis address in response to the original X-axis and Z-axis address outputs from the address generator. Also included is an address selection circuit for selecting either the original X-axis address supplied from the three dimensional address generator or the corrected X-axis address from the address correction circuit as a resultant X-axis address in response to a stereo graphic mode request signal. A frame buffer address generator is provided for converting the resultant X-axis address received from the address selection means and the Y-axis address received from the three dimensional address generator into the frame buffer linear address.

Abstract: A method and computer program are provided for controlling access to a memory device wherein, even with a complex data storage structure, access is made to memory areas within the memory device with a minimal number of selection inputs required for selection of a desired memory area.

Abstract: A method and apparatus for buffering 2-dimensional graphical image data to be supplied to a scrolling display controller. A 2-dimensional, circularly addressed linear data buffer is used to store a portion of an entire image. The data buffer is larger than the amount of data displayed at one time. A user enters scrolling commands and the display scrolls around the data initially in the buffer. New data is loaded into the buffer as the displayed data approaches the edge of the buffered data.

Abstract: A central processing unit (CPU) configured to apply an intelligent wait methodology is provided. The CPU includes a chip select module that defines a chip select signal associated with an external device. The chip select module includes an address space configured to store addresses associated with the external device. The address space provides an address section. The address section is associated with the external device and is subdivided into address sub-sections associated with an address range and assigned through the chip select signal. The address sub-sections are configured to determine a bus cycle based on an association with either the CPU monitoring a wait line between the CPU and the external device or the CPU waiting for a number of wait states. A device and a method for optimizing a bus cycle length between a CPU and an external device in communication with the CPU are provided.

Abstract: A method of addressing multistable nematic liquid crystal devices, in particular bistable nematic liquid crystal devices is provided. The method is a line at a time addressing scheme where one of at least two data waveforms is applied simultaneously to each of the column electrodes whilst a strobe waveform is applied to a row. The strobe waveform comprises a blanking portion sufficient to cause the liquid crystal material to blank, irrespective of which data waveform is applied, immediately followed by a discriminating portion which is such that in combination with an appropriate data waveform allows for selective latching. At least part of both the blanking portion and the discriminating portion are applied during the line address time for the particular row of interest.

Abstract: A data processing system and method in which, by way of example, a memory system is coupled to a video game program processing system. The video game program processing system has a predetermined address space for executing programs stored in a program memory portion of the memory system. The contents of a plurality of storage locations determine a configuration of the memory system depending on which of a plurality of different game programs is to be executed by the video game program processing system.

Abstract: Prior to executing a program on a fragment, a conflict detection unit, within a fragment processor checks if there is a position conflict indicating a RAW (read after write) hazard may exist. A RAW hazard exists when there is a pending write to a destination location that source data will be read from during execution of the program. When the fragment enters a processing pipeline, each destination location that may be written during the processing of the fragment is entered in conflict detection unit. During processing, the conflict detection unit is updated when a pending write to a destination location is completed.

Abstract: A 3D rendering texture caching scheme that minimizes external bandwidth requirements for texture and increases the rate at which textured pixels are available. The texture caching scheme efficiently pre-fetches data at the main memory access granularity and stores it in cache memory. The data in the main memory and texture cache memory is organized in a manner to achieve large reuse of texels with a minimum of cache memory to minimize cache misses. The texture main memory stores a two dimensional array of texels, each texel having an address and one of N identifiers. The texture cache memory has addresses partitioned into N banks, each bank containing texels transferred from the main memory that have the corresponding identifier. A cache controller determines which texels need to be transferred from the texture main memory to the texture cache memory and which texels are currently in the cache using a least most recently used algorithm.

Abstract: A method and apparatus for efficiently rasterizing graphics is provided. The method is intended to be used in combination with a frame buffer that provides fast tile-based addressing. Within this environment, frame buffer memory locations are organized into a tile hierarchy. For this hierarchy, smaller low-level tiles combine to form larger mid-level tiles. Mid-level tiles combine to form high-level tiles. The tile hierarchy may be expanded to include more levels, or collapsed to included fewer levels. A graphics primitive is rasterized by selecting an starting vertex. The low-level tile that includes the starting vertex is then rasterized. The remaining low-level tiles that are included in the same mid-level tile as the starting vertex are then rasterized. Rasterization continues with the mid-level tiles that are included in the same high-level tile as the starting vertex. These mid-level tiles are rasterized by rasterizing their component low-level tiles.

Abstract: An opaque memory region for a bridge of an I/O adapter. The opaque memory region is inaccessible to memory transactions which traverse the bridge either from a primary bus to secondary bus or secondary bus to primary bus. As a result, memory transactions which target the opaque memory region are ignored by the bridge, allowing for the same address to exist on both sides of the bridge with different data stored in each. The implementation of the opaque memory region provides a means to complete memory transactions within I/O adapter subsystem memory, hence, relieving host computer system memory resources. In addition, a number of I/O adapters can be used in a host computer system where the host and all the I/O devices use some of the same memory addresses.

Abstract: A system and method are disclosed to allow the tiling of sample jitter patterns to be independent of the tiling of clustered graphics accelerators. Each accelerator uses an x,y “bias” offset to shift the origin of the jitter pattern within the sample space region addressed by the accelerator. In this way, multiple accelerators may be programmed so that their jitter patterns integrate into one global pattern without discontinuities at the region boundaries.

Abstract: In a method and buffer device for data stream transformation, a buffer memory is configured into addressable locations for writing an input data stream therein, a label memory is used for storing write and read labeled positions, and a buffer controller is connected to the buffer memory and the label memory. The buffer controller controls the writing of the input data stream into the addressable locations of the buffer memory according to the write labeled positions and a write data sequence, calculates the read labeled positions corresponding to the write labeled positions in accordance with the write data sequence and a read data sequence, updates the read labeled positions stored in the label memory, and reads data from the addressable locations of the buffer memory with reference to the read labeled positions stored in the label memory so as to generate an output data stream.

Abstract: A circuit for outputting area pattern bits from an area pattern array. The circuit includes a first stage, second stage and third stage. The first stage is configured to output N adjacent scan lines from a 2N×2N area pattern array based on a first address. N is a positive integer. The second stage is configured to receive the N adjacent scanlines and to select an N×N block from the N adjacent scanlines based on a second address. The third stage is configured to (a) select an (N/2)×N region of bits from the N×N block and load bits of the (N/2)×N region into a set of pixel tag outputs in a first mode, and (b) select an N×(N/2) region of bits from the N×N block and load bits of the N×(N/2) region into the set of pixel tag outputs in a second mode.

Abstract: A system is provided for storing pixel data associated with a predetermined pixel region. The system is configured to store pixel data in a predetermined block of memory along with a fill check bit indicative of whether or not values for each pixel within the pixel region are the same as a predetermined reference pixel. The system also provides for the generation of a stream of pixel data corresponding to a pixel region by outputting a value for a pixel within the region that is equal to the reference pixel when the fill check bit is set.

Abstract: A logic enhanced memory that may be used in a video graphics system is presented. The logic enhanced memory includes an operation block that performs a number of operations on a block-by-block basis such that parallel processing results. The operations performed by the operation pipeline include blending operations for fragment blocks received from a graphics processing circuit, where the fragment blocks include pixel fragments generated by rendering graphics primitives. Other operations include selective reads and writes to the memory array, clearing functions, and swapping functions. Mask values included in the commands executed to control the operation pipeline allow for selectivity with respect to portions of the data packets, or blocks, to which the operations are applied.

Abstract: A Memory Interface and Video Attribute Controller (MIVAC) is inserted between a dynamic RAM (DRAM) capable of a consecutive data read operation, such as the operation associated with the static column mode, page mode, or nibble mode, and a graphic processor to provide a parallel data processing. A serial data transfer is executed on each data bus between the MIVAC and the DRAM, whereas parallel data transfer is conducted between the MIVAC and the graphic processor. As a result, the graphic processor can be configured with a reduced number of DRAMs so that the graphic processor operates without paying attention to the consecutive data read mode of the DRAM.