Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a data buffer, an inter-track interference response circuit, and an inter-track interference signal estimator circuit. The data buffer is operable to store a previous track data set. The inter-track interference response circuit is operable to estimate an inter-track interference response from the previous track data set based at least in part on the previous track data set and a current track data set. The inter-track interference signal estimator circuit is operable to calculate an inter-track interference from the previous track data set based at least in part on the previous track data set and the inter-track interference response from the previous track data set.

Abstract: A disk drive is disclosed having a plurality of disk surfaces, wherein each disk surface comprises a plurality of data tracks, and each data track comprises a plurality of data sectors. When a read command is received from a host, data is read from first and second data sectors on first and second disk surfaces, respectively, in response to the read command, wherein the first data sector stores data at a first data rate, and the second data sector stores data at a second data rate substantially less than the first data rate. The data is transferred to the host at a substantially constant average transfer rate. In this manner, the disk drive does not appear abnormal to a benchmark program that reads a plurality of data sectors across multiple disk surfaces.

Abstract: A hard disk drive that includes a disk with servo bits. The hard disk drive also includes a central processing unit that performs a servo routine using the servo bits, and a separate a notch hardware engine that is utilize by the central processing unit to perform a notch filter function in the servo routine. Off-loading the notch filter function onto a hardware engine reduces the overhead on the central processing unit when performing a servo routine. Utilizing the notch hardware engine can improve the speed of the central processing unit by a factor of 10×.

Abstract: Systems and techniques associated with signal processing are described. A described technique includes generating asymmetry vectors that model asymmetry in a received analog signal, including an effect of asymmetry spreading in a read channel and selecting at least two different indicators of asymmetry based on the asymmetry vectors. The technique can include using the selected indicators of asymmetry to compensate for one or more asymmetries associated with the analog signal.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a decoder circuit providing a decoded output, and a dynamic scalar calculation circuit that determines a first dynamic scaling value and a second dynamic scaling value based at least in part on the decoded output. A first multiplier circuit multiplies the decoded output by the first dynamic scaling value and provides a first scaled output. A detector circuit receives the first scaled output and provides a detected output. A second multiplier circuit multiplies the detected output by the second dynamic scaling value and provides a second scaled output.

Abstract: A method and apparatus is provided for extending a read bandwidth and increasing a high-frequency signal-to-noise ratio (SNR) of a front-end of a read path of a hard disk drive (HDD) by introducing a high impedance section at the front-end of the read path. The high impedance section may mitigate capacitive effects found at the front-end of the read path, thereby improving signal transfer by extending the read bandwidth.

Abstract: Impedance compensation features are used along the transmission-line path between a transmitter/driver/source and the receiver/transducer to compensate for the impedance discontinuities or mismatches (for example, those caused by physical interconnection features) and/or to improve the frequency response of the signal transfer along the transmission line. The impedance compensation features are non-uniformities with impedance characteristics selected to compensate for the target impedance discontinuities. The compensation features can be non-uniformities (geometric structures designed to have specific impedance characteristics) in the electrically conductive traces that are integrated in the interconnect transmission line between the transmitter/driver/source and the receiver/transducer. The effective impedance level of the transmission line can be lowered or raised using the compensation features.

Abstract: Various embodiments of the present invention provide systems and methods for reducing low frequency loss in a magnetic storage device. For example, some embodiments provide data processing circuits that include: an input circuit, a processing circuit, a data detection circuit, and a baseline compensation circuit. The input circuit receives a first data input and provides a second data input. The input circuit excludes low frequency energy exhibited in the first data input from the second data input. The processing circuit generates a representation of the second data input, and the data detection circuit generates a representation of the first data input based at least in part on the representation of the second data input.

Abstract: A data storage apparatus includes: a medium for storing data having synchronization marks and data blocks, the synchronization mark and the data block being allocated alternately in the circumference direction of the medium; a head writing data into or reading out data from the medium; and a processor for executing a process including: reading out synchronization marks, measuring time for the head to pass through each of the data blocks based on signals read out from each of the synchronization marks in the circumference direction, generating write/read clock for each of the data blocks, which is continuously changing in speed, by calculating difference in time for the head to pass through the each one of the data blocks and its adjacent one of the blocks on the basis of the time measured, and writing data into or reading out data from the medium in synchronization with the write/read clock.

Abstract: An apparatus including one or more reader circuits, one or more writer circuits, and a loopback channel. The one or more reader circuits may be configured to read data from a magnetic medium. The one or more writer circuits may be configured to write data to the magnetic medium. The loopback channel is coupled between the one or more reader circuits and the one or more writer circuits.

Abstract: A system in one embodiment includes multiple analog inputs for receiving readback signals, an analog to digital converter coupled to each of the analog inputs for converting the readback signals to digital signals, a buffer coupled to outputs of the analog to digital converters for at least temporarily storing the digital signals, and a digital processing section also coupled to outputs of the analog to digital converters for processing the digital signals for reconstructing data therefrom. A method in one embodiment includes receiving multiple channels of analog readback signals from a magnetic head, converting the analog signals in each channel to digital signals, buffering the digital signals, and outputting the buffered digital signals. A method in another embodiment includes receiving a readback waveform from a magnetic storage device, reducing a frequency offset of the readback waveform, and generating a synchronized, oversampled waveform from the readback waveform.

Abstract: A method and apparatus to read information from an information storage medium using a read channel, where that read channel includes a data cache. The invention generates an analog waveform comprising the information, and provides that analog waveform to a read channel, and generates a digital signal from that analog waveform using one or more first operating parameters. The method error corrects that digital signal at an actual error correction rate, and determines if the actual error correction rate is greater than an error correction rate threshold. If the actual error correction rate exceeds the error correction rate threshold, then the method captures the digital signal, stores that captured data in a data cache, reads that digital signal from the cache, generates one or more second operating parameters, and provides those one or more second operating parameters to the read channel.

Abstract: In a method for causing data to be written to a non-volatile medium, first data to be encoded and written in a sector of the non-volatile medium as a codeword is transmitted to a write or read/write channel device, and a write gate signal corresponding to the sector is asserted. Asserting the write gate signal indicates to the write or read/write channel device when to write the codeword to the sector. While asserting the write gate signal to cause the codeword to be written, second data to be encoded and written to the non-volatile medium is transmitted to the write or read/write channel device.

Abstract: A disk drive is disclosed comprising a disk, a head for writing data to the disk, and control circuitry coupled to the head, the control circuitry comprising a signal amplifier outputting a first signal comprising an offset voltage, the control circuitry operable to determine a state signal based on comparing the first signal to a reference signal, increase a M-bit digital count value in response to a first state of the state signal, decrease the M-bit digital count value in response to a second state of the state signal, and determine a first analog signal based on N bits of the digital count value, wherein the first analog signal adjusts the offset voltage and M>N.

Abstract: A read-channel module including a VGA module to amplify a signal based on a variable gain, an ADC module to generate a sample based on the amplified signal, and an AGC module to control the variable gain of the VGA module. A gain adjusting module generates (i) a first gain and (ii) a second gain when an amplitude of the sample is (i) less than or equal to a first predetermined threshold and (ii) greater than or equal to a second predetermined threshold, respectively. The AGC module (i) increases and (ii) decreases the variable gain of the VGA module based on (i) the first gain and (ii) the second gain, respectively. The gain adjusting module generates the first gain and the second gain by (i) multiplying a present gain of the AGC module by a predetermined multiplier or (ii) adding a predetermined offset to the present gain.

Abstract: Embodiments of the present invention help to reduce the occurrence of read hard errors in a hard disk drive (HDD). According to one embodiment, a HDD rewrites data on all data tracks of a block M when the number of write operations to the block consisting of continuous plural data tracks. The HDD further rewrites data on continuous plural data tracks and adjacent to the block. Since the number of write operations is counted every block, a memory area to register the number of write operations can be reduced.

Abstract: Various systems and methods for peak signal detection. As one example, a method for peak signal detection that includes receiving a signal is disclosed. The received signal includes a signal region where the signal is increasing in amplitude, another signal region where the signal is decreasing in amplitude, and a transitional signal region coupling the first two signal regions. In some cases, the transitional region is of zero duration and the signal transitions directly from the increasing region to the decreasing region. The method further include calculating a distance between the signal region of increasing amplitude and the signal region of decreasing amplitude, and determining a peak of the received signal that is one half the distance from the signal region of increasing amplitude.

Abstract: A method of protecting information written to a recording medium includes magnetizing the recording medium to form a first magnetic pattern corresponding to information to be stored, and magnetizing the recording medium to form a protective magnetic pattern having a phase difference of 180° from the first magnetic pattern at a position adjacent to where the first magnetic pattern is formed, with adjacent bits of the first magnetic pattern opposite and the protective magnetic pattern opposite to each other.

Abstract: According to one embodiment, a disk storage apparatus includes a data recording module and a controller. The data recording module is configured to record a first sync mark and a second sync mark in each data sector provided on a disk. The controller is configured to control the data recording module, causing the data recording module to omit recording the second sync mark in one of segments into which the data sector is split.

Abstract: According to one embodiment, a magnetic head for perpendicular recording includes a first magnetic core includes a main pole configured to produce a recording magnetic field, and a return pole configured to reflux magnetic flux from the main pole to form a magnetic circuit in conjunction with the main pole, a first coil configured to excite magnetic flux in the magnetic circuit, side shields arranged individually on opposite sides of the main pole transversely relative to a track so as to be magnetically separated from the main pole and formed integrally with the return pole, a second magnetic core configured to form a physically closed magnetic path, a part of which comprises the return pole, and a second coil wound around the second magnetic core and configured to excite magnetic flux in the closed magnetic path.

Abstract: A synchronizing apparatus, which controls, by a PLL circuit, a sampling clock to be used to sample input data and synchronizes a phase of the sampling clock with a target phase that is desirable for sampling the input data, includes: phase error detection means for detecting a phase error from sampling data and the sampling clock, the sampling data being sampled from the input data at timing of the sampling clock; frequency error detection means for detecting, based on a differential coefficient obtained as a result of detecting the phase error, a frequency error; and frequency correction means for correcting a frequency of the sampling clock such that the detected frequency error becomes close to zero by adding a frequency correction value to an integral term of a loop filter of the PLL circuit, the frequency correction value being calculated based on the frequency error.

Abstract: A system for removing low frequency disturbance signals from a control system output. The system includes a controller, a mixer, a feedback loop, and a low pass filter. The controller generates a control signal. The mixer is connected to the controller and receives the control signal from the controller. The feedback loop connects an output of said mixer to an input of the mixer. A low pass filter in the feedback loop allows low frequency disturbance signals in the control signal output from the mixer to pass through the feedback loop and to be added to the control signal by said mixer for handling by the controller.

Abstract: Methods and apparatus for detecting L-bit sync words occurring at N-bit intervals in PPM-encoded servo pattern read signals read in magnetic tape drives. A soft output detector processes the PPM-encoded servo pattern read signal to produce a series of soft output samples corresponding to respective bits encoded in the servo pattern. A sync word detector then produces block correlation values for respective positions of a sliding L-sample block in the series of soft output samples by (i) calculating at each block position bit correlation values indicating correlation between respective samples and corresponding bits of the sync word and (ii) summing each bit correlation value minus a predetermined function of the corresponding sample value. The sync word detector then detects a sync word at the block position with the maximum block correlation value in an (N+L?1)-sample sequence of the series of soft output samples.

Abstract: The present disclosure includes apparatus, systems and techniques relating to detecting sync marks. In some implementations, an apparatus includes phase locking circuitry that includes a phase calculator to identify a phase of sampled data, and a phase-locked loop to generate an output signal and phase-lock the generated output signal with the calculated phase of the sampled data to produce a phase-locked signal. The apparatus includes detector circuitry to receive phase information of the phase-locked output signal. The detector circuitry includes a detector to generate a stream of decision bits for the sampled data with each bit in the stream being associated with a different phase. The detector circuitry includes an output selector to select at least one bit from the stream based on the received phase information of the phase-locked output signal.

Abstract: A method to map defects is provided. A select data track of a storage medium is scanned for a defect. At least one data wedge affected by the defect on the select data track is identified. Each data wedge includes available area for writing user data defined between two servo wedges that include position information. The at least one affected data wedge is identified as unusuable.

Abstract: A reading element of a magnetic head has a first magnetoresistive effect part (first MR part) and a second magnetoresistive effect part (second MR part), an electrical resistance of the first MR part changing according to an external magnetic field applied to a first magnetic field sense area, an electrical resistance of the second MR part changing according to an external magnetic field applied to a second magnetic field sense area. A width of the second magnetic field sense area in a track width direction of the recording medium is larger than a width of the first magnetic field sense area in the track width direction, and a phase of change in the electrical resistance of the second MR part with respect to the external magnetic field substantially reverses to or substantially the same as a phase in the electrical resistance of the first MR part.

Abstract: A device, method, and computer program product are provided for migrating pieces of data from a first recording location to a second recording location based on access frequency. The device comprises an obtaining unit for obtaining, for each of the pieces of data, first information indicating the number of times any data has been read from the first recording location after the piece of data is written to the first recording location and second information indicating the number of times the piece of data has been read from the first recording location. Moreover, the device comprises a tracking unit for tracking access frequency with respect to each of the pieces of data using the first information and the second information. Furthermore, the device comprises a determining unit for determining recording positions of each of the pieces of data in the second recording location based on the tracked access frequency.

Abstract: According to one embodiment, a magnetic recording head includes a main magnetic pole, a shield, and a stacked structure body. The shield is provided to oppose the main magnetic pole. The stacked structure body is provided between the main magnetic pole and the shield. The stacked structure body includes a first magnetic layer, a second magnetic layer, and an intermediate layer. The first magnetic layer has coercivity lower than a magnetic field applied from the main magnetic pole. A size of a film surface of the second magnetic layer is larger than a size of a film surface of the first magnetic layer. The intermediate layer is provided between the first magnetic layer and the second magnetic layer and is made of a nonmagnetic material. A current is configured to pass between the first magnetic layer and the second magnetic layer.

Abstract: The present invention provides a technique for converting burst data to digital data, applying FFT operation to 2n (n is an integer) pieces of digital data in response to any start signal synchronized with a sector signal, applying a window function centered around data corresponding to a frequency of a burst data signal component before the FFT operation, and performing head positioning based on a result as the detected value of the burst data.

Abstract: A method to decode linear position (“LPOS”) information encoded in a sequential information storage medium, by detecting each of one or a plurality of sequential first LPOS servo patterns encoded in a first servo band using a first servo sensor in communication with a first servo channel. While detecting that one or a plurality of first LPOS servo patterns, the method fails to detect (n) second LPOS servo patterns encoded in a second servo band. The method determines a value for (n), and then syncs the first servo channel with the second servo channel using that value of (n).

Abstract: A power-saving method adapted in a hard disk in a computer system having a CPU and a memory module is provided. The power-saving method comprises the following steps. A data-to-be-written is transferred from the memory module through the CPU to the hard disk filter. A determining module is provided to determine whether a data access frequency of the computer system exceeds a threshold value. When the data access frequency exceeds the threshold value, the determining module further determines whether a request-queuing time exceeds an idle-mode activation time. When the request-queuing time exceeds the idle-mode activation time interval, the data-to-be-written is stored in a temporary storage location by the hard disk filter. When a condition of the computer system is satisfied, the data-to-be-written is written to the hard disk to extend the duration of an idle-mode of the hard disk. A power-saving operating system is disclosed herein as well.

Abstract: Methods, apparatuses, and systems describing digital techniques to decode signals extracted from computer-readable storage media. A digital signal that includes a digital representation of a repeatable runout signal having a magnitude and included in an analog signal is obtained. An estimate of the magnitude of the RRO signal based on the digital signal is determined. The estimate is provided for decoding the digital signal to extract the included data by adapting a detector gain target in accordance with the estimate. The detector gain target is a function of a desired amplitude of the RRO signal.

Abstract: A communications circuit includes a first filter having a corner frequency that is adjustable. A data type identifier that tracks first and second types of data flowing through the communications circuit. A control module that adjusts the corner frequency of the first filter to provide alternating current (AC) coupling during the first type of data and adjusts the corner frequency of the first filter to provide direct current (DC) coupling during the second type of data.

Abstract: Various embodiments of the present invention provide systems and methods for reducing low frequency loss in a magnetic storage device. For example, a data processing circuit is disclosed that includes an amplifier, two filters and a summation element. The amplifier provides an amplified output that is filtered using a first of the two filters to create a first filtered output. The first filtered output is then filtered using the second of the two filters to create a second filtered output. The summation element sums the first filtered output with the second filtered output to provide a pole altered output.

Abstract: Various embodiments of the present invention provide systems and methods for providing a corrected dibit signal. As an example, various embodiments of the present invention provide dibit correction circuits. Such dibit correction circuits include a dibit sample buffer, a maximum sample detector circuit, a side sample detector circuit, and a dibit correction circuit. The dibit sample buffer includes a plurality of samples of an uncorrected dibit signal. The maximum sample detector circuit identifies a maximum sample of the plurality of samples of the uncorrected dibit signal, and the side sample detector circuit identifies a first side sample prior to the maximum sample on the uncorrected dibit signal and a second side sample following the maximum sample on the uncorrected dibit signal.

Abstract: An information reproducing apparatus which reproduces information recorded on a medium includes an asymmetry correction circuit configured to correct an asymmetry of a signal read from a medium. The apparatus also includes a first high pass filter installed before the asymmetry correction circuit and configured to remove noise in the signal by a first cut-off frequency. The apparatus also includes a second high pass filter installed after the asymmetry correction circuit and configured to remove the noise in the signal by a second cut-off frequency, wherein the second cut-off frequency is higher than the first cut-off frequency.

Abstract: In one embodiment, an apparatus comprises two or more slave channels, wherein each one of the slave channels comprises a non-adaptive filter operable to filter an input signal to the slave channel using filter coefficients received from a master channel; and the master channel coupled to each one of the slave channels, wherein the master channel comprises an adaptive filter operable to: for each one of one or more of the slave channels, determine the filter coefficients for the slave channel using the input signal to the slave channel; and send the filter coefficients to the slave channel.

Abstract: A method and apparatus to read information from an information storage medium using a read channel, where that read channel includes a data cache. The invention generates an analog waveform comprising the information, and provides that analog waveform to a read channel, and generates a digital signal from that analog waveform using one or more first operating parameters. The method error corrects that digital signal at an actual error correction rate, and determines if the actual error correction rate is greater than an error correction rate threshold. If the actual error correction rate exceeds the error correction rate threshold, then the method captures the digital signal, stores that captured data in a data cache, reads that digital signal from the cache, generates one or more second operating parameters, and provides those one or more second operating parameters to the read channel.

Abstract: Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds.

Abstract: A disk drive is disclosed comprising a disk and a head actuated radially over the disk, wherein the head generates a read signal. A sampling device samples the read signal to generate a sequence of read signal samples, and an equalizer comprising a plurality of coefficients, equalizes the read signal samples to generate a sequence of equalized samples. A sequence detector detects an estimated data sequence from the equalized samples, wherein the sequence detector operates according to a target response comprising a plurality of target values. Control circuitry adapts the equalizer coefficients by computing error values in response to a difference between expected samples and the equalized samples, computing a gradient in response to a correlation of the read signal samples with the error values, and adjusting at least one of the equalizer coefficients in response to the gradient.

Abstract: A specialized structure measures clock-to-data jitter in an optical memory interface by averaging the result of two second-order estimates of zero crossing using measured signal values on either side of the zero crossing. In one embodiment, a first estimate uses two sample points before the zero crossing and one sample point after while the second estimate uses one sample point before the zero crossing and sample two points after. An existing clock associated with an internal analog-to-digital converter is used to evenly space the samples in time. To simplify the second-order estimate calculations, the three samples of the exemplary embodiment are give x values of ?1, 0, and +1 respectively. Which of the two roots of the second-order estimates is used is based on the slope of the signal at the zero crossing.

Abstract: A system for removing low frequency disturbance signals from a control system output. The system includes a controller, a mixer, a feedback loop, and a low pass filter. The controller generates a control signal. The mixer is connected to the controller and receives the control signal from the controller. The feedback loop connects an output of said mixer to an input of the mixer. A low pass filter in the feedback loop allows low frequency disturbance signals in the control signal output from the mixer to pass through the feedback loop and to be added to the control signal by said mixer for handling by the controller.

Abstract: A storage medium on which servo patterns are encoded to provide lateral and longitudinal position (LPOS) information is provided. Each of the servo patterns includes a servo frame, including first through fourth bursts, which are each independently modulated with multi-level pulse position modulation (PPM) to encode at least one independent bit per burst.

Abstract: A system and method for determining the value of a longitudinal position (“LPOS”) bit of a storage medium. A system comprises a selector that selects a value for a longitudinal position (“LPOS”) bit from a plurality of possible values derived from LPOS information read from a storage medium. A quality determiner that determines a quality value for each of a plurality of LPOS values derived from the LPOS information. The selection of the value for the LPOS bit is based, at least in part, on the quality values.

Abstract: An apparatus and a method of detecting an error symbol in a data storage apparatus so that an error correcting performance of an error correction decoder.

Abstract: A novel magnetic recording medium is disclosed in which a plurality of magnetic data recording layers and navigation layers are separate from one another. By decoupling the navigation and data layers, data may be written to data layers without the need to align the written data along servo tracks. Thus, the data layers may be configured for high recording density. Beneficially, imperfections within the magnetic data layers may also be compensated for by the use of adaptive error correction schemes which vary the encoding/decoding of data during writing/reading based upon the local quality of the recording media.

Abstract: Various embodiments of the present invention provide systems and methods for acquiring timing and/or gain information. For example, various embodiments of the present invention provide data processing circuits that include a sample splitting circuit, a first averaging circuit, a second averaging circuit and a parameter calculation circuit. The sample splitting circuit receives a data input that includes a series of samples that repeat periodically over at least a first phase and a second phase. The sample splitting circuit divides the series of samples into at least a first sub-stream corresponding to the first phase and a second sub-stream corresponding to the second phase. The first averaging circuit averages values from the first sub-stream to yield a first average, and the second averaging circuit averages values from the second sub-stream to yield a second average. The parameter calculation circuit calculates a parameter value based at least in part on the first average and the second average.

Abstract: A hard disk drive is disclosed and related methods of reading/writing data are disclosed. The hard disk drive includes a disk serving as a main data storage medium, and first and second buffers storing data to be stored on the disk, as well as a controller defining a data I/O path in relation to a detected operating state of the hard disk drive.

Abstract: In one general embodiment, a recording system controller includes a controller controlling a timing of flux switching of adjacent pairs of writers such that the writers in a given pair do not switch substantially concurrently, and reducing a current of one of the writers in the pair while the adjacent writer is writing a transition. In another general embodiment, a recording system controller includes a controller controlling a timing of pulse writing of adjacent pairs of writers such that the writers in a given pair do not pulse substantially concurrently. In yet another general embodiment, a method includes controlling a timing of pulse writing or flux switching of adjacent pairs of writers such that the writers in a given pair do not pulse or switch substantially concurrently.

Abstract: A hard disk drive controller includes a buffer block temporarily storing recording data received from a host or reproduced data to be output to the host. A formatter outputs the recording data or the reproduced data and outputs a first control signal and a second control signal based on error information of partial data sectors included in a data sector corresponding to the recording data or the reproduced data. An error correction code block encodes and outputs data corresponding to partial data sectors having no errors in the received recording data based on the first control signal received from the formatter during a write operation and decodes data corresponding to partial data sectors having no errors in the received reproduced data based on the first control signal and outputs the decoded data in response to the second control signal during a read operation.