Abstract: A ceramic electronic device comprises an element body including a ceramic layer and an internal electrode layer, and an external electrode electrically connected to at least one end of the internal electrode layer. The element body includes an interface part at least at a part of a boundary between the external electrode and the ceramic layer. The interface part includes an oxide containing aluminium and an oxide containing boron.

Abstract: An electrode foil for an electrolytic capacitor includes: an anode body including a first metal; a first dielectric layer covering at least a part of the anode body and including an oxide of the first metal; and a second dielectric layer covering at least a part of the first dielectric layer and including an oxide of a second metal. The first metal includes at least one selected from the group consisting of titanium, tantalum, niobium, and aluminum. And the second metal includes at least one selected from the group consisting of silicon, zirconium, hafnium, and tantalum. A thickness T2 of the second dielectric layer is smaller than a thickness T1 of the first dielectric layer.

Abstract: All organic, dielectric polymers with high discharge efficiency at elevated operation temperatures are reported.

Abstract: A thin film high polymer laminated capacitor includes: a laminated chip including dielectric layers, and internal electrode layers including first metal layers including a first metal vapor-deposited on the dielectric layers, and second metal layers including a second metal vapor-deposited on the first metal layers. The dielectric layers and the internal electrode layers being laminated and bonded alternately, and external electrodes formed on one end and the other end of the laminated chip. The laminated chip having a first region having the first metal layers formed on the dielectric layers, which are laminated alternately, and edge regions having the second metal layers formed on layers connected to the one end and layers connected to the other end in the first metal layers, which are laminated alternately, the first region having a capacitor function region, and the edge region having a heavy edge.

Abstract: A method for producing a piezoelectric transducer device is provided, including a membrane including at least one silicon and/or silicon nitride layer; a piezoelectric layer including at least one piezoelectric material with crystalline perovskite structure and arranged on the membrane; first and second electrodes electrically in contact with the piezoelectric layer; and in which the piezoelectric layer is in direct contact with the silicon and/or silicon nitride layer, or in which the piezoelectric layer is in contact with the silicon and/or silicon nitride layer solely through one or more metal layers.

Abstract: Control console for a powered surgical tool (310) that includes a transformer (250) with a secondary winding (264) across which the tool drive signal is present. Also internal to the transformer is a matched current source that consists of leakage control winding (246) and a capacitor. The current sourced by the matched current source at least partially cancels out leakage current that may be present.

Abstract: The present disclosure is directed to systems and methods for providing a dielectric layer on a semiconductor substrate capable of supporting very high density interconnects (i.e., ?100 IO/mm). The dielectric layer includes a maleimide polymer in which a thiol-terminated functional group crosslinks with an epoxy resin. The resultant dielectric material provides a dielectric constant of less than 3 and a dissipation factor of less than 0.001. Additionally, the thiol functional group forms coordination complexes with noble metals present in the conductive structures, thus by controlling the stoichiometry of epoxy to polyimide, the thiol-polyimide may beneficially provide an adhesion enhancer between the dielectric and noble metal conductive structures.

Abstract: A semiconductor device includes a dielectric layer, a conductive layer formed over the dielectric layer, and a reduction sacrificial layer formed between the dielectric layer and the conductive layer, wherein the reduction sacrificial layer includes a first reduction sacrificial material having higher electronegativity than the dielectric layer, and a second reduction sacrificial material having higher electronegativity than the first reduction sacrificial material.

Abstract: A resistive particle sensor is described for detecting soot in the exhaust gas of an internal combustion engine, including a sensor element having two strip conductors, which extend spaced apart in meanders in parallel to one another in an area of the sensor element that may be exposed to the exhaust gas, and a resistance strip conductor, the two strip conductors each being capacitively connected via capacitor elements to the resistance strip conductor.

Abstract: Disclosed are fusion memory devices and methods of fabricating the same. The fusion memory device comprises a first memory device including a first substrate having active and inactive surfaces opposite to each other and a first memory cell circuit on the active surface of the first substrate, a non-memory device including a second substrate having active and inactive surfaces opposite to each other and a non-memory circuit on the active surface of the second substrate, the non-memory device being provided on the first memory device, and a second memory device on the inactive surface of the second substrate and including a second memory cell circuit different from the first memory cell circuit. The non-memory device lies between the first and second memory cell circuits and controls an electrical operation of each of the first and second memory cell circuits.

Abstract: The present disclosure provides an unmanned vehicle comprising a device to be powered; a capacitor energy storage system (CESS) and controller board for at least temporarily powering and operating the device to powered. Further, the CESS includes one or more metacapacitors as an energy storage medium. Additionally, the disclosure provides a capacitor energy storage cell composed of the at least one metacapacitor and a DC-voltage conversion device, where the output voltage of the metacapacitor is the input voltage of the DC-voltage conversion device. Still further, the CESS may be comprised of a module of said capacitor energy storage cells, or a system of modules of said capacitor energy storage cells.

Abstract: Embodiments of the present invention are directed to a back-end-of-line (BEOL) compatible metal-insulator-metal on-chip decoupling capacitor (MIMCAP). This BEOL compatible process includes a thermal treatment for inducing an amorphous-to-cubic phase change in the insulating layer of the MIM stack prior to forming the top electrode. In a non-limiting embodiment of the invention, a bottom electrode layer is formed, and an insulator layer is formed on a surface of the bottom electrode layer. The insulator layer can include an amorphous dielectric material. The insulator layer is thermally treated such that the amorphous dielectric material undergoes a cubic phase transition, thereby forming a cubic phase dielectric material. A top electrode layer is formed on a surface of the cubic phase dielectric material of the insulator layer.

Abstract: A semiconductor device including a mounting substrate, a semiconductor chip, a rear-surface metal layer, an AuSn solder layer, and a solder blocking metal layer, is disclosed. The semiconductor chip is mounted on the mounting substrate, and includes front and rear surfaces, and a heat generating element. The rear-surface metal layer includes gold (Au). The AuSn solder layer is located between the mounting substrate and the rear surface to fix the semiconductor chip to the mounting substrate. The solder blocking metal layer is located between the rear surface and the mounting substrate, and in a non-heating region excluding a heating region in which the heat generating element is formed. The solder blocking metal layer includes at least one of NiCr, Ni and Ti and extends to an edge of the semiconductor chip. A void is provided between the solder blocking metal layer and the AuSn solder layer.

Abstract: A thin-film device that includes a base portion and a rewiring layer. The rewiring layer includes a first resin insulating layer and a second resin insulating layer, which are sequentially arranged from a side of the base portion, metallic layers and close-contact layers. The metallic layers and the close-contact layers form a respective wiring electrodes. These wiring electrodes are disposed at an interface between the first resin insulating layer and the second resin insulating layer. At an end portion of the wiring electrodes, the close-contact layer projects from the metallic layer by a first predetermined length along the interface.

Abstract: A semiconductor device includes a dielectric layer, a conductive layer formed over the dielectric layer, and a reduction sacrificial layer formed between the dielectric layer and the conductive layer, wherein the reduction sacrificial layer includes a first reduction sacrificial material having higher electronegativity than the dielectric layer, and a second reduction sacrificial material having higher electronegativity than the first reduction sacrificial material.

Abstract: Disclosed herein is a solar reactor comprising a reactor member; an aperture for receiving solar radiation, the aperture being disposed in a plane on a wall of the reactor member, where the plane is oriented at any angle other than parallel relative to the centerline of the reactor member; a plurality of absorber tubes, wherein the absorber tubes are oriented such that their respective centerlines are at an angle other than 90° relative to the centerline of the reactor member; and wherein the aperture has a hydraulic diameter that is from 0.2 to 4 times a hydraulic diameter of at least one absorber tube in the plurality of absorber tubes; and a reactive material, the reactive material being disposed in the plurality of absorber tubes.

Abstract: A capacitor component includes: a semiconductor substrate including first and second portions, a trench penetrating through the substrate from one surface of the substrate to the other surface of the substrate to separate the first and second portions of the substrate from each other, a dielectric layer disposed in the trench and on the one surface of the substrate; a first pad electrode and a second pad electrode spaced apart from each other, and penetrating through the dielectric layer to be in contact with the first and second portions of the substrate, respectively, and a passivation layer disposed on the dielectric layer, covering portions of the first pad electrode and the second pad electrode, and exposing at least a portion of each of the first pad electrode and the second pad electrode.

Abstract: The present invention provides a process for fabricating an n-cell supercapacitor stack, including a step of providing at least n+1 identical, or substantially identical, electrically inert conductive sheets having a defined perimeter, n identical, or substantially identical, ion-permeable insulating sheets having a defined perimeter, n identical, or substantially identical, first electrodes having a defined perimeter, n identical, or substantially identical, second electrodes having a defined perimeter, and at least n matching dielectric frames having an outer perimeter, which is larger than the perimeter of the conductive sheet and the perimeter of the insulating sheet; a step of assembling the supercapacitor stack, a step of disposing an additional conductive sheet on top of the nth second electrode; and a step of attaching adjacent units onto one another, such that at least one of the frames within each unit is attached to at least one of the frames within each respective unit adjacent thereto.

Abstract: A capacitor that includes a first capacitor layer having a first substrate provided with a first trench structure having a trench, a first electrode, and a second electrode provided in a region of the first trench structure that includes a trench, and a second capacitor layer having a second substrate, a third electrode, and a fourth electrode. Moreover, the first capacitor layer and the second capacitor layer are disposed such that the second electrode and the third electrode oppose each other and are electrically connected.

Abstract: A ceramic dielectric includes a plurality of semi-conductive grains including a semiconductor oxide including barium (Ba), titanium (Ti), and a rare earth element. A ceramic dielectric also includes an insulative oxide located between adjacent semiconductor grains and an acceptor element including manganese (Mn), magnesium (Mg), aluminum (Al), iron (Fe), scandium (Sc), gallium (Ga), or a combination thereof, a method of manufacturing the ceramic dielectric, and a ceramic electronic component, and an electronic device including the ceramic dielectric.

Abstract: Provided is a substrate with transparent electrode, which is capable of achieving both acceleration of crystallization dining a heat treatment and suppression of crystallization under a normal temperature environment. In the substrate with transparent electrode, a transparent electrode thin-film formed of a transparent conductive oxide is formed on a film substrate. An underlayer that contains a metal oxide as a main component is formed between the film substrate and the transparent electrode thin-film. The underlayer and the transparent electrode thin-film are in contact with each other. The transparent electrode thin-film is amorphous, and the base layer is dielectric and crystalline.

Abstract: Provided is a thin film capacitor that includes: a first electrode layer having a principal surface in which a plurality of recesses are provided; a dielectric layer laminated on the principal surface of the first electrode layer; and a second electrode layer laminated on the dielectric layer. When a depth of the recess is defined as FL and a thickness of the dielectric layer is defined as T, H/T is 0.05 or more and 0.5 or less.

Abstract: A multilayer ceramic capacitor includes: a ceramic body including dielectric layers and having first and second surfaces opposing each other, third and fourth surfaces connecting the first and second surfaces to each other, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other; a plurality of internal electrodes disposed in the ceramic body, each exposed to the first and second surfaces and having one ends exposed to the third or fourth surface; and a first side margin portion and a second side margin portion disposed, respectively, on the first and second surfaces of the ceramic body, wherein a metal or a metal oxide is disposed in each of the first and second side margin portions, and a ratio of a diameter of the metal or the metal oxide to a thickness of the dielectric layer is 0.8 or less.

Abstract: A multilayer ceramic capacitor includes: a ceramic body including dielectric layers and having first and second surfaces opposing each other, third and fourth surfaces connecting the first and second surfaces to each other, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other; a plurality of internal electrodes disposed in the ceramic body, each exposed to the first and second surfaces and having one ends exposed to the third or fourth surface; and a first side margin portion and a second side margin portion disposed, respectively, on the first and second surfaces of the ceramic body, wherein a metal or a metal oxide is disposed in each of the first and second side margin portions, and a ratio of a diameter of the metal or the metal oxide to a thickness of the dielectric layer is 0.8 or less.

Abstract: Some embodiments include an apparatus having horizontally-spaced bottom electrodes supported by a supporting structure. Leaker device material is directly against the bottom electrodes. Insulative material is over the bottom electrodes, and upper electrodes are over the insulative material. Plate material extends across the upper electrodes and couples the upper electrodes to one another. The plate material is directly against the leaker device material. The leaker device material electrically couples the bottom electrodes to the plate material, and may be configured to discharge at least a portion of excess charge from the bottom electrodes to the plate material. Some embodiments include methods of forming apparatuses which include capacitors having bottom electrodes and top electrodes, with the top electrodes being electrically coupled to one another through a conductive plate. Leaker devices are formed to electrically couple the bottom electrodes to the conductive plate.

Abstract: An improved multilayer ceramic capacitor is described. The multilayered ceramic capacitor comprises first internal electrodes and second internal electrodes. The first internal electrodes and said second internal electrodes are parallel with dielectric there between. A first external termination is in electrical connection with the first internal electrodes and a second external termination is in electrical contact with the second internal electrodes. A closed void layer, comprising at least one closed void, is between electrodes.

Abstract: The present disclosure provides an energy storage cell comprising at least one capacitive energy storage device and a DC-voltage conversion device. The capacitive energy storage device comprises at least one meta-capacitor. The output voltage of the capacitive energy storage device is the input voltage of the DC-voltage conversion device. The present disclosure also provides a capacitive energy storage module and a capacitive energy storage system.

Abstract: Provided is a substrate with transparent electrode, which is capable of achieving both acceleration of crystallization during a heat treatment and suppression of crystallization under a normal temperature environment. In the substrate with transparent electrode, a transparent electrode thin-film formed of a transparent conductive oxide is formed on a film substrate. An underlayer that contains a metal oxide as a main component is formed between the film substrate and the transparent electrode thin-film. The underlayer and the transparent electrode thin-film are in contact with each other. The transparent electrode thin-film is amorphous, and the base layer is dielectric and crystalline.

Abstract: A thin-film ceramic capacitor includes a body, a plurality of dielectric layers and first and second electrode layers alternately disposed on a substrate in the body, first and second electrode pads disposed on an external surface of the body, and a plurality of vias disposed in the body, the plurality of dielectric layers and first and second electrode layers having inclined etched surfaces exposed to the plurality of vias, a first via, of the plurality of vias, being connected to the inclined surface of the first electrode layer, and a second via, of the plurality of vias, being connected to the inclined surface of the second electrode layer.

Abstract: In a communication cable having a multi-core cable with a plurality of core cables in which a pair of signal lines are covered with an insulator, in which the insulator is covered with a shield tape, and in which the shield tape is covered with a wrapping tape, and having a connector formed on an end portion of the multi-core cable, the communication cable further has a case which is inserted/removed to/from a slot formed on a communication device to which the communication cable is connected, a substrate which is housed in the case and to which an end portion of the multi-core cable is connected, and a resin portion which molds a connection portion between the end portion of the multi-core cable and the substrate.

Abstract: A multilayer polymer dielectric film includes a stack of coextruded, alternating first dielectric layers and second dielectric layers that receive electrical charge. The first dielectric layers include a first polymer material and the second dielectric layers include a second polymer material different from the first polymer material. The first polymer material has a permittivity greater than the second polymer material. The second polymer material has a breakdown strength greater than the first polymer material. Adjoining first dielectric layers and second dielectric layers define an interface between the layers that delocalizes electrical charge build-up in the layers. The stack has substantially the crystallographic symmetry before and during receiving electrical charge.

Abstract: A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

Abstract: A heated capacitor runs current through either a lower metal plate, an upper metal plate, a lower metal trace that lies adjacent to a lower metal plate, an upper metal trace that lies adjacent to an upper metal plate, or both a lower metal trace that lies adjacent to a lower metal plate and an upper metal trace that lies adjacent to an upper metal plate to generate heat from the resistance to remove moisture from a moisture-sensitive insulating layer.

Abstract: A touch module and a touch panel comprising the same are provided. The touch panel comprises a substrate and a touch module disposed on the substrate. The touch module comprises a first conductive element, a second conductive element, and a dielectric element disposed between the first conductive element and the second conductive element, whereby the first conductive element are electrically insulated from the second conductive element. The dielectric element has a thickness equal to or less than 1 micrometer, and thereby it is beneficial to achieve miniaturization of the touch panel.

Abstract: A methodology for addressing package warpage is described. In an embodiment a package includes a die mounted on a wiring board. Portion of a metal plane within the wiring board includes a reduced portion, characterized by a reduced thickness that is less than a baseline thickness.

Abstract: The aim of the invention is to create a composition for coating electric conductors which is significantly more resistant to partial discharges than prior art compositions while the produced insulating layer is highly extensible. Said aim is achieved by a composition comprising 1 to 50 percent by weight of microparticles that have a specifically adjusted electronic defect structure in the crystal lattice, resulting in greater polarizability of the valence electrons, and an organic and/or organic-inorganic matrix.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a substrate core by attaching a first dielectric layer to a second conductive layer of a thin film capacitor, and attaching a second dielectric layer to a first conductive layer of the thin film capacitor.

Abstract: A semiconductor device includes a semiconductor chip, a plurality of external terminals, and a board. The board includes a first main surface in which a plurality of first electrodes electrically connected to the semiconductor chip are formed, a second main surface in which a plurality of second electrodes electrically connected to the plurality of external terminals are formed, and a plurality of interconnect layers, provided between the first main surface and the second main surface, for forming a plurality of signal paths that electrically connect the first electrode and the second electrode corresponding thereto. The interconnect layer includes a plurality of metal members which are dispersedly disposed at a distance shorter than an electromagnetic wavelength equivalent to a signal band of a signal supplied to the signal path, in the vicinity of a portion in which a structure of an interconnect for forming the signal path is changed.

Abstract: In a method for manufacturing an ion-sensitive structure for an ion-sensitive sensor, first a semiconductor substrate bearing an oxide layer is provided, whereupon a metal oxide layer and a metal layer are deposited and tempered, in order to obtain a layer sequence having a crystallized metal oxide layer and an oxidized and crystallized metal layer on the semiconductor substrate bearing the oxide layer. In such case, the metal oxide layer and the metal layer have a compatible metal element, and the coating thickness dMOX of the metal oxide layer is greater than the coating thickness dMET of the metal layer.

Abstract: A reconstituted electronic device comprising at least one die and at least one passive component. A functional material is incorporated in the substrate of the device to modify the electrical behavior of the passive component. The passive component may be formed in redistribution layers of the device. Composite functional materials may be used in the substrate to forms part of or all of the passive component. A metal carrier may form part of the substrate and part of the at least one passive component.

Abstract: A dielectric ceramic is formed with sintered grains constituting the dielectric have an average grain size of 0.2 to 1.0 ?m and an oxygen defect concentration of 0.2 to 0.5%. An acceptor element is added to the dielectric ceramic by no more than 0.5 mol per 100 mol of the primary component of BaTiO3. The oxygen defect concentration is temporarily increased by reduction and sintering, after which the oxygen defect concentration is reduced through the subsequent re-oxidization process. Crystal strain generated in the re-oxidization process increases the dielectric constant.

Abstract: A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly-doped or non-doped material. The highly doped material will remain amorphous (<30% crystalline) after an anneal step. The high band gap material will remain amorphous (<30% crystalline) after an anneal step. The lightly-doped or non-doped material will become crystalline (?30% crystalline) after an anneal step. The high band gap material is formed between the amorphous highly doped material and the lightly or non-doped material and provides an intermediate barrier to conduction through the multi-layer dielectric stack.

Abstract: Disclosed is a wiring substrate that is provided with a wiring pattern formed from a metal plate, and an insulation layer as a base material to which the wiring pattern is to be fixed. The wiring pattern has a mounting pad for having electronic parts (11) surface-mounted. Electronic parts are mounted onto the surface of the wiring pattern, by pouring solder into the mounting pad of the wiring pattern.

Abstract: A thin film capacitor includes an under electrode, a plurality of dielectric body layers and a plurality of internal electrode layers that are alternately laminated on the under electrode, the internal electrode layers respectively including protrusion parts that each protrude from the dielectric body layers viewed in the lamination direction, and connection electrodes to which at least a portion of each of the protrusion parts contacts. Assuming that protrusion amounts of the protrusion parts of the internal electrode layers that are connected to the same connection electrode are regarded as L, a protrusion amount Ln of a protrusion part of nth (n?2) internal electrode layer from the under electrode side is smaller than another protrusion amount Ln-1 of another protrusion part of (n?1)th internal electrode layer.

Abstract: A capacitor includes a dielectric layer, a first external electrode layer, a second external electrode layer, a first internal electrode portion, a second internal electrode portion, and an adsorbing portion. The first internal electrode portion is provided on a first through-hole portion, one end of the first internal electrode portion being connected to the first external electrode layer. The second internal electrode portion is provided on a second through-hole portion, one end of the second internal electrode portion being connected to the second external electrode layer. The adsorbing portion adsorbs the first external electrode layer and the second external electrode layer, the adsorbing portion being provided on a third through-hole portion.

Abstract: A design for an improved metal-on-metal capacitor design is described. The design includes a substantially diagonal feedline (411, 412, 413) in each metal layer. Each metal layer (21, 22, 23) comprises two sets of metal fingers which are interleaved. Each set of fingers comprises two subsets of fingers and the subsets of fingers are arranged at right angles to each other. Fingers in a first of the two sets are all connected to the diagonal feedline, while fingers in the other set are connected together via fingers at the periphery of the device. The design is repeated in adjacent layers, where the design may be identical or rotated (e.g by 180°) between adjacent metal layers.

Abstract: A electronic device is provided. The electronic device includes a first electrode formed in a first layer; a second electrode formed in the first layer, wherein the first electrode and the second electrode are symmetrically disposed with respect to a first point; and a first floating metal ring formed in the first layer and enclosing the first electrode and the second electrode.

Abstract: There is provided a multi-layered ceramic capacitor having a dual layer-electrode structure formed by applying a dual layer of electrode paste to the multi-layered ceramic capacitor. The multi-layered ceramic capacitor having a dual layer-electrode structure includes a capacitor body having a preset length and width and having a plurality dielectric layers stacked therein, an internal electrode unit formed on the plurality of dielectric layers and having a preset capacitance, and an external electrode unit including first external electrodes respectively formed on both sides of the capacitor body to be electrically connected to internal electrodes, and second external electrodes formed on the first external electrodes.

Abstract: A film capacitor element including a base dielectric film layer 12, a vapor-deposition metal film layer 14 formed on the base dielectric film layer 12 and consisting of a first film portion 20 and a second film portion 22 that are spaced apart from each other by a margin portion 18, and a dielectric covering film layer 16 which is formed integrally on the second film portion 22 by vapor-deposition polymerization or coating and which has a covering portion 30 which fills the margin portion 18 and covers an entire area of an end face of the second film portion 22 on the side of the margin portion 18. The first film portion 20 including a non-covered portion 34 which is not covered by the dielectric covering film layer 16.

Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10?7 amps/cm2 at from ?1.1V to +1.1V.