Layered Patents (Class 361/313)
  • Patent number: 10270010
    Abstract: Provided is a substrate with transparent electrode, which is capable of achieving both acceleration of crystallization during a heat treatment and suppression of crystallization under a normal temperature environment. In the substrate with transparent electrode, a transparent electrode thin-film formed of a transparent conductive oxide is formed on a film substrate. An underlayer that contains a metal oxide as a main component is formed between the film substrate and the transparent electrode thin-film. The underlayer and the transparent electrode thin-film are in contact with each other. The transparent electrode thin-film is amorphous, and the base layer is dielectric and crystalline.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: April 23, 2019
    Assignee: KANEKA CORPORATION
    Inventors: Takashi Kuchiyama, Hironori Hayakawa, Hiroaki Ueda, Yuji Motohara, Kenji Yamamoto
  • Patent number: 10199167
    Abstract: A thin-film ceramic capacitor includes a body, a plurality of dielectric layers and first and second electrode layers alternately disposed on a substrate in the body, first and second electrode pads disposed on an external surface of the body, and a plurality of vias disposed in the body, the plurality of dielectric layers and first and second electrode layers having inclined etched surfaces exposed to the plurality of vias, a first via, of the plurality of vias, being connected to the inclined surface of the first electrode layer, and a second via, of the plurality of vias, being connected to the inclined surface of the second electrode layer.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seung Hun Han, Sung Min Cho, Tae Joon Park, Hyun Ho Shin, Sang Kee Yoon
  • Patent number: 10157696
    Abstract: In a communication cable having a multi-core cable with a plurality of core cables in which a pair of signal lines are covered with an insulator, in which the insulator is covered with a shield tape, and in which the shield tape is covered with a wrapping tape, and having a connector formed on an end portion of the multi-core cable, the communication cable further has a case which is inserted/removed to/from a slot formed on a communication device to which the communication cable is connected, a substrate which is housed in the case and to which an end portion of the multi-core cable is connected, and a resin portion which molds a connection portion between the end portion of the multi-core cable and the substrate.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: December 18, 2018
    Assignee: Hitachi Metals, Ltd.
    Inventors: Hideki Nonen, Takashi Kumakura
  • Patent number: 10068706
    Abstract: A multilayer polymer dielectric film includes a stack of coextruded, alternating first dielectric layers and second dielectric layers that receive electrical charge. The first dielectric layers include a first polymer material and the second dielectric layers include a second polymer material different from the first polymer material. The first polymer material has a permittivity greater than the second polymer material. The second polymer material has a breakdown strength greater than the first polymer material. Adjoining first dielectric layers and second dielectric layers define an interface between the layers that delocalizes electrical charge build-up in the layers. The stack has substantially the crystallographic symmetry before and during receiving electrical charge.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: September 4, 2018
    Assignee: Case Western Reserve University
    Inventors: Eric Baer, Anne Hiltner, James S. Shirk, Mason A. Wolak
  • Patent number: 10008559
    Abstract: A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: June 26, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Hao Chen, Che-Cheng Chang, Wen-Tung Chen, Yu-Cheng Liu, Horng-Huei Tseng
  • Patent number: 9875846
    Abstract: A heated capacitor runs current through either a lower metal plate, an upper metal plate, a lower metal trace that lies adjacent to a lower metal plate, an upper metal trace that lies adjacent to an upper metal plate, or both a lower metal trace that lies adjacent to a lower metal plate and an upper metal trace that lies adjacent to an upper metal plate to generate heat from the resistance to remove moisture from a moisture-sensitive insulating layer.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: January 23, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Honglin Guo, Byron Lovell Williams
  • Patent number: 9671907
    Abstract: A touch module and a touch panel comprising the same are provided. The touch panel comprises a substrate and a touch module disposed on the substrate. The touch module comprises a first conductive element, a second conductive element, and a dielectric element disposed between the first conductive element and the second conductive element, whereby the first conductive element are electrically insulated from the second conductive element. The dielectric element has a thickness equal to or less than 1 micrometer, and thereby it is beneficial to achieve miniaturization of the touch panel.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: June 6, 2017
    Assignee: TPK Touch Solutions (Xiamen) Inc.
    Inventors: I-Chung Hsu, Kuo-Shu Hsu
  • Patent number: 9633953
    Abstract: A methodology for addressing package warpage is described. In an embodiment a package includes a die mounted on a wiring board. Portion of a metal plane within the wiring board includes a reduced portion, characterized by a reduced thickness that is less than a baseline thickness.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: April 25, 2017
    Assignee: Apple Inc.
    Inventors: Jun Chung Hsu, Jie-Hua Zhao
  • Patent number: 9580611
    Abstract: The aim of the invention is to create a composition for coating electric conductors which is significantly more resistant to partial discharges than prior art compositions while the produced insulating layer is highly extensible. Said aim is achieved by a composition comprising 1 to 50 percent by weight of microparticles that have a specifically adjusted electronic defect structure in the crystal lattice, resulting in greater polarizability of the valence electrons, and an organic and/or organic-inorganic matrix.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: February 28, 2017
    Assignee: Leibniz-Institut fuer neue Materialien gemeinnuetzige Gesellschaft mit beschraenkter Haftung
    Inventors: Sener Albayrak, Carsten Becker-Willinger, Michael Veith, Oral Cenk Aktas
  • Patent number: 9572258
    Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a substrate core by attaching a first dielectric layer to a second conductive layer of a thin film capacitor, and attaching a second dielectric layer to a first conductive layer of the thin film capacitor.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: February 14, 2017
    Assignee: Intel Corporation
    Inventors: Sriram Srinivasan, John S. Guzek, Cengiz A. Palanduz, Victor Prokofiev, Joel A. Auernheimer
  • Patent number: 9560762
    Abstract: A semiconductor device includes a semiconductor chip, a plurality of external terminals, and a board. The board includes a first main surface in which a plurality of first electrodes electrically connected to the semiconductor chip are formed, a second main surface in which a plurality of second electrodes electrically connected to the plurality of external terminals are formed, and a plurality of interconnect layers, provided between the first main surface and the second main surface, for forming a plurality of signal paths that electrically connect the first electrode and the second electrode corresponding thereto. The interconnect layer includes a plurality of metal members which are dispersedly disposed at a distance shorter than an electromagnetic wavelength equivalent to a signal band of a signal supplied to the signal path, in the vicinity of a portion in which a structure of an interconnect for forming the signal path is changed.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: January 31, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Ryuichi Oikawa
  • Patent number: 9383334
    Abstract: In a method for manufacturing an ion-sensitive structure for an ion-sensitive sensor, first a semiconductor substrate bearing an oxide layer is provided, whereupon a metal oxide layer and a metal layer are deposited and tempered, in order to obtain a layer sequence having a crystallized metal oxide layer and an oxidized and crystallized metal layer on the semiconductor substrate bearing the oxide layer. In such case, the metal oxide layer and the metal layer have a compatible metal element, and the coating thickness dMOX of the metal oxide layer is greater than the coating thickness dMET of the metal layer.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: July 5, 2016
    Assignee: Endress+Hauser Conducta GmbH+Co. KG
    Inventors: Christian Kunath, Eberhard Kurth, Torsten Pechstein
  • Patent number: 9379174
    Abstract: A reconstituted electronic device comprising at least one die and at least one passive component. A functional material is incorporated in the substrate of the device to modify the electrical behavior of the passive component. The passive component may be formed in redistribution layers of the device. Composite functional materials may be used in the substrate to forms part of or all of the passive component. A metal carrier may form part of the substrate and part of the at least one passive component.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: June 28, 2016
    Assignee: QUALCOMM TECHNOLOGIES INTERNATIONAL, LTD.
    Inventors: Vlad Lenive, Simon Stacey
  • Patent number: 9281125
    Abstract: A dielectric ceramic is formed with sintered grains constituting the dielectric have an average grain size of 0.2 to 1.0 ?m and an oxygen defect concentration of 0.2 to 0.5%. An acceptor element is added to the dielectric ceramic by no more than 0.5 mol per 100 mol of the primary component of BaTiO3. The oxygen defect concentration is temporarily increased by reduction and sintering, after which the oxygen defect concentration is reduced through the subsequent re-oxidization process. Crystal strain generated in the re-oxidization process increases the dielectric constant.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: March 8, 2016
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Katsuya Taniguchi, Tetsuo Shimura
  • Patent number: 9178006
    Abstract: A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly-doped or non-doped material. The highly doped material will remain amorphous (<30% crystalline) after an anneal step. The high band gap material will remain amorphous (<30% crystalline) after an anneal step. The lightly-doped or non-doped material will become crystalline (?30% crystalline) after an anneal step. The high band gap material is formed between the amorphous highly doped material and the lightly or non-doped material and provides an intermediate barrier to conduction through the multi-layer dielectric stack.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: November 3, 2015
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Xiangxin Rui, Hanhong Chen, Naonori Fujiwara, Imran Hashim, Kenichi Koyanagi
  • Patent number: 9084371
    Abstract: Disclosed is a wiring substrate that is provided with a wiring pattern formed from a metal plate, and an insulation layer as a base material to which the wiring pattern is to be fixed. The wiring pattern has a mounting pad for having electronic parts (11) surface-mounted. Electronic parts are mounted onto the surface of the wiring pattern, by pouring solder into the mounting pad of the wiring pattern.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: July 14, 2015
    Assignee: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Hitoshi Shimadu, Kazunori Kondou, Takehiko Sawada, Takahiro Hayakawa, Tomoaki Asai, Ryou Yamauchi
  • Patent number: 9030800
    Abstract: A thin film capacitor includes an under electrode, a plurality of dielectric body layers and a plurality of internal electrode layers that are alternately laminated on the under electrode, the internal electrode layers respectively including protrusion parts that each protrude from the dielectric body layers viewed in the lamination direction, and connection electrodes to which at least a portion of each of the protrusion parts contacts. Assuming that protrusion amounts of the protrusion parts of the internal electrode layers that are connected to the same connection electrode are regarded as L, a protrusion amount Ln of a protrusion part of nth (n?2) internal electrode layer from the under electrode side is smaller than another protrusion amount Ln-1 of another protrusion part of (n?1)th internal electrode layer.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: May 12, 2015
    Assignee: TDK Corporation
    Inventors: Tatsuo Namikawa, Yoshihiko Yano, Yasunobu Oikawa
  • Patent number: 9007741
    Abstract: A capacitor includes a dielectric layer, a first external electrode layer, a second external electrode layer, a first internal electrode portion, a second internal electrode portion, and an adsorbing portion. The first internal electrode portion is provided on a first through-hole portion, one end of the first internal electrode portion being connected to the first external electrode layer. The second internal electrode portion is provided on a second through-hole portion, one end of the second internal electrode portion being connected to the second external electrode layer. The adsorbing portion adsorbs the first external electrode layer and the second external electrode layer, the adsorbing portion being provided on a third through-hole portion.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: April 14, 2015
    Assignee: Taiyo Yuden Co., ltd.
    Inventors: Hidetoshi Masuda, Yoshinari Take
  • Patent number: 8976506
    Abstract: A design for an improved metal-on-metal capacitor design is described. The design includes a substantially diagonal feedline (411, 412, 413) in each metal layer. Each metal layer (21, 22, 23) comprises two sets of metal fingers which are interleaved. Each set of fingers comprises two subsets of fingers and the subsets of fingers are arranged at right angles to each other. Fingers in a first of the two sets are all connected to the diagonal feedline, while fingers in the other set are connected together via fingers at the periphery of the device. The design is repeated in adjacent layers, where the design may be identical or rotated (e.g by 180°) between adjacent metal layers.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: March 10, 2015
    Assignee: Cambridge Silicon Radio Ltd.
    Inventor: Rainer Herberholz
  • Patent number: 8971013
    Abstract: A electronic device is provided. The electronic device includes a first electrode formed in a first layer; a second electrode formed in the first layer, wherein the first electrode and the second electrode are symmetrically disposed with respect to a first point; and a first floating metal ring formed in the first layer and enclosing the first electrode and the second electrode.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: March 3, 2015
    Assignee: MediaTek Inc.
    Inventor: YuJen Wang
  • Patent number: 8917490
    Abstract: There is provided a multi-layered ceramic capacitor having a dual layer-electrode structure formed by applying a dual layer of electrode paste to the multi-layered ceramic capacitor. The multi-layered ceramic capacitor having a dual layer-electrode structure includes a capacitor body having a preset length and width and having a plurality dielectric layers stacked therein, an internal electrode unit formed on the plurality of dielectric layers and having a preset capacitance, and an external electrode unit including first external electrodes respectively formed on both sides of the capacitor body to be electrically connected to internal electrodes, and second external electrodes formed on the first external electrodes.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: December 23, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hyun Tae Kim, Jin Ju Park, Se Hyun Kim, Doo Young Kim, Kyung Nam Hwang
  • Patent number: 8861178
    Abstract: A film capacitor element including a base dielectric film layer 12, a vapor-deposition metal film layer 14 formed on the base dielectric film layer 12 and consisting of a first film portion 20 and a second film portion 22 that are spaced apart from each other by a margin portion 18, and a dielectric covering film layer 16 which is formed integrally on the second film portion 22 by vapor-deposition polymerization or coating and which has a covering portion 30 which fills the margin portion 18 and covers an entire area of an end face of the second film portion 22 on the side of the margin portion 18. The first film portion 20 including a non-covered portion 34 which is not covered by the dielectric covering film layer 16.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: October 14, 2014
    Assignee: Kojima Press Industry Co., Ltd.
    Inventors: Akito Terashima, Munetaka Hayakawa, Kaoru Ito
  • Patent number: 8857022
    Abstract: A low capacitance density, high voltage MIM capacitor and the high density MIM capacitor and a method of manufacture are provided. The method includes depositing a plurality of plates and a plurality of dielectric layers interleaved with one another. The method further includes etching a portion of an uppermost plate of the plurality of plates while protecting other portions of the uppermost plate. The protected other portions of the uppermost plate forms a top plate of a first metal-insulator-metal (MIM) capacitor and the etching exposes a top plate of a second MIM capacitor.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: James S. Dunn, Zhong-Xiang He, Anthony K. Stamper
  • Patent number: 8861177
    Abstract: A metallized film capacitor includes a dielectric film and two metal vapor-deposition electrodes facing each other across the dielectric film. At least one of the metal vapor-deposition electrodes is made of substantially only aluminum and magnesium. This metallized film capacitor has superior leak current characteristics and moisture resistant performances, and can be used for forming a case mold type capacitor with a small size.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: October 14, 2014
    Assignee: Panasonic Corporation
    Inventors: Hiroki Takeoka, Hiroshi Kubota, Yukikazu Ohchi, Hiroshi Fujii, Yukihiro Shimasaki
  • Patent number: 8861179
    Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10?7 amps/cm2 at from ?1.1V to +1.1V.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: October 14, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Rishikesh Krishnan, John Smythe, Vishwanath Bhat, Noel Rocklein, Bhaskar Srinivasan, Jeff Hull, Chris Carlson
  • Patent number: 8848336
    Abstract: A crystalline perovskite crystalline composite paraelectric material includes nano-regions containing rich N3? anions dispersed in a nano-grain sized matrix of crystalline oxide perovskite material, wherein (ABO3-?)?-(ABO3-?-?N?)1-?. A represents a divalent element, B represents a tetravalent element, ? satisfies 0.005???1.0, 1-? satisfies 0.05?1-??0.9, and 1-? is an area ratio between the regions containing rich N3? anions and the matrix of remaining oxide perovskite material.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 30, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Ivoyl Koutsaroff, Shinichi Higai, Akira Ando
  • Patent number: 8847574
    Abstract: Disclosed is an electrical isolator circuit comprising an input stage comprising first and second inputs, the input stage being configured to receive an input voltage signal; an output stage comprising first and second outputs electrically connected across a load capacitor; and a DC isolator comprising a first capacitor between said first input and said first output and second capacitor between said second input and said second output. The first and second plates of each of the first, second and load capacitors are defined by conductive layers of a printed circuit board and the dielectric of each of the first, second and load capacitors are defined by a non-conducting part of the printed circuit board.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: September 30, 2014
    Assignee: Broadcom Europe Limited
    Inventors: Iain Barnett, Jonathan Ephraim David Hurwitz, William Michael James Holland
  • Patent number: 8842412
    Abstract: A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: James S. Dunn, Zhong-Xiang He, Anthony K. Stamper
  • Patent number: 8842415
    Abstract: There is provided a multilayer ceramic capacitor, including: a multilayer body in which a plurality of dielectric layers are stacked in a thickness direction; and inner electrode layers formed within the multilayer body and including first and second inner electrodes disposed to be opposed to each other; wherein a ratio (MA1/CA1) of MA1 to CA1 is between 0.07 and 0.20, wherein CA1 represents an area of the multilayer body in a cross section of the multilayer body taken in a length and thickness direction, and MA1 represents an area of a first margin part in the cross section of the multilayer body taken in the length and thickness direction, the first margin part being a portion of the multilayer body, other than a first capacitance forming part thereof in which the first and second inner electrodes overlap in the thickness direction.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: September 23, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Ghyu Ahn, Byoung Hwa Lee, Min Cheol Park, Sang Soo Park, Dong Seok Park
  • Patent number: 8830652
    Abstract: A capacitor having improved tolerance to humidity. The capacitor includes a packaging material and/or a dielectric material comprising a film having a water vapor transmission rate significantly lower than the dielectric films and/or packaging films used in conventional capacitors.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: September 9, 2014
    Assignee: Zoll Medical Corporation
    Inventor: Allan Scott Baucom
  • Patent number: 8797713
    Abstract: Provided is a laminated ceramic capacitor that can suppress the decrease in insulation resistance after a moisture-resistance loading test. It contains ceramic layers which include: main-phase grains that have a perovskite-type compound containing Ba and Ti and optionally containing Ca, Sr, Zr, and Hf; and secondary-phase grains that have an average grain size of 100 nm or more and have a Si content of 50 mol % or more per grain, the average grain boundary number, represented by (Average Thickness for Ceramic Layers 3)/(Average Grain Size for Main Phase Grains)?1, is greater than 0 and 3.0 or less, and the average grain size for the secondary-phase grains is ¼ or more of the average thickness for the ceramic layers 3.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: August 5, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takayuki Yao
  • Patent number: 8788109
    Abstract: A power system can include an input configured to be coupled to a utility grid. The power system can further include an electrical energy storage unit comprising a dielectric layer disposed between first and second electrode layers, the dielectric layer comprising a high permittivity ceramic material. In an embodiment, the power system can include a control computer can control a first switch to deactivate a main electrical energy storage unit that includes the electrical energy storage unit, and to control the second switch to activate a backup energy storage unit. In a further embodiment, the power system can include an output coupled to the utility power grid. In a further embodiment, the power system can include a control computer to control a first switch to deactivate a main electrical energy storage unit, and to control a second switch to activate an electrical energy storage unit buffer.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: July 22, 2014
    Assignee: EEStor, Inc.
    Inventors: Richard D. Weir, Carl W. Nelson
  • Publication number: 20140185187
    Abstract: The present invention discloses an electrostatic energy storage device and a preparation method thereof. The device comprises at least one electrostatic energy storage unit, wherein each electrostatic energy storage unit is provided with a five-layer structure and comprises two metal film electrodes which form a capacitor, composite nano insulating film layers attached to the inner sides of the two metal film electrodes, and a ceramic nano crystalline film arranged between the composite nano insulating film layers. Based on the electrostatic parallel-plate induction capacitor principle, the metal film electrodes with a nano microstructure and the ceramic nano crystalline film sandwiched between the metal film electrodes and having an ultrahigh dielectric constant form an electrostatic induction plate capacitor to store electrostatic energy.
    Type: Application
    Filed: December 11, 2013
    Publication date: July 3, 2014
    Inventors: Jin Bai, Gang Feng
  • Patent number: 8767374
    Abstract: A capacitor and a manufacturing method thereof with improved capacitance density, simplified production process, and/or improved high frequency characteristic without having to form a nano-scale pattern are provided. A capacitor element 12 includes a dielectric layer made of porous oxide substrate, first and second internal electrodes formed within holes of the porous oxide substrate, a first external electrode electrically connected to the first internal electrode, a second external electrode electrically connected to the second internal electrodes.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiyo Yuden Co., Ltd.
    Inventor: Hidetoshi Masuda
  • Patent number: 8760841
    Abstract: A capacitor forming method includes forming an electrically conductive support material over a substrate, with the support material containing at least 25 at % carbon. The method includes forming an opening through at least the support material where the opening has an aspect ratio of at least 20:1 within a thickness of the support material. After forming the opening, the method includes processing the support material to effect a reduction in conductivity, and forming a capacitor structure in the opening.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: June 24, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Mark W. Kiehlbauch
  • Patent number: 8760843
    Abstract: A capacitive device includes a first capacitor including a first wiring layer, a first dielectric film, a first conductive layer, a first insulating layer on the first capacitor, a second capacitor on the first insulating layer including a second conductive layer, a second dielectric film, and a third conductive layer, a second insulating layer on the second capacitor, a second wiring layer on the second insulating layer including first and second connection wires, a first via connecting the first wiring layer to the second conductive layer, a second via connecting the third conductive layer to the second wiring layer, a third via connecting the first connection wire to the first conductive layer, and a fourth via connecting the second connection wire to the first wiring layer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: June 24, 2014
    Assignee: Dongbu Hitek Co., Ltd.
    Inventors: Jong Taek Hwang, Han Choon Lee, Oh Jin Jung, Jin Youn Cho
  • Patent number: 8749949
    Abstract: In a structure or device having a pair of electrical conductors separated by an insulator across which a voltage is placed, resistive layers are formed around the conductors to force the electric potential within the insulator to distribute more uniformly so as to decrease or eliminate electric field enhancement at the conductor edges. This is done by utilizing the properties of resistive layers to allow the voltage on the electrode to diffuse outwards, reducing the field stress at the conductor edge. Preferably, the resistive layer has a tapered resistivity, with a lower resistivity adjacent to the conductor and a higher resistivity away from the conductor. Generally, a resistive path across the insulator is provided, preferably by providing a resistive region in the bulk of the insulator, with the resistive layer extending over the resistive region.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: June 10, 2014
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: George J. Caporaso, Stephen E. Sampayan, David M. Sanders
  • Patent number: 8721820
    Abstract: A method for manufacturing a multilayer ceramic electronic component significantly reduces and prevents swelling or distortion when a conductive paste is applied to a green ceramic element body. A ceramic green sheet used in the method satisfies 180.56?A/B wherein A is a polymerization degree of an organic binder contained in the ceramic green sheet, and B is a volume content of a plasticizer contained in the ceramic green sheet.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: May 13, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Koji Sato, Yukio Sanada, Yasuhiro Nishisaka
  • Patent number: 8713770
    Abstract: A ceramic multilayer surface-mount capacitor with inherent crack mitigation void patterning to channel flex cracks into a safe zone, thereby negating any electrical failures.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: May 6, 2014
    Assignee: Kemet Electronics Corporation
    Inventor: John D. Prymak
  • Patent number: 8693164
    Abstract: An electrical multi-layered component includes a monolithic base member that has a plurality of ceramic layers and electrode layers disposed one on top of the other in alternating fashion. The base member includes two end surfaces opposite to one another and two side surfaces opposite to one another. The multi-layered component includes a plurality of external electrodes and a plurality of internal electrodes designed into the electrode layers. The internal electrodes at least partially overlap and form overlap areas. Each internal electrode is associated with a respective external electrode. At least one first internal electrode extending from an end surface overlaps with at least one second internal electrode (8) extending from an opposite end surface. At least a third internal electrode extends from an end surface.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: April 8, 2014
    Assignee: Epcos AG
    Inventors: Thomas Feichtinger, Georg Krenn
  • Publication number: 20140071588
    Abstract: A capacitor structure of capacitive touch panel including a first electrode layer, a first material layer, a second material layer and a second electrode layer is provided. The first material layer is disposed on the first electrode layer, and the material of the first material layer is selected from one of a semiconductor material and an insulating material. The second material layer is disposed on the first material layer, and the material of the second material layer is selected from another one of the semiconductor material and the insulating material. The second electrode layer is disposed on the second material layer.
    Type: Application
    Filed: June 18, 2013
    Publication date: March 13, 2014
    Inventors: Wei-Tsung Chen, Ted-Hong Shinn, Chuang-Chuang Tsai, Wen-Chung Tang, Chih-Hsiang Yang
  • Patent number: 8667654
    Abstract: A method manufactures a capacitor having polycrystalline dielectric layer between two metallic electrodes. The dielectric layer is formed by a polycrystalline growth of a dielectric metallic oxide on one of the metallic electrodes. At least one polycrystalline growth condition of the dielectric oxide is modified during the formation of the polycrystalline dielectric layer, which results in a variation of the polycrystalline properties of the dielectric oxide within the thickness of said layer.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: March 11, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Mickael Gros-Jean
  • Patent number: 8654503
    Abstract: A capacitor having improved tolerance to humidity. The capacitor includes a packaging material and/or a dielectric material comprising a film having a water vapor transmission rate significantly lower than the dielectric films and/or packaging films used in conventional capacitors.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: February 18, 2014
    Assignee: Zoll Medical Corporation
    Inventor: Allan Scott Baucom
  • Patent number: 8649154
    Abstract: Methods of manufacturing metal-insulator-metal capacitor structures, and the metal-insulator-metal capacitor structures obtained, are disclosed. In one embodiment, a method includes providing a substrate, forming on the substrate a first metal layer comprising a first metal, and using atomic layer deposition with an H2O oxidant to deposit on the first metal layer a protective layer comprising TiO2. The method further includes using atomic layer deposition with an O3 oxidant to deposit on the protective layer a dielectric layer of a dielectric material, and forming on the dielectric layer a second metal layer comprising a second metal. In another embodiment, a metal-insulator-metal capacitor includes a bottom electrode comprising a first metal, a protective layer deposited on the bottom electrode and comprising TiO2, a dielectric layer deposited on the protective layer and comprising a dielectric material, and a top electrode formed on the dielectric layer and comprising a second metal.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: February 11, 2014
    Assignee: IMEC
    Inventors: Mihaela Ioana Popovici, Johan Swerts, Jorge Kittl, Sven Van Elshocht
  • Patent number: 8644000
    Abstract: A multilayer ceramic capacitor, having a plurality of electrode layers and a plurality of substantially titanium dioxide dielectric layers, wherein each respective titanium dioxide dielectric layer is substantially free of porosity, wherein each respective substantially titanium dioxide dielectric layer is positioned between two respective electrode layers, wherein each respective substantially titanium dioxide dielectric layer has an average grain size of between about 200 and about 400 nanometers, wherein each respective substantially titanium dioxide dielectric layer has maximum particle size of less than about 500 nanometers. Typically, each respective substantially titanium dioxide dielectric layer further includes at least one dopant selected from the group including P, V, Nb, Ta, Mo, W, and combinations thereof, and the included dopant is typically present in amounts of less than about 0.01 atomic percent.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: February 4, 2014
    Inventors: Fatih Dogan, Alan Devoe, Ian Burn
  • Patent number: 8634180
    Abstract: There is provided a multi-layered ceramic capacitor having a dual layer-electrode structure formed by applying a dual layer of electrode paste to the multi-layered ceramic capacitor. The multi-layered ceramic capacitor having a dual layer-electrode structure includes a capacitor body having a preset length and width and having a plurality dielectric layers stacked therein, an internal electrode unit formed on the plurality of dielectric layers and having a preset capacitance, and an external electrode unit including first external electrodes respectively formed on both sides of the capacitor body to be electrically connected to internal electrodes, and second external electrodes formed on the first external electrodes.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: January 21, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hyun Tae Kim, Jin Ju Park, Se Hyun Kim, Doo Young Kim, Kyung Nam Hwang
  • Patent number: 8614875
    Abstract: An anchor group anchors organic dielectric compounds used in the production of organically based capacitors. The capacitors referred to are those that can be produced in a parallel process on a prepeg or other common printed circuit board substrate without additional metallization on copper. The pre-fabricated capacitor layer can then be built into the printed circuit board, thereby gaining on space and cost for the surface of the printed circuit board.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: December 24, 2013
    Assignee: Siemens Aktiengesellschaft
    Inventors: Günter Schmid, Dan Taroata
  • Patent number: 8611068
    Abstract: A multilayer polymer dielectric film includes a coextruded first dielectric layer and second dielectric layer. The first dielectric includes a first polymer material and the second dielectric layer includes a second polymer material. The first dielectric layer and the second dielectric layer defining an interface between the layers that delocalizes charges in the layers.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: December 17, 2013
    Assignee: Case Western Reserve University
    Inventors: Eric Baer, Anne Hiltner, James S. Shirk, Mason A. Wolak
  • Patent number: 8607424
    Abstract: A method and apparatus for a reverse metal-insulator-metal (MIM) capacitor. The apparatus includes a lower metal layer, a bottom electrode, and an upper metal layer. The lower metal layer is disposed above a substrate layer. The bottom electrode is disposed above the lower metal layer and coupled to the lower metal layer. The upper metal layer is disposed above the bottom electrode. The upper metal layer comprises a top electrode of a metal-insulator-metal (MIM) capacitor.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: December 17, 2013
    Assignee: Cypress Semiconductor Corp.
    Inventors: Vladimir Korobov, Oliver Pohland
  • Patent number: 8605409
    Abstract: An electrical multi-layered component includes a monolithic base member that has a plurality of ceramic layers and electrode layers disposed one on top of the other in alternating fashion. The base member includes two end surfaces opposite to one another and two side surfaces opposite to one another. The multi-layered component includes a plurality of external electrodes and a plurality of internal electrodes designed into the electrode layers. The internal electrodes at least partially overlap and form overlap areas. Each internal electrode is associated with a respective external electrode. At least one first internal electrode extending from an end surface overlaps with at least one second internal electrode (8) extending from an opposite end surface. At least a third internal electrode extends from an end surface.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: December 10, 2013
    Assignee: Epcos AG
    Inventors: Thomas Feichtinger, Georg Krenn