Layered Patents (Class 361/313)
  • Patent number: 11095129
    Abstract: The present disclosure provides an unmanned vehicle comprising a device to be powered; a capacitor energy storage system (CESS) and controller board for at least temporarily powering and operating the device to powered. Further, the CESS includes one or more metacapacitors as an energy storage medium. Additionally, the disclosure provides a capacitor energy storage cell composed of the at least one metacapacitor and a DC-voltage conversion device, where the output voltage of the metacapacitor is the input voltage of the DC-voltage conversion device. Still further, the CESS may be comprised of a module of said capacitor energy storage cells, or a system of modules of said capacitor energy storage cells.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: August 17, 2021
    Assignee: CAPACITOR SCIENCES INCORPORATED
    Inventors: Ian Kelly-Morgan, Pavel Ivan Lazarev
  • Patent number: 11038013
    Abstract: Embodiments of the present invention are directed to a back-end-of-line (BEOL) compatible metal-insulator-metal on-chip decoupling capacitor (MIMCAP). This BEOL compatible process includes a thermal treatment for inducing an amorphous-to-cubic phase change in the insulating layer of the MIM stack prior to forming the top electrode. In a non-limiting embodiment of the invention, a bottom electrode layer is formed, and an insulator layer is formed on a surface of the bottom electrode layer. The insulator layer can include an amorphous dielectric material. The insulator layer is thermally treated such that the amorphous dielectric material undergoes a cubic phase transition, thereby forming a cubic phase dielectric material. A top electrode layer is formed on a surface of the cubic phase dielectric material of the insulator layer.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: June 15, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul Jamison, Takashi Ando, John Greg Massey, Eduard Cartier
  • Patent number: 11031365
    Abstract: A semiconductor device including a mounting substrate, a semiconductor chip, a rear-surface metal layer, an AuSn solder layer, and a solder blocking metal layer, is disclosed. The semiconductor chip is mounted on the mounting substrate, and includes front and rear surfaces, and a heat generating element. The rear-surface metal layer includes gold (Au). The AuSn solder layer is located between the mounting substrate and the rear surface to fix the semiconductor chip to the mounting substrate. The solder blocking metal layer is located between the rear surface and the mounting substrate, and in a non-heating region excluding a heating region in which the heat generating element is formed. The solder blocking metal layer includes at least one of NiCr, Ni and Ti and extends to an edge of the semiconductor chip. A void is provided between the solder blocking metal layer and the AuSn solder layer.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: June 8, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Fumio Yamada
  • Patent number: 10978249
    Abstract: A thin-film device that includes a base portion and a rewiring layer. The rewiring layer includes a first resin insulating layer and a second resin insulating layer, which are sequentially arranged from a side of the base portion, metallic layers and close-contact layers. The metallic layers and the close-contact layers form a respective wiring electrodes. These wiring electrodes are disposed at an interface between the first resin insulating layer and the second resin insulating layer. At an end portion of the wiring electrodes, the close-contact layer projects from the metallic layer by a first predetermined length along the interface.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: April 13, 2021
    Assignee: MURATA MANUFACTURING CO, LTD.
    Inventor: Souko Fukahori
  • Patent number: 10964614
    Abstract: A semiconductor device includes a dielectric layer, a conductive layer formed over the dielectric layer, and a reduction sacrificial layer formed between the dielectric layer and the conductive layer, wherein the reduction sacrificial layer includes a first reduction sacrificial material having higher electronegativity than the dielectric layer, and a second reduction sacrificial material having higher electronegativity than the first reduction sacrificial material.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: March 30, 2021
    Assignee: SK hynix Inc.
    Inventors: Sang Young Lee, Kyung Woong Park, Han Joon Kim
  • Patent number: 10906017
    Abstract: Disclosed herein is a solar reactor comprising a reactor member; an aperture for receiving solar radiation, the aperture being disposed in a plane on a wall of the reactor member, where the plane is oriented at any angle other than parallel relative to the centerline of the reactor member; a plurality of absorber tubes, wherein the absorber tubes are oriented such that their respective centerlines are at an angle other than 90° relative to the centerline of the reactor member; and wherein the aperture has a hydraulic diameter that is from 0.2 to 4 times a hydraulic diameter of at least one absorber tube in the plurality of absorber tubes; and a reactive material, the reactive material being disposed in the plurality of absorber tubes.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: February 2, 2021
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: James F. Klausner, Joerg Petrasch, Nicholas AuYeung, Ayyoub Mehdizadeh Momen, Rishi Mishra, Jinchao Lu, David Worthington Hahn, Nikhil Sehgal, Renwei Mei, Benjamin Greek, Fotouh A. Al-Raqom, Kyle Allen
  • Patent number: 10903003
    Abstract: A capacitor component includes: a semiconductor substrate including first and second portions, a trench penetrating through the substrate from one surface of the substrate to the other surface of the substrate to separate the first and second portions of the substrate from each other, a dielectric layer disposed in the trench and on the one surface of the substrate; a first pad electrode and a second pad electrode spaced apart from each other, and penetrating through the dielectric layer to be in contact with the first and second portions of the substrate, respectively, and a passivation layer disposed on the dielectric layer, covering portions of the first pad electrode and the second pad electrode, and exposing at least a portion of each of the first pad electrode and the second pad electrode.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: January 26, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Chang Soo Jang, Ho Phil Jung, Seung Mo Lim, Tae Joon Park
  • Patent number: 10896786
    Abstract: The present invention provides a process for fabricating an n-cell supercapacitor stack, including a step of providing at least n+1 identical, or substantially identical, electrically inert conductive sheets having a defined perimeter, n identical, or substantially identical, ion-permeable insulating sheets having a defined perimeter, n identical, or substantially identical, first electrodes having a defined perimeter, n identical, or substantially identical, second electrodes having a defined perimeter, and at least n matching dielectric frames having an outer perimeter, which is larger than the perimeter of the conductive sheet and the perimeter of the insulating sheet; a step of assembling the supercapacitor stack, a step of disposing an additional conductive sheet on top of the nth second electrode; and a step of attaching adjacent units onto one another, such that at least one of the frames within each unit is attached to at least one of the frames within each respective unit adjacent thereto.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: January 19, 2021
    Assignee: POCELL TECH LTD.
    Inventors: Frederic Derfler, Ervin Tal-Gutelmacher, Mordechay Moshkovich, Tamir Stein
  • Patent number: 10879347
    Abstract: A capacitor that includes a first capacitor layer having a first substrate provided with a first trench structure having a trench, a first electrode, and a second electrode provided in a region of the first trench structure that includes a trench, and a second capacitor layer having a second substrate, a third electrode, and a fourth electrode. Moreover, the first capacitor layer and the second capacitor layer are disposed such that the second electrode and the third electrode oppose each other and are electrically connected.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: December 29, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasuhiro Murase, Tomoyuki Ashimine, Hiroshi Nakagawa
  • Patent number: 10872725
    Abstract: A ceramic dielectric includes a plurality of semi-conductive grains including a semiconductor oxide including barium (Ba), titanium (Ti), and a rare earth element. A ceramic dielectric also includes an insulative oxide located between adjacent semiconductor grains and an acceptor element including manganese (Mn), magnesium (Mg), aluminum (Al), iron (Fe), scandium (Sc), gallium (Ga), or a combination thereof, a method of manufacturing the ceramic dielectric, and a ceramic electronic component, and an electronic device including the ceramic dielectric.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: December 22, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung-Seok Moon, Hyeon Cheol Park, Chan Kwak, Hyun Sik Kim, Daejin Yang, Youngjin Cho
  • Patent number: 10777709
    Abstract: Provided is a substrate with transparent electrode, which is capable of achieving both acceleration of crystallization dining a heat treatment and suppression of crystallization under a normal temperature environment. In the substrate with transparent electrode, a transparent electrode thin-film formed of a transparent conductive oxide is formed on a film substrate. An underlayer that contains a metal oxide as a main component is formed between the film substrate and the transparent electrode thin-film. The underlayer and the transparent electrode thin-film are in contact with each other. The transparent electrode thin-film is amorphous, and the base layer is dielectric and crystalline.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: September 15, 2020
    Assignee: KANEKA CORPORATION
    Inventors: Takashi Kuchiyama, Hironori Hayakawa, Hiroaki Ueda, Yuji Motohara, Kenji Yamamoto
  • Patent number: 10755854
    Abstract: Provided is a thin film capacitor that includes: a first electrode layer having a principal surface in which a plurality of recesses are provided; a dielectric layer laminated on the principal surface of the first electrode layer; and a second electrode layer laminated on the dielectric layer. When a depth of the recess is defined as FL and a thickness of the dielectric layer is defined as T, H/T is 0.05 or more and 0.5 or less.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: August 25, 2020
    Assignee: TDK CORPORATION
    Inventors: Masahiro Hiraoka, Hitoshi Saita, Suguru Andoh, Atsuo Matsutani
  • Patent number: 10658114
    Abstract: A multilayer ceramic capacitor includes: a ceramic body including dielectric layers and having first and second surfaces opposing each other, third and fourth surfaces connecting the first and second surfaces to each other, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other; a plurality of internal electrodes disposed in the ceramic body, each exposed to the first and second surfaces and having one ends exposed to the third or fourth surface; and a first side margin portion and a second side margin portion disposed, respectively, on the first and second surfaces of the ceramic body, wherein a metal or a metal oxide is disposed in each of the first and second side margin portions, and a ratio of a diameter of the metal or the metal oxide to a thickness of the dielectric layer is 0.8 or less.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: May 19, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yong Park, Ji Hong Jo, Ki Pyo Hong
  • Patent number: 10650978
    Abstract: Some embodiments include an apparatus having horizontally-spaced bottom electrodes supported by a supporting structure. Leaker device material is directly against the bottom electrodes. Insulative material is over the bottom electrodes, and upper electrodes are over the insulative material. Plate material extends across the upper electrodes and couples the upper electrodes to one another. The plate material is directly against the leaker device material. The leaker device material electrically couples the bottom electrodes to the plate material, and may be configured to discharge at least a portion of excess charge from the bottom electrodes to the plate material. Some embodiments include methods of forming apparatuses which include capacitors having bottom electrodes and top electrodes, with the top electrodes being electrically coupled to one another through a conductive plate. Leaker devices are formed to electrically couple the bottom electrodes to the conductive plate.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: May 12, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ashonita A. Chavan, Beth R. Cook, Manuj Nahar, Durai Vishak Nirmal Ramaswamy
  • Patent number: 10650969
    Abstract: A multilayer ceramic capacitor includes: a ceramic body including dielectric layers and having first and second surfaces opposing each other, third and fourth surfaces connecting the first and second surfaces to each other, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other; a plurality of internal electrodes disposed in the ceramic body, each exposed to the first and second surfaces and having one ends exposed to the third or fourth surface; and a first side margin portion and a second side margin portion disposed, respectively, on the first and second surfaces of the ceramic body, wherein a metal or a metal oxide is disposed in each of the first and second side margin portions, and a ratio of a diameter of the metal or the metal oxide to a thickness of the dielectric layer is 0.8 or less.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: May 12, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yong Park, Ji Hong Jo, Ki Pyo Hong
  • Patent number: 10593483
    Abstract: An improved multilayer ceramic capacitor is described. The multilayered ceramic capacitor comprises first internal electrodes and second internal electrodes. The first internal electrodes and said second internal electrodes are parallel with dielectric there between. A first external termination is in electrical connection with the first internal electrodes and a second external termination is in electrical contact with the second internal electrodes. A closed void layer, comprising at least one closed void, is between electrodes.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: March 17, 2020
    Assignee: KEMET Electronics Corporation
    Inventor: John Bultitude
  • Patent number: 10305295
    Abstract: The present disclosure provides an energy storage cell comprising at least one capacitive energy storage device and a DC-voltage conversion device. The capacitive energy storage device comprises at least one meta-capacitor. The output voltage of the capacitive energy storage device is the input voltage of the DC-voltage conversion device. The present disclosure also provides a capacitive energy storage module and a capacitive energy storage system.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: May 28, 2019
    Assignee: Capacitor Sciences Incorporated
    Inventors: Ian S. G. Kelly-Morgan, Matthew R. Robinson, Paul Furuta, Daniel Membreno, Pavel Ivan Lazarev
  • Patent number: 10270010
    Abstract: Provided is a substrate with transparent electrode, which is capable of achieving both acceleration of crystallization during a heat treatment and suppression of crystallization under a normal temperature environment. In the substrate with transparent electrode, a transparent electrode thin-film formed of a transparent conductive oxide is formed on a film substrate. An underlayer that contains a metal oxide as a main component is formed between the film substrate and the transparent electrode thin-film. The underlayer and the transparent electrode thin-film are in contact with each other. The transparent electrode thin-film is amorphous, and the base layer is dielectric and crystalline.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: April 23, 2019
    Assignee: KANEKA CORPORATION
    Inventors: Takashi Kuchiyama, Hironori Hayakawa, Hiroaki Ueda, Yuji Motohara, Kenji Yamamoto
  • Patent number: 10199167
    Abstract: A thin-film ceramic capacitor includes a body, a plurality of dielectric layers and first and second electrode layers alternately disposed on a substrate in the body, first and second electrode pads disposed on an external surface of the body, and a plurality of vias disposed in the body, the plurality of dielectric layers and first and second electrode layers having inclined etched surfaces exposed to the plurality of vias, a first via, of the plurality of vias, being connected to the inclined surface of the first electrode layer, and a second via, of the plurality of vias, being connected to the inclined surface of the second electrode layer.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seung Hun Han, Sung Min Cho, Tae Joon Park, Hyun Ho Shin, Sang Kee Yoon
  • Patent number: 10157696
    Abstract: In a communication cable having a multi-core cable with a plurality of core cables in which a pair of signal lines are covered with an insulator, in which the insulator is covered with a shield tape, and in which the shield tape is covered with a wrapping tape, and having a connector formed on an end portion of the multi-core cable, the communication cable further has a case which is inserted/removed to/from a slot formed on a communication device to which the communication cable is connected, a substrate which is housed in the case and to which an end portion of the multi-core cable is connected, and a resin portion which molds a connection portion between the end portion of the multi-core cable and the substrate.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: December 18, 2018
    Assignee: Hitachi Metals, Ltd.
    Inventors: Hideki Nonen, Takashi Kumakura
  • Patent number: 10068706
    Abstract: A multilayer polymer dielectric film includes a stack of coextruded, alternating first dielectric layers and second dielectric layers that receive electrical charge. The first dielectric layers include a first polymer material and the second dielectric layers include a second polymer material different from the first polymer material. The first polymer material has a permittivity greater than the second polymer material. The second polymer material has a breakdown strength greater than the first polymer material. Adjoining first dielectric layers and second dielectric layers define an interface between the layers that delocalizes electrical charge build-up in the layers. The stack has substantially the crystallographic symmetry before and during receiving electrical charge.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: September 4, 2018
    Assignee: Case Western Reserve University
    Inventors: Eric Baer, Anne Hiltner, James S. Shirk, Mason A. Wolak
  • Patent number: 10008559
    Abstract: A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: June 26, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Hao Chen, Che-Cheng Chang, Wen-Tung Chen, Yu-Cheng Liu, Horng-Huei Tseng
  • Patent number: 9875846
    Abstract: A heated capacitor runs current through either a lower metal plate, an upper metal plate, a lower metal trace that lies adjacent to a lower metal plate, an upper metal trace that lies adjacent to an upper metal plate, or both a lower metal trace that lies adjacent to a lower metal plate and an upper metal trace that lies adjacent to an upper metal plate to generate heat from the resistance to remove moisture from a moisture-sensitive insulating layer.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: January 23, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Honglin Guo, Byron Lovell Williams
  • Patent number: 9671907
    Abstract: A touch module and a touch panel comprising the same are provided. The touch panel comprises a substrate and a touch module disposed on the substrate. The touch module comprises a first conductive element, a second conductive element, and a dielectric element disposed between the first conductive element and the second conductive element, whereby the first conductive element are electrically insulated from the second conductive element. The dielectric element has a thickness equal to or less than 1 micrometer, and thereby it is beneficial to achieve miniaturization of the touch panel.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: June 6, 2017
    Assignee: TPK Touch Solutions (Xiamen) Inc.
    Inventors: I-Chung Hsu, Kuo-Shu Hsu
  • Patent number: 9633953
    Abstract: A methodology for addressing package warpage is described. In an embodiment a package includes a die mounted on a wiring board. Portion of a metal plane within the wiring board includes a reduced portion, characterized by a reduced thickness that is less than a baseline thickness.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: April 25, 2017
    Assignee: Apple Inc.
    Inventors: Jun Chung Hsu, Jie-Hua Zhao
  • Patent number: 9580611
    Abstract: The aim of the invention is to create a composition for coating electric conductors which is significantly more resistant to partial discharges than prior art compositions while the produced insulating layer is highly extensible. Said aim is achieved by a composition comprising 1 to 50 percent by weight of microparticles that have a specifically adjusted electronic defect structure in the crystal lattice, resulting in greater polarizability of the valence electrons, and an organic and/or organic-inorganic matrix.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: February 28, 2017
    Assignee: Leibniz-Institut fuer neue Materialien gemeinnuetzige Gesellschaft mit beschraenkter Haftung
    Inventors: Sener Albayrak, Carsten Becker-Willinger, Michael Veith, Oral Cenk Aktas
  • Patent number: 9572258
    Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a substrate core by attaching a first dielectric layer to a second conductive layer of a thin film capacitor, and attaching a second dielectric layer to a first conductive layer of the thin film capacitor.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: February 14, 2017
    Assignee: Intel Corporation
    Inventors: Sriram Srinivasan, John S. Guzek, Cengiz A. Palanduz, Victor Prokofiev, Joel A. Auernheimer
  • Patent number: 9560762
    Abstract: A semiconductor device includes a semiconductor chip, a plurality of external terminals, and a board. The board includes a first main surface in which a plurality of first electrodes electrically connected to the semiconductor chip are formed, a second main surface in which a plurality of second electrodes electrically connected to the plurality of external terminals are formed, and a plurality of interconnect layers, provided between the first main surface and the second main surface, for forming a plurality of signal paths that electrically connect the first electrode and the second electrode corresponding thereto. The interconnect layer includes a plurality of metal members which are dispersedly disposed at a distance shorter than an electromagnetic wavelength equivalent to a signal band of a signal supplied to the signal path, in the vicinity of a portion in which a structure of an interconnect for forming the signal path is changed.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: January 31, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Ryuichi Oikawa
  • Patent number: 9383334
    Abstract: In a method for manufacturing an ion-sensitive structure for an ion-sensitive sensor, first a semiconductor substrate bearing an oxide layer is provided, whereupon a metal oxide layer and a metal layer are deposited and tempered, in order to obtain a layer sequence having a crystallized metal oxide layer and an oxidized and crystallized metal layer on the semiconductor substrate bearing the oxide layer. In such case, the metal oxide layer and the metal layer have a compatible metal element, and the coating thickness dMOX of the metal oxide layer is greater than the coating thickness dMET of the metal layer.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: July 5, 2016
    Assignee: Endress+Hauser Conducta GmbH+Co. KG
    Inventors: Christian Kunath, Eberhard Kurth, Torsten Pechstein
  • Patent number: 9379174
    Abstract: A reconstituted electronic device comprising at least one die and at least one passive component. A functional material is incorporated in the substrate of the device to modify the electrical behavior of the passive component. The passive component may be formed in redistribution layers of the device. Composite functional materials may be used in the substrate to forms part of or all of the passive component. A metal carrier may form part of the substrate and part of the at least one passive component.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: June 28, 2016
    Assignee: QUALCOMM TECHNOLOGIES INTERNATIONAL, LTD.
    Inventors: Vlad Lenive, Simon Stacey
  • Patent number: 9281125
    Abstract: A dielectric ceramic is formed with sintered grains constituting the dielectric have an average grain size of 0.2 to 1.0 ?m and an oxygen defect concentration of 0.2 to 0.5%. An acceptor element is added to the dielectric ceramic by no more than 0.5 mol per 100 mol of the primary component of BaTiO3. The oxygen defect concentration is temporarily increased by reduction and sintering, after which the oxygen defect concentration is reduced through the subsequent re-oxidization process. Crystal strain generated in the re-oxidization process increases the dielectric constant.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: March 8, 2016
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Katsuya Taniguchi, Tetsuo Shimura
  • Patent number: 9178006
    Abstract: A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly-doped or non-doped material. The highly doped material will remain amorphous (<30% crystalline) after an anneal step. The high band gap material will remain amorphous (<30% crystalline) after an anneal step. The lightly-doped or non-doped material will become crystalline (?30% crystalline) after an anneal step. The high band gap material is formed between the amorphous highly doped material and the lightly or non-doped material and provides an intermediate barrier to conduction through the multi-layer dielectric stack.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: November 3, 2015
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Xiangxin Rui, Hanhong Chen, Naonori Fujiwara, Imran Hashim, Kenichi Koyanagi
  • Patent number: 9084371
    Abstract: Disclosed is a wiring substrate that is provided with a wiring pattern formed from a metal plate, and an insulation layer as a base material to which the wiring pattern is to be fixed. The wiring pattern has a mounting pad for having electronic parts (11) surface-mounted. Electronic parts are mounted onto the surface of the wiring pattern, by pouring solder into the mounting pad of the wiring pattern.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: July 14, 2015
    Assignee: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Hitoshi Shimadu, Kazunori Kondou, Takehiko Sawada, Takahiro Hayakawa, Tomoaki Asai, Ryou Yamauchi
  • Patent number: 9030800
    Abstract: A thin film capacitor includes an under electrode, a plurality of dielectric body layers and a plurality of internal electrode layers that are alternately laminated on the under electrode, the internal electrode layers respectively including protrusion parts that each protrude from the dielectric body layers viewed in the lamination direction, and connection electrodes to which at least a portion of each of the protrusion parts contacts. Assuming that protrusion amounts of the protrusion parts of the internal electrode layers that are connected to the same connection electrode are regarded as L, a protrusion amount Ln of a protrusion part of nth (n?2) internal electrode layer from the under electrode side is smaller than another protrusion amount Ln-1 of another protrusion part of (n?1)th internal electrode layer.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: May 12, 2015
    Assignee: TDK Corporation
    Inventors: Tatsuo Namikawa, Yoshihiko Yano, Yasunobu Oikawa
  • Patent number: 9007741
    Abstract: A capacitor includes a dielectric layer, a first external electrode layer, a second external electrode layer, a first internal electrode portion, a second internal electrode portion, and an adsorbing portion. The first internal electrode portion is provided on a first through-hole portion, one end of the first internal electrode portion being connected to the first external electrode layer. The second internal electrode portion is provided on a second through-hole portion, one end of the second internal electrode portion being connected to the second external electrode layer. The adsorbing portion adsorbs the first external electrode layer and the second external electrode layer, the adsorbing portion being provided on a third through-hole portion.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: April 14, 2015
    Assignee: Taiyo Yuden Co., ltd.
    Inventors: Hidetoshi Masuda, Yoshinari Take
  • Patent number: 8976506
    Abstract: A design for an improved metal-on-metal capacitor design is described. The design includes a substantially diagonal feedline (411, 412, 413) in each metal layer. Each metal layer (21, 22, 23) comprises two sets of metal fingers which are interleaved. Each set of fingers comprises two subsets of fingers and the subsets of fingers are arranged at right angles to each other. Fingers in a first of the two sets are all connected to the diagonal feedline, while fingers in the other set are connected together via fingers at the periphery of the device. The design is repeated in adjacent layers, where the design may be identical or rotated (e.g by 180°) between adjacent metal layers.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: March 10, 2015
    Assignee: Cambridge Silicon Radio Ltd.
    Inventor: Rainer Herberholz
  • Patent number: 8971013
    Abstract: A electronic device is provided. The electronic device includes a first electrode formed in a first layer; a second electrode formed in the first layer, wherein the first electrode and the second electrode are symmetrically disposed with respect to a first point; and a first floating metal ring formed in the first layer and enclosing the first electrode and the second electrode.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: March 3, 2015
    Assignee: MediaTek Inc.
    Inventor: YuJen Wang
  • Patent number: 8917490
    Abstract: There is provided a multi-layered ceramic capacitor having a dual layer-electrode structure formed by applying a dual layer of electrode paste to the multi-layered ceramic capacitor. The multi-layered ceramic capacitor having a dual layer-electrode structure includes a capacitor body having a preset length and width and having a plurality dielectric layers stacked therein, an internal electrode unit formed on the plurality of dielectric layers and having a preset capacitance, and an external electrode unit including first external electrodes respectively formed on both sides of the capacitor body to be electrically connected to internal electrodes, and second external electrodes formed on the first external electrodes.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: December 23, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hyun Tae Kim, Jin Ju Park, Se Hyun Kim, Doo Young Kim, Kyung Nam Hwang
  • Patent number: 8861178
    Abstract: A film capacitor element including a base dielectric film layer 12, a vapor-deposition metal film layer 14 formed on the base dielectric film layer 12 and consisting of a first film portion 20 and a second film portion 22 that are spaced apart from each other by a margin portion 18, and a dielectric covering film layer 16 which is formed integrally on the second film portion 22 by vapor-deposition polymerization or coating and which has a covering portion 30 which fills the margin portion 18 and covers an entire area of an end face of the second film portion 22 on the side of the margin portion 18. The first film portion 20 including a non-covered portion 34 which is not covered by the dielectric covering film layer 16.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: October 14, 2014
    Assignee: Kojima Press Industry Co., Ltd.
    Inventors: Akito Terashima, Munetaka Hayakawa, Kaoru Ito
  • Patent number: 8861177
    Abstract: A metallized film capacitor includes a dielectric film and two metal vapor-deposition electrodes facing each other across the dielectric film. At least one of the metal vapor-deposition electrodes is made of substantially only aluminum and magnesium. This metallized film capacitor has superior leak current characteristics and moisture resistant performances, and can be used for forming a case mold type capacitor with a small size.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: October 14, 2014
    Assignee: Panasonic Corporation
    Inventors: Hiroki Takeoka, Hiroshi Kubota, Yukikazu Ohchi, Hiroshi Fujii, Yukihiro Shimasaki
  • Patent number: 8857022
    Abstract: A low capacitance density, high voltage MIM capacitor and the high density MIM capacitor and a method of manufacture are provided. The method includes depositing a plurality of plates and a plurality of dielectric layers interleaved with one another. The method further includes etching a portion of an uppermost plate of the plurality of plates while protecting other portions of the uppermost plate. The protected other portions of the uppermost plate forms a top plate of a first metal-insulator-metal (MIM) capacitor and the etching exposes a top plate of a second MIM capacitor.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: James S. Dunn, Zhong-Xiang He, Anthony K. Stamper
  • Patent number: 8861179
    Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10?7 amps/cm2 at from ?1.1V to +1.1V.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: October 14, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Rishikesh Krishnan, John Smythe, Vishwanath Bhat, Noel Rocklein, Bhaskar Srinivasan, Jeff Hull, Chris Carlson
  • Patent number: 8847574
    Abstract: Disclosed is an electrical isolator circuit comprising an input stage comprising first and second inputs, the input stage being configured to receive an input voltage signal; an output stage comprising first and second outputs electrically connected across a load capacitor; and a DC isolator comprising a first capacitor between said first input and said first output and second capacitor between said second input and said second output. The first and second plates of each of the first, second and load capacitors are defined by conductive layers of a printed circuit board and the dielectric of each of the first, second and load capacitors are defined by a non-conducting part of the printed circuit board.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: September 30, 2014
    Assignee: Broadcom Europe Limited
    Inventors: Iain Barnett, Jonathan Ephraim David Hurwitz, William Michael James Holland
  • Patent number: 8848336
    Abstract: A crystalline perovskite crystalline composite paraelectric material includes nano-regions containing rich N3? anions dispersed in a nano-grain sized matrix of crystalline oxide perovskite material, wherein (ABO3-?)?-(ABO3-?-?N?)1-?. A represents a divalent element, B represents a tetravalent element, ? satisfies 0.005???1.0, 1-? satisfies 0.05?1-??0.9, and 1-? is an area ratio between the regions containing rich N3? anions and the matrix of remaining oxide perovskite material.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 30, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Ivoyl Koutsaroff, Shinichi Higai, Akira Ando
  • Patent number: 8842415
    Abstract: There is provided a multilayer ceramic capacitor, including: a multilayer body in which a plurality of dielectric layers are stacked in a thickness direction; and inner electrode layers formed within the multilayer body and including first and second inner electrodes disposed to be opposed to each other; wherein a ratio (MA1/CA1) of MA1 to CA1 is between 0.07 and 0.20, wherein CA1 represents an area of the multilayer body in a cross section of the multilayer body taken in a length and thickness direction, and MA1 represents an area of a first margin part in the cross section of the multilayer body taken in the length and thickness direction, the first margin part being a portion of the multilayer body, other than a first capacitance forming part thereof in which the first and second inner electrodes overlap in the thickness direction.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: September 23, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Ghyu Ahn, Byoung Hwa Lee, Min Cheol Park, Sang Soo Park, Dong Seok Park
  • Patent number: 8842412
    Abstract: A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: James S. Dunn, Zhong-Xiang He, Anthony K. Stamper
  • Patent number: 8830652
    Abstract: A capacitor having improved tolerance to humidity. The capacitor includes a packaging material and/or a dielectric material comprising a film having a water vapor transmission rate significantly lower than the dielectric films and/or packaging films used in conventional capacitors.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: September 9, 2014
    Assignee: Zoll Medical Corporation
    Inventor: Allan Scott Baucom
  • Patent number: 8797713
    Abstract: Provided is a laminated ceramic capacitor that can suppress the decrease in insulation resistance after a moisture-resistance loading test. It contains ceramic layers which include: main-phase grains that have a perovskite-type compound containing Ba and Ti and optionally containing Ca, Sr, Zr, and Hf; and secondary-phase grains that have an average grain size of 100 nm or more and have a Si content of 50 mol % or more per grain, the average grain boundary number, represented by (Average Thickness for Ceramic Layers 3)/(Average Grain Size for Main Phase Grains)?1, is greater than 0 and 3.0 or less, and the average grain size for the secondary-phase grains is ¼ or more of the average thickness for the ceramic layers 3.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: August 5, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takayuki Yao
  • Patent number: 8788109
    Abstract: A power system can include an input configured to be coupled to a utility grid. The power system can further include an electrical energy storage unit comprising a dielectric layer disposed between first and second electrode layers, the dielectric layer comprising a high permittivity ceramic material. In an embodiment, the power system can include a control computer can control a first switch to deactivate a main electrical energy storage unit that includes the electrical energy storage unit, and to control the second switch to activate a backup energy storage unit. In a further embodiment, the power system can include an output coupled to the utility power grid. In a further embodiment, the power system can include a control computer to control a first switch to deactivate a main electrical energy storage unit, and to control a second switch to activate an electrical energy storage unit buffer.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: July 22, 2014
    Assignee: EEStor, Inc.
    Inventors: Richard D. Weir, Carl W. Nelson
  • Publication number: 20140185187
    Abstract: The present invention discloses an electrostatic energy storage device and a preparation method thereof. The device comprises at least one electrostatic energy storage unit, wherein each electrostatic energy storage unit is provided with a five-layer structure and comprises two metal film electrodes which form a capacitor, composite nano insulating film layers attached to the inner sides of the two metal film electrodes, and a ceramic nano crystalline film arranged between the composite nano insulating film layers. Based on the electrostatic parallel-plate induction capacitor principle, the metal film electrodes with a nano microstructure and the ceramic nano crystalline film sandwiched between the metal film electrodes and having an ultrahigh dielectric constant form an electrostatic induction plate capacitor to store electrostatic energy.
    Type: Application
    Filed: December 11, 2013
    Publication date: July 3, 2014
    Inventors: Jin Bai, Gang Feng