Layered Patents (Class 361/313)
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Patent number: 12217912Abstract: A film capacitor that includes a wound body having a dielectric film and a metal layer, the dielectric film including a cured product of a first organic material having a hydroxy group and a second organic material that is an aromatic compound having an isocyanate group, the metal layer being disposed at least on a first main surface of the dielectric film. The first main surface of the dielectric film includes a plurality of protrusions having the second organic material. In an area range of 100 ?m by 140 ?m of the first main surface of the dielectric film, the plurality of the protrusions have an average diameter of 0.58 ?m to 5.98 ?m and an average height of 0.11 ?m to 2.54 ?m, and a number of the plurality of the protrusions ranges from 50 to 450.Type: GrantFiled: April 4, 2023Date of Patent: February 4, 2025Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Kazuto Yamazaki, Tomoki Inakura
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Patent number: 12133987Abstract: There is provided a feedthrough including a ceramic body; and a plurality of electrical conductors embedded in the ceramic body. Wherein the density of the electrical conductors exceeds 1 conductor per 23 thou2 (14,839 ?m2) through a planar cross-section of the ceramic body.Type: GrantFiled: April 18, 2019Date of Patent: November 5, 2024Assignee: Morgan Advanced Ceramics, Inc.Inventors: Abhishek S. Patnaik, John Antalek, Mark Schmeckpeper, Abhaya Bakshi, Robert MacKinnon
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Patent number: 12062499Abstract: A body includes dielectric films, first electrode films, and second electrode films being stacked on one another or being wound together. A first external electrode is at one end of the body and electrically connected to the first electrode films. A second external electrode is at another end of the body and electrically connected to the second electrode films. The body includes a capacitance portion in which each of the first electrode films faces a corresponding second electrode film of the second electrode films with a corresponding dielectric film of the dielectric films in between, and the capacitance portion includes spaces each between a corresponding dielectric film of the dielectric films and a corresponding first electrode film of the first electrode films or between a corresponding dielectric film of the dielectric films and a corresponding second electrode film of the second electrode films.Type: GrantFiled: December 9, 2020Date of Patent: August 13, 2024Assignee: KYOCERA CORPORATIONInventor: Yuki Senoo
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Patent number: 12034036Abstract: A semiconductor device includes a lower electrode; an upper electrode disposed to be spaced apart from the lower electrode; and a dielectric layer disposed between the lower electrode and the upper electrode, and including a first metal oxide region, a second metal oxide region, and a third metal oxide region.Type: GrantFiled: May 28, 2021Date of Patent: July 9, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Jeonggyu Song, Younsoo Kim, Haeryong Kim, Boeun Park, Eunha Lee, Jooho Lee, Hyangsook Lee, Yong-Hee Cho, Eunae Cho
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Patent number: 12002664Abstract: A cleaning method is provided. In the cleaning method, residues of elements of a group for a common semiconductor material in a chamber are removed with plasma of a halogen-containing gas. Residues of metal elements of groups 12 and 13 and groups 14 and 15 in the chamber are removed with plasma of a hydrocarbon-containing gas. A C-containing material in the chamber is removed with plasma of an O-containing gas. Further, the removing with the plasma of the halogen-containing gas, the removing with the plasma of the hydrocarbon-containing gas, and the removing with the plasma of the O-containing gas are performed in that order or the removing with the plasma of the hydrocarbon-containing gas, the removing with the plasma of the O-containing gas, and the removing with the plasma of the halogen-containing gas are performed in that order X times where X?1.Type: GrantFiled: November 10, 2022Date of Patent: June 4, 2024Assignee: TOKYO ELECTRON LIMITEDInventor: Masahiro Yamazaki
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Patent number: 11996239Abstract: In an embodiment a capacitor includes a dielectric layer including a polyamideimide, the dielectric layer being uniform and a first electrode disposed directly adjacent to the dielectric layer.Type: GrantFiled: September 17, 2021Date of Patent: May 28, 2024Assignee: TDK Electronics AGInventors: Birgit Six, Stefan Sax
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Patent number: 11915876Abstract: A ceramic electronic device comprises an element body including a ceramic layer and an internal electrode layer, and an external electrode electrically connected to at least one end of the internal electrode layer. The element body includes an interface part at least at a part of a boundary between the external electrode and the ceramic layer. The interface part includes an oxide containing aluminium and an oxide containing boron.Type: GrantFiled: July 6, 2022Date of Patent: February 27, 2024Assignee: TDK CORPORATIONInventors: Toshihiro Iguchi, Norihisa Ando, Kenya Tamaki, Hisashi Kobayashi
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Patent number: 11915885Abstract: An electrode foil for an electrolytic capacitor includes: an anode body including a first metal; a first dielectric layer covering at least a part of the anode body and including an oxide of the first metal; and a second dielectric layer covering at least a part of the first dielectric layer and including an oxide of a second metal. The first metal includes at least one selected from the group consisting of titanium, tantalum, niobium, and aluminum. And the second metal includes at least one selected from the group consisting of silicon, zirconium, hafnium, and tantalum. A thickness T2 of the second dielectric layer is smaller than a thickness T1 of the first dielectric layer.Type: GrantFiled: September 4, 2020Date of Patent: February 27, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Miwa Ogawa, Naomi Kurihara
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Patent number: 11898000Abstract: All organic, dielectric polymers with high discharge efficiency at elevated operation temperatures are reported.Type: GrantFiled: July 2, 2020Date of Patent: February 13, 2024Assignee: UNIVERSITY OF CONNECTICUTInventor: Gregory A. Sotzing
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Patent number: 11854748Abstract: A thin film high polymer laminated capacitor includes: a laminated chip including dielectric layers, and internal electrode layers including first metal layers including a first metal vapor-deposited on the dielectric layers, and second metal layers including a second metal vapor-deposited on the first metal layers. The dielectric layers and the internal electrode layers being laminated and bonded alternately, and external electrodes formed on one end and the other end of the laminated chip. The laminated chip having a first region having the first metal layers formed on the dielectric layers, which are laminated alternately, and edge regions having the second metal layers formed on layers connected to the one end and layers connected to the other end in the first metal layers, which are laminated alternately, the first region having a capacitor function region, and the edge region having a heavy edge.Type: GrantFiled: November 26, 2021Date of Patent: December 26, 2023Assignee: RUBYCON CORPORATIONInventors: Tomonao Kako, Chiharu Ito
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Patent number: 11758816Abstract: A method for producing a piezoelectric transducer device is provided, including a membrane including at least one silicon and/or silicon nitride layer; a piezoelectric layer including at least one piezoelectric material with crystalline perovskite structure and arranged on the membrane; first and second electrodes electrically in contact with the piezoelectric layer; and in which the piezoelectric layer is in direct contact with the silicon and/or silicon nitride layer, or in which the piezoelectric layer is in contact with the silicon and/or silicon nitride layer solely through one or more metal layers.Type: GrantFiled: June 19, 2019Date of Patent: September 12, 2023Assignee: Commissariat A L'Energie Atomique et aux Energies AlternativesInventor: Gwenael Le Rhun
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Patent number: 11673163Abstract: Control console for a powered surgical tool (310) that includes a transformer (250) with a secondary winding (264) across which the tool drive signal is present. Also internal to the transformer is a matched current source that consists of leakage control winding (246) and a capacitor. The current sourced by the matched current source at least partially cancels out leakage current that may be present.Type: GrantFiled: May 25, 2017Date of Patent: June 13, 2023Assignee: STRYKER CORPORATIONInventor: Adam Darwin Downey
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Patent number: 11552010Abstract: The present disclosure is directed to systems and methods for providing a dielectric layer on a semiconductor substrate capable of supporting very high density interconnects (i.e., ?100 IO/mm). The dielectric layer includes a maleimide polymer in which a thiol-terminated functional group crosslinks with an epoxy resin. The resultant dielectric material provides a dielectric constant of less than 3 and a dissipation factor of less than 0.001. Additionally, the thiol functional group forms coordination complexes with noble metals present in the conductive structures, thus by controlling the stoichiometry of epoxy to polyimide, the thiol-polyimide may beneficially provide an adhesion enhancer between the dielectric and noble metal conductive structures.Type: GrantFiled: May 12, 2017Date of Patent: January 10, 2023Assignee: Intel CorporationInventors: Robert A. May, Andrew J. Brown, Sri Ranga Sai Boyapati, Kristof Darmawikarta
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Patent number: 11532527Abstract: A semiconductor device includes a dielectric layer, a conductive layer formed over the dielectric layer, and a reduction sacrificial layer formed between the dielectric layer and the conductive layer, wherein the reduction sacrificial layer includes a first reduction sacrificial material having higher electronegativity than the dielectric layer, and a second reduction sacrificial material having higher electronegativity than the first reduction sacrificial material.Type: GrantFiled: March 2, 2021Date of Patent: December 20, 2022Assignee: SK hynix Inc.Inventors: Sang Young Lee, Kyung Woong Park, Han Joon Kim
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Patent number: 11486844Abstract: A resistive particle sensor is described for detecting soot in the exhaust gas of an internal combustion engine, including a sensor element having two strip conductors, which extend spaced apart in meanders in parallel to one another in an area of the sensor element that may be exposed to the exhaust gas, and a resistance strip conductor, the two strip conductors each being capacitively connected via capacitor elements to the resistance strip conductor.Type: GrantFiled: May 30, 2018Date of Patent: November 1, 2022Assignee: Robert Bosch GmbHInventors: Carolin Maria Schilling, Enno Baars, Karola Herweg, Mathias Klenk
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Patent number: 11462528Abstract: Disclosed are fusion memory devices and methods of fabricating the same. The fusion memory device comprises a first memory device including a first substrate having active and inactive surfaces opposite to each other and a first memory cell circuit on the active surface of the first substrate, a non-memory device including a second substrate having active and inactive surfaces opposite to each other and a non-memory circuit on the active surface of the second substrate, the non-memory device being provided on the first memory device, and a second memory device on the inactive surface of the second substrate and including a second memory cell circuit different from the first memory cell circuit. The non-memory device lies between the first and second memory cell circuits and controls an electrical operation of each of the first and second memory cell circuits.Type: GrantFiled: July 2, 2019Date of Patent: October 4, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyunmog Park, Daehyun Kim, Jinmin Kim, Hei Seung Kim, Hyunsik Park, Sangkil Lee
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Patent number: 11095129Abstract: The present disclosure provides an unmanned vehicle comprising a device to be powered; a capacitor energy storage system (CESS) and controller board for at least temporarily powering and operating the device to powered. Further, the CESS includes one or more metacapacitors as an energy storage medium. Additionally, the disclosure provides a capacitor energy storage cell composed of the at least one metacapacitor and a DC-voltage conversion device, where the output voltage of the metacapacitor is the input voltage of the DC-voltage conversion device. Still further, the CESS may be comprised of a module of said capacitor energy storage cells, or a system of modules of said capacitor energy storage cells.Type: GrantFiled: December 20, 2017Date of Patent: August 17, 2021Assignee: CAPACITOR SCIENCES INCORPORATEDInventors: Ian Kelly-Morgan, Pavel Ivan Lazarev
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Patent number: 11038013Abstract: Embodiments of the present invention are directed to a back-end-of-line (BEOL) compatible metal-insulator-metal on-chip decoupling capacitor (MIMCAP). This BEOL compatible process includes a thermal treatment for inducing an amorphous-to-cubic phase change in the insulating layer of the MIM stack prior to forming the top electrode. In a non-limiting embodiment of the invention, a bottom electrode layer is formed, and an insulator layer is formed on a surface of the bottom electrode layer. The insulator layer can include an amorphous dielectric material. The insulator layer is thermally treated such that the amorphous dielectric material undergoes a cubic phase transition, thereby forming a cubic phase dielectric material. A top electrode layer is formed on a surface of the cubic phase dielectric material of the insulator layer.Type: GrantFiled: July 24, 2019Date of Patent: June 15, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul Jamison, Takashi Ando, John Greg Massey, Eduard Cartier
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Patent number: 11031365Abstract: A semiconductor device including a mounting substrate, a semiconductor chip, a rear-surface metal layer, an AuSn solder layer, and a solder blocking metal layer, is disclosed. The semiconductor chip is mounted on the mounting substrate, and includes front and rear surfaces, and a heat generating element. The rear-surface metal layer includes gold (Au). The AuSn solder layer is located between the mounting substrate and the rear surface to fix the semiconductor chip to the mounting substrate. The solder blocking metal layer is located between the rear surface and the mounting substrate, and in a non-heating region excluding a heating region in which the heat generating element is formed. The solder blocking metal layer includes at least one of NiCr, Ni and Ti and extends to an edge of the semiconductor chip. A void is provided between the solder blocking metal layer and the AuSn solder layer.Type: GrantFiled: June 24, 2019Date of Patent: June 8, 2021Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Fumio Yamada
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Patent number: 10978249Abstract: A thin-film device that includes a base portion and a rewiring layer. The rewiring layer includes a first resin insulating layer and a second resin insulating layer, which are sequentially arranged from a side of the base portion, metallic layers and close-contact layers. The metallic layers and the close-contact layers form a respective wiring electrodes. These wiring electrodes are disposed at an interface between the first resin insulating layer and the second resin insulating layer. At an end portion of the wiring electrodes, the close-contact layer projects from the metallic layer by a first predetermined length along the interface.Type: GrantFiled: March 18, 2019Date of Patent: April 13, 2021Assignee: MURATA MANUFACTURING CO, LTD.Inventor: Souko Fukahori
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Patent number: 10964614Abstract: A semiconductor device includes a dielectric layer, a conductive layer formed over the dielectric layer, and a reduction sacrificial layer formed between the dielectric layer and the conductive layer, wherein the reduction sacrificial layer includes a first reduction sacrificial material having higher electronegativity than the dielectric layer, and a second reduction sacrificial material having higher electronegativity than the first reduction sacrificial material.Type: GrantFiled: December 27, 2018Date of Patent: March 30, 2021Assignee: SK hynix Inc.Inventors: Sang Young Lee, Kyung Woong Park, Han Joon Kim
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Patent number: 10906017Abstract: Disclosed herein is a solar reactor comprising a reactor member; an aperture for receiving solar radiation, the aperture being disposed in a plane on a wall of the reactor member, where the plane is oriented at any angle other than parallel relative to the centerline of the reactor member; a plurality of absorber tubes, wherein the absorber tubes are oriented such that their respective centerlines are at an angle other than 90° relative to the centerline of the reactor member; and wherein the aperture has a hydraulic diameter that is from 0.2 to 4 times a hydraulic diameter of at least one absorber tube in the plurality of absorber tubes; and a reactive material, the reactive material being disposed in the plurality of absorber tubes.Type: GrantFiled: July 10, 2017Date of Patent: February 2, 2021Assignee: University of Florida Research Foundation, Inc.Inventors: James F. Klausner, Joerg Petrasch, Nicholas AuYeung, Ayyoub Mehdizadeh Momen, Rishi Mishra, Jinchao Lu, David Worthington Hahn, Nikhil Sehgal, Renwei Mei, Benjamin Greek, Fotouh A. Al-Raqom, Kyle Allen
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Patent number: 10903003Abstract: A capacitor component includes: a semiconductor substrate including first and second portions, a trench penetrating through the substrate from one surface of the substrate to the other surface of the substrate to separate the first and second portions of the substrate from each other, a dielectric layer disposed in the trench and on the one surface of the substrate; a first pad electrode and a second pad electrode spaced apart from each other, and penetrating through the dielectric layer to be in contact with the first and second portions of the substrate, respectively, and a passivation layer disposed on the dielectric layer, covering portions of the first pad electrode and the second pad electrode, and exposing at least a portion of each of the first pad electrode and the second pad electrode.Type: GrantFiled: August 17, 2018Date of Patent: January 26, 2021Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Chang Soo Jang, Ho Phil Jung, Seung Mo Lim, Tae Joon Park
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Patent number: 10896786Abstract: The present invention provides a process for fabricating an n-cell supercapacitor stack, including a step of providing at least n+1 identical, or substantially identical, electrically inert conductive sheets having a defined perimeter, n identical, or substantially identical, ion-permeable insulating sheets having a defined perimeter, n identical, or substantially identical, first electrodes having a defined perimeter, n identical, or substantially identical, second electrodes having a defined perimeter, and at least n matching dielectric frames having an outer perimeter, which is larger than the perimeter of the conductive sheet and the perimeter of the insulating sheet; a step of assembling the supercapacitor stack, a step of disposing an additional conductive sheet on top of the nth second electrode; and a step of attaching adjacent units onto one another, such that at least one of the frames within each unit is attached to at least one of the frames within each respective unit adjacent thereto.Type: GrantFiled: December 28, 2017Date of Patent: January 19, 2021Assignee: POCELL TECH LTD.Inventors: Frederic Derfler, Ervin Tal-Gutelmacher, Mordechay Moshkovich, Tamir Stein
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Patent number: 10879347Abstract: A capacitor that includes a first capacitor layer having a first substrate provided with a first trench structure having a trench, a first electrode, and a second electrode provided in a region of the first trench structure that includes a trench, and a second capacitor layer having a second substrate, a third electrode, and a fourth electrode. Moreover, the first capacitor layer and the second capacitor layer are disposed such that the second electrode and the third electrode oppose each other and are electrically connected.Type: GrantFiled: July 25, 2019Date of Patent: December 29, 2020Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Yasuhiro Murase, Tomoyuki Ashimine, Hiroshi Nakagawa
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Patent number: 10872725Abstract: A ceramic dielectric includes a plurality of semi-conductive grains including a semiconductor oxide including barium (Ba), titanium (Ti), and a rare earth element. A ceramic dielectric also includes an insulative oxide located between adjacent semiconductor grains and an acceptor element including manganese (Mn), magnesium (Mg), aluminum (Al), iron (Fe), scandium (Sc), gallium (Ga), or a combination thereof, a method of manufacturing the ceramic dielectric, and a ceramic electronic component, and an electronic device including the ceramic dielectric.Type: GrantFiled: August 10, 2018Date of Patent: December 22, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung-Seok Moon, Hyeon Cheol Park, Chan Kwak, Hyun Sik Kim, Daejin Yang, Youngjin Cho
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Patent number: 10777709Abstract: Provided is a substrate with transparent electrode, which is capable of achieving both acceleration of crystallization dining a heat treatment and suppression of crystallization under a normal temperature environment. In the substrate with transparent electrode, a transparent electrode thin-film formed of a transparent conductive oxide is formed on a film substrate. An underlayer that contains a metal oxide as a main component is formed between the film substrate and the transparent electrode thin-film. The underlayer and the transparent electrode thin-film are in contact with each other. The transparent electrode thin-film is amorphous, and the base layer is dielectric and crystalline.Type: GrantFiled: March 6, 2019Date of Patent: September 15, 2020Assignee: KANEKA CORPORATIONInventors: Takashi Kuchiyama, Hironori Hayakawa, Hiroaki Ueda, Yuji Motohara, Kenji Yamamoto
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Patent number: 10755854Abstract: Provided is a thin film capacitor that includes: a first electrode layer having a principal surface in which a plurality of recesses are provided; a dielectric layer laminated on the principal surface of the first electrode layer; and a second electrode layer laminated on the dielectric layer. When a depth of the recess is defined as FL and a thickness of the dielectric layer is defined as T, H/T is 0.05 or more and 0.5 or less.Type: GrantFiled: September 28, 2018Date of Patent: August 25, 2020Assignee: TDK CORPORATIONInventors: Masahiro Hiraoka, Hitoshi Saita, Suguru Andoh, Atsuo Matsutani
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Patent number: 10658114Abstract: A multilayer ceramic capacitor includes: a ceramic body including dielectric layers and having first and second surfaces opposing each other, third and fourth surfaces connecting the first and second surfaces to each other, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other; a plurality of internal electrodes disposed in the ceramic body, each exposed to the first and second surfaces and having one ends exposed to the third or fourth surface; and a first side margin portion and a second side margin portion disposed, respectively, on the first and second surfaces of the ceramic body, wherein a metal or a metal oxide is disposed in each of the first and second side margin portions, and a ratio of a diameter of the metal or the metal oxide to a thickness of the dielectric layer is 0.8 or less.Type: GrantFiled: October 29, 2018Date of Patent: May 19, 2020Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Yong Park, Ji Hong Jo, Ki Pyo Hong
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Patent number: 10650969Abstract: A multilayer ceramic capacitor includes: a ceramic body including dielectric layers and having first and second surfaces opposing each other, third and fourth surfaces connecting the first and second surfaces to each other, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other; a plurality of internal electrodes disposed in the ceramic body, each exposed to the first and second surfaces and having one ends exposed to the third or fourth surface; and a first side margin portion and a second side margin portion disposed, respectively, on the first and second surfaces of the ceramic body, wherein a metal or a metal oxide is disposed in each of the first and second side margin portions, and a ratio of a diameter of the metal or the metal oxide to a thickness of the dielectric layer is 0.8 or less.Type: GrantFiled: February 13, 2019Date of Patent: May 12, 2020Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Yong Park, Ji Hong Jo, Ki Pyo Hong
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Patent number: 10650978Abstract: Some embodiments include an apparatus having horizontally-spaced bottom electrodes supported by a supporting structure. Leaker device material is directly against the bottom electrodes. Insulative material is over the bottom electrodes, and upper electrodes are over the insulative material. Plate material extends across the upper electrodes and couples the upper electrodes to one another. The plate material is directly against the leaker device material. The leaker device material electrically couples the bottom electrodes to the plate material, and may be configured to discharge at least a portion of excess charge from the bottom electrodes to the plate material. Some embodiments include methods of forming apparatuses which include capacitors having bottom electrodes and top electrodes, with the top electrodes being electrically coupled to one another through a conductive plate. Leaker devices are formed to electrically couple the bottom electrodes to the conductive plate.Type: GrantFiled: December 15, 2017Date of Patent: May 12, 2020Assignee: Micron Technology, Inc.Inventors: Ashonita A. Chavan, Beth R. Cook, Manuj Nahar, Durai Vishak Nirmal Ramaswamy
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Patent number: 10593483Abstract: An improved multilayer ceramic capacitor is described. The multilayered ceramic capacitor comprises first internal electrodes and second internal electrodes. The first internal electrodes and said second internal electrodes are parallel with dielectric there between. A first external termination is in electrical connection with the first internal electrodes and a second external termination is in electrical contact with the second internal electrodes. A closed void layer, comprising at least one closed void, is between electrodes.Type: GrantFiled: January 28, 2019Date of Patent: March 17, 2020Assignee: KEMET Electronics CorporationInventor: John Bultitude
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Patent number: 10305295Abstract: The present disclosure provides an energy storage cell comprising at least one capacitive energy storage device and a DC-voltage conversion device. The capacitive energy storage device comprises at least one meta-capacitor. The output voltage of the capacitive energy storage device is the input voltage of the DC-voltage conversion device. The present disclosure also provides a capacitive energy storage module and a capacitive energy storage system.Type: GrantFiled: February 12, 2016Date of Patent: May 28, 2019Assignee: Capacitor Sciences IncorporatedInventors: Ian S. G. Kelly-Morgan, Matthew R. Robinson, Paul Furuta, Daniel Membreno, Pavel Ivan Lazarev
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Patent number: 10270010Abstract: Provided is a substrate with transparent electrode, which is capable of achieving both acceleration of crystallization during a heat treatment and suppression of crystallization under a normal temperature environment. In the substrate with transparent electrode, a transparent electrode thin-film formed of a transparent conductive oxide is formed on a film substrate. An underlayer that contains a metal oxide as a main component is formed between the film substrate and the transparent electrode thin-film. The underlayer and the transparent electrode thin-film are in contact with each other. The transparent electrode thin-film is amorphous, and the base layer is dielectric and crystalline.Type: GrantFiled: January 19, 2015Date of Patent: April 23, 2019Assignee: KANEKA CORPORATIONInventors: Takashi Kuchiyama, Hironori Hayakawa, Hiroaki Ueda, Yuji Motohara, Kenji Yamamoto
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Patent number: 10199167Abstract: A thin-film ceramic capacitor includes a body, a plurality of dielectric layers and first and second electrode layers alternately disposed on a substrate in the body, first and second electrode pads disposed on an external surface of the body, and a plurality of vias disposed in the body, the plurality of dielectric layers and first and second electrode layers having inclined etched surfaces exposed to the plurality of vias, a first via, of the plurality of vias, being connected to the inclined surface of the first electrode layer, and a second via, of the plurality of vias, being connected to the inclined surface of the second electrode layer.Type: GrantFiled: July 5, 2017Date of Patent: February 5, 2019Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seung Hun Han, Sung Min Cho, Tae Joon Park, Hyun Ho Shin, Sang Kee Yoon
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Patent number: 10157696Abstract: In a communication cable having a multi-core cable with a plurality of core cables in which a pair of signal lines are covered with an insulator, in which the insulator is covered with a shield tape, and in which the shield tape is covered with a wrapping tape, and having a connector formed on an end portion of the multi-core cable, the communication cable further has a case which is inserted/removed to/from a slot formed on a communication device to which the communication cable is connected, a substrate which is housed in the case and to which an end portion of the multi-core cable is connected, and a resin portion which molds a connection portion between the end portion of the multi-core cable and the substrate.Type: GrantFiled: June 1, 2017Date of Patent: December 18, 2018Assignee: Hitachi Metals, Ltd.Inventors: Hideki Nonen, Takashi Kumakura
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Patent number: 10068706Abstract: A multilayer polymer dielectric film includes a stack of coextruded, alternating first dielectric layers and second dielectric layers that receive electrical charge. The first dielectric layers include a first polymer material and the second dielectric layers include a second polymer material different from the first polymer material. The first polymer material has a permittivity greater than the second polymer material. The second polymer material has a breakdown strength greater than the first polymer material. Adjoining first dielectric layers and second dielectric layers define an interface between the layers that delocalizes electrical charge build-up in the layers. The stack has substantially the crystallographic symmetry before and during receiving electrical charge.Type: GrantFiled: January 11, 2017Date of Patent: September 4, 2018Assignee: Case Western Reserve UniversityInventors: Eric Baer, Anne Hiltner, James S. Shirk, Mason A. Wolak
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Patent number: 10008559Abstract: A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.Type: GrantFiled: January 31, 2017Date of Patent: June 26, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Hao Chen, Che-Cheng Chang, Wen-Tung Chen, Yu-Cheng Liu, Horng-Huei Tseng
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Patent number: 9875846Abstract: A heated capacitor runs current through either a lower metal plate, an upper metal plate, a lower metal trace that lies adjacent to a lower metal plate, an upper metal trace that lies adjacent to an upper metal plate, or both a lower metal trace that lies adjacent to a lower metal plate and an upper metal trace that lies adjacent to an upper metal plate to generate heat from the resistance to remove moisture from a moisture-sensitive insulating layer.Type: GrantFiled: February 12, 2016Date of Patent: January 23, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Honglin Guo, Byron Lovell Williams
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Patent number: 9671907Abstract: A touch module and a touch panel comprising the same are provided. The touch panel comprises a substrate and a touch module disposed on the substrate. The touch module comprises a first conductive element, a second conductive element, and a dielectric element disposed between the first conductive element and the second conductive element, whereby the first conductive element are electrically insulated from the second conductive element. The dielectric element has a thickness equal to or less than 1 micrometer, and thereby it is beneficial to achieve miniaturization of the touch panel.Type: GrantFiled: January 22, 2014Date of Patent: June 6, 2017Assignee: TPK Touch Solutions (Xiamen) Inc.Inventors: I-Chung Hsu, Kuo-Shu Hsu
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Patent number: 9633953Abstract: A methodology for addressing package warpage is described. In an embodiment a package includes a die mounted on a wiring board. Portion of a metal plane within the wiring board includes a reduced portion, characterized by a reduced thickness that is less than a baseline thickness.Type: GrantFiled: October 20, 2014Date of Patent: April 25, 2017Assignee: Apple Inc.Inventors: Jun Chung Hsu, Jie-Hua Zhao
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Patent number: 9580611Abstract: The aim of the invention is to create a composition for coating electric conductors which is significantly more resistant to partial discharges than prior art compositions while the produced insulating layer is highly extensible. Said aim is achieved by a composition comprising 1 to 50 percent by weight of microparticles that have a specifically adjusted electronic defect structure in the crystal lattice, resulting in greater polarizability of the valence electrons, and an organic and/or organic-inorganic matrix.Type: GrantFiled: September 4, 2007Date of Patent: February 28, 2017Assignee: Leibniz-Institut fuer neue Materialien gemeinnuetzige Gesellschaft mit beschraenkter HaftungInventors: Sener Albayrak, Carsten Becker-Willinger, Michael Veith, Oral Cenk Aktas
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Patent number: 9572258Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a substrate core by attaching a first dielectric layer to a second conductive layer of a thin film capacitor, and attaching a second dielectric layer to a first conductive layer of the thin film capacitor.Type: GrantFiled: December 30, 2004Date of Patent: February 14, 2017Assignee: Intel CorporationInventors: Sriram Srinivasan, John S. Guzek, Cengiz A. Palanduz, Victor Prokofiev, Joel A. Auernheimer
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Patent number: 9560762Abstract: A semiconductor device includes a semiconductor chip, a plurality of external terminals, and a board. The board includes a first main surface in which a plurality of first electrodes electrically connected to the semiconductor chip are formed, a second main surface in which a plurality of second electrodes electrically connected to the plurality of external terminals are formed, and a plurality of interconnect layers, provided between the first main surface and the second main surface, for forming a plurality of signal paths that electrically connect the first electrode and the second electrode corresponding thereto. The interconnect layer includes a plurality of metal members which are dispersedly disposed at a distance shorter than an electromagnetic wavelength equivalent to a signal band of a signal supplied to the signal path, in the vicinity of a portion in which a structure of an interconnect for forming the signal path is changed.Type: GrantFiled: October 9, 2013Date of Patent: January 31, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Ryuichi Oikawa
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Patent number: 9383334Abstract: In a method for manufacturing an ion-sensitive structure for an ion-sensitive sensor, first a semiconductor substrate bearing an oxide layer is provided, whereupon a metal oxide layer and a metal layer are deposited and tempered, in order to obtain a layer sequence having a crystallized metal oxide layer and an oxidized and crystallized metal layer on the semiconductor substrate bearing the oxide layer. In such case, the metal oxide layer and the metal layer have a compatible metal element, and the coating thickness dMOX of the metal oxide layer is greater than the coating thickness dMET of the metal layer.Type: GrantFiled: August 20, 2014Date of Patent: July 5, 2016Assignee: Endress+Hauser Conducta GmbH+Co. KGInventors: Christian Kunath, Eberhard Kurth, Torsten Pechstein
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Patent number: 9379174Abstract: A reconstituted electronic device comprising at least one die and at least one passive component. A functional material is incorporated in the substrate of the device to modify the electrical behavior of the passive component. The passive component may be formed in redistribution layers of the device. Composite functional materials may be used in the substrate to forms part of or all of the passive component. A metal carrier may form part of the substrate and part of the at least one passive component.Type: GrantFiled: July 25, 2014Date of Patent: June 28, 2016Assignee: QUALCOMM TECHNOLOGIES INTERNATIONAL, LTD.Inventors: Vlad Lenive, Simon Stacey
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Patent number: 9281125Abstract: A dielectric ceramic is formed with sintered grains constituting the dielectric have an average grain size of 0.2 to 1.0 ?m and an oxygen defect concentration of 0.2 to 0.5%. An acceptor element is added to the dielectric ceramic by no more than 0.5 mol per 100 mol of the primary component of BaTiO3. The oxygen defect concentration is temporarily increased by reduction and sintering, after which the oxygen defect concentration is reduced through the subsequent re-oxidization process. Crystal strain generated in the re-oxidization process increases the dielectric constant.Type: GrantFiled: July 23, 2013Date of Patent: March 8, 2016Assignee: TAIYO YUDEN CO., LTD.Inventors: Katsuya Taniguchi, Tetsuo Shimura
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Patent number: 9178006Abstract: A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly-doped or non-doped material. The highly doped material will remain amorphous (<30% crystalline) after an anneal step. The high band gap material will remain amorphous (<30% crystalline) after an anneal step. The lightly-doped or non-doped material will become crystalline (?30% crystalline) after an anneal step. The high band gap material is formed between the amorphous highly doped material and the lightly or non-doped material and provides an intermediate barrier to conduction through the multi-layer dielectric stack.Type: GrantFiled: February 10, 2014Date of Patent: November 3, 2015Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Xiangxin Rui, Hanhong Chen, Naonori Fujiwara, Imran Hashim, Kenichi Koyanagi
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Patent number: 9084371Abstract: Disclosed is a wiring substrate that is provided with a wiring pattern formed from a metal plate, and an insulation layer as a base material to which the wiring pattern is to be fixed. The wiring pattern has a mounting pad for having electronic parts (11) surface-mounted. Electronic parts are mounted onto the surface of the wiring pattern, by pouring solder into the mounting pad of the wiring pattern.Type: GrantFiled: July 27, 2010Date of Patent: July 14, 2015Assignee: KABUSHIKI KAISHA TOYOTA JIDOSHOKKIInventors: Hitoshi Shimadu, Kazunori Kondou, Takehiko Sawada, Takahiro Hayakawa, Tomoaki Asai, Ryou Yamauchi
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Patent number: 9030800Abstract: A thin film capacitor includes an under electrode, a plurality of dielectric body layers and a plurality of internal electrode layers that are alternately laminated on the under electrode, the internal electrode layers respectively including protrusion parts that each protrude from the dielectric body layers viewed in the lamination direction, and connection electrodes to which at least a portion of each of the protrusion parts contacts. Assuming that protrusion amounts of the protrusion parts of the internal electrode layers that are connected to the same connection electrode are regarded as L, a protrusion amount Ln of a protrusion part of nth (n?2) internal electrode layer from the under electrode side is smaller than another protrusion amount Ln-1 of another protrusion part of (n?1)th internal electrode layer.Type: GrantFiled: March 12, 2013Date of Patent: May 12, 2015Assignee: TDK CorporationInventors: Tatsuo Namikawa, Yoshihiko Yano, Yasunobu Oikawa