Abstract: A metallized film capacitor includes a dielectric film and two metal vapor-deposition electrodes facing each other across the dielectric film. At least one of the metal vapor-deposition electrodes is made of substantially only aluminum and magnesium. This metallized film capacitor has superior leak current characteristics and moisture resistant performances, and can be used for forming a case mold type capacitor with a small size.

Abstract: A low capacitance density, high voltage MIM capacitor and the high density MIM capacitor and a method of manufacture are provided. The method includes depositing a plurality of plates and a plurality of dielectric layers interleaved with one another. The method further includes etching a portion of an uppermost plate of the plurality of plates while protecting other portions of the uppermost plate. The protected other portions of the uppermost plate forms a top plate of a first metal-insulator-metal (MIM) capacitor and the etching exposes a top plate of a second MIM capacitor.

Abstract: A crystalline perovskite crystalline composite paraelectric material includes nano-regions containing rich N3? anions dispersed in a nano-grain sized matrix of crystalline oxide perovskite material, wherein (ABO3-?)?-(ABO3-?-?N?)1-?. A represents a divalent element, B represents a tetravalent element, ? satisfies 0.005???1.0, 1-? satisfies 0.05?1-??0.9, and 1-? is an area ratio between the regions containing rich N3? anions and the matrix of remaining oxide perovskite material.

Abstract: Disclosed is an electrical isolator circuit comprising an input stage comprising first and second inputs, the input stage being configured to receive an input voltage signal; an output stage comprising first and second outputs electrically connected across a load capacitor; and a DC isolator comprising a first capacitor between said first input and said first output and second capacitor between said second input and said second output. The first and second plates of each of the first, second and load capacitors are defined by conductive layers of a printed circuit board and the dielectric of each of the first, second and load capacitors are defined by a non-conducting part of the printed circuit board.

Abstract: A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit.

Abstract: There is provided a multilayer ceramic capacitor, including: a multilayer body in which a plurality of dielectric layers are stacked in a thickness direction; and inner electrode layers formed within the multilayer body and including first and second inner electrodes disposed to be opposed to each other; wherein a ratio (MA1/CA1) of MA1 to CA1 is between 0.07 and 0.20, wherein CA1 represents an area of the multilayer body in a cross section of the multilayer body taken in a length and thickness direction, and MA1 represents an area of a first margin part in the cross section of the multilayer body taken in the length and thickness direction, the first margin part being a portion of the multilayer body, other than a first capacitance forming part thereof in which the first and second inner electrodes overlap in the thickness direction.

Abstract: A capacitor having improved tolerance to humidity. The capacitor includes a packaging material and/or a dielectric material comprising a film having a water vapor transmission rate significantly lower than the dielectric films and/or packaging films used in conventional capacitors.

Abstract: Provided is a laminated ceramic capacitor that can suppress the decrease in insulation resistance after a moisture-resistance loading test. It contains ceramic layers which include: main-phase grains that have a perovskite-type compound containing Ba and Ti and optionally containing Ca, Sr, Zr, and Hf; and secondary-phase grains that have an average grain size of 100 nm or more and have a Si content of 50 mol % or more per grain, the average grain boundary number, represented by (Average Thickness for Ceramic Layers 3)/(Average Grain Size for Main Phase Grains)?1, is greater than 0 and 3.0 or less, and the average grain size for the secondary-phase grains is ¼ or more of the average thickness for the ceramic layers 3.

Abstract: A power system can include an input configured to be coupled to a utility grid. The power system can further include an electrical energy storage unit comprising a dielectric layer disposed between first and second electrode layers, the dielectric layer comprising a high permittivity ceramic material. In an embodiment, the power system can include a control computer can control a first switch to deactivate a main electrical energy storage unit that includes the electrical energy storage unit, and to control the second switch to activate a backup energy storage unit. In a further embodiment, the power system can include an output coupled to the utility power grid. In a further embodiment, the power system can include a control computer to control a first switch to deactivate a main electrical energy storage unit, and to control a second switch to activate an electrical energy storage unit buffer.

Abstract: The present invention discloses an electrostatic energy storage device and a preparation method thereof. The device comprises at least one electrostatic energy storage unit, wherein each electrostatic energy storage unit is provided with a five-layer structure and comprises two metal film electrodes which form a capacitor, composite nano insulating film layers attached to the inner sides of the two metal film electrodes, and a ceramic nano crystalline film arranged between the composite nano insulating film layers. Based on the electrostatic parallel-plate induction capacitor principle, the metal film electrodes with a nano microstructure and the ceramic nano crystalline film sandwiched between the metal film electrodes and having an ultrahigh dielectric constant form an electrostatic induction plate capacitor to store electrostatic energy.

Abstract: A capacitor and a manufacturing method thereof with improved capacitance density, simplified production process, and/or improved high frequency characteristic without having to form a nano-scale pattern are provided. A capacitor element 12 includes a dielectric layer made of porous oxide substrate, first and second internal electrodes formed within holes of the porous oxide substrate, a first external electrode electrically connected to the first internal electrode, a second external electrode electrically connected to the second internal electrodes.

Abstract: A capacitor forming method includes forming an electrically conductive support material over a substrate, with the support material containing at least 25 at % carbon. The method includes forming an opening through at least the support material where the opening has an aspect ratio of at least 20:1 within a thickness of the support material. After forming the opening, the method includes processing the support material to effect a reduction in conductivity, and forming a capacitor structure in the opening.

Abstract: A capacitive device includes a first capacitor including a first wiring layer, a first dielectric film, a first conductive layer, a first insulating layer on the first capacitor, a second capacitor on the first insulating layer including a second conductive layer, a second dielectric film, and a third conductive layer, a second insulating layer on the second capacitor, a second wiring layer on the second insulating layer including first and second connection wires, a first via connecting the first wiring layer to the second conductive layer, a second via connecting the third conductive layer to the second wiring layer, a third via connecting the first connection wire to the first conductive layer, and a fourth via connecting the second connection wire to the first wiring layer.

Abstract: In a structure or device having a pair of electrical conductors separated by an insulator across which a voltage is placed, resistive layers are formed around the conductors to force the electric potential within the insulator to distribute more uniformly so as to decrease or eliminate electric field enhancement at the conductor edges. This is done by utilizing the properties of resistive layers to allow the voltage on the electrode to diffuse outwards, reducing the field stress at the conductor edge. Preferably, the resistive layer has a tapered resistivity, with a lower resistivity adjacent to the conductor and a higher resistivity away from the conductor. Generally, a resistive path across the insulator is provided, preferably by providing a resistive region in the bulk of the insulator, with the resistive layer extending over the resistive region.

Abstract: A method for manufacturing a multilayer ceramic electronic component significantly reduces and prevents swelling or distortion when a conductive paste is applied to a green ceramic element body. A ceramic green sheet used in the method satisfies 180.56?A/B wherein A is a polymerization degree of an organic binder contained in the ceramic green sheet, and B is a volume content of a plasticizer contained in the ceramic green sheet.

Abstract: A ceramic multilayer surface-mount capacitor with inherent crack mitigation void patterning to channel flex cracks into a safe zone, thereby negating any electrical failures.

Abstract: An electrical multi-layered component includes a monolithic base member that has a plurality of ceramic layers and electrode layers disposed one on top of the other in alternating fashion. The base member includes two end surfaces opposite to one another and two side surfaces opposite to one another. The multi-layered component includes a plurality of external electrodes and a plurality of internal electrodes designed into the electrode layers. The internal electrodes at least partially overlap and form overlap areas. Each internal electrode is associated with a respective external electrode. At least one first internal electrode extending from an end surface overlaps with at least one second internal electrode (8) extending from an opposite end surface. At least a third internal electrode extends from an end surface.

Abstract: A capacitor structure of capacitive touch panel including a first electrode layer, a first material layer, a second material layer and a second electrode layer is provided. The first material layer is disposed on the first electrode layer, and the material of the first material layer is selected from one of a semiconductor material and an insulating material. The second material layer is disposed on the first material layer, and the material of the second material layer is selected from another one of the semiconductor material and the insulating material. The second electrode layer is disposed on the second material layer.

Abstract: A method manufactures a capacitor having polycrystalline dielectric layer between two metallic electrodes. The dielectric layer is formed by a polycrystalline growth of a dielectric metallic oxide on one of the metallic electrodes. At least one polycrystalline growth condition of the dielectric oxide is modified during the formation of the polycrystalline dielectric layer, which results in a variation of the polycrystalline properties of the dielectric oxide within the thickness of said layer.

Abstract: A capacitor having improved tolerance to humidity. The capacitor includes a packaging material and/or a dielectric material comprising a film having a water vapor transmission rate significantly lower than the dielectric films and/or packaging films used in conventional capacitors.

Abstract: Methods of manufacturing metal-insulator-metal capacitor structures, and the metal-insulator-metal capacitor structures obtained, are disclosed. In one embodiment, a method includes providing a substrate, forming on the substrate a first metal layer comprising a first metal, and using atomic layer deposition with an H2O oxidant to deposit on the first metal layer a protective layer comprising TiO2. The method further includes using atomic layer deposition with an O3 oxidant to deposit on the protective layer a dielectric layer of a dielectric material, and forming on the dielectric layer a second metal layer comprising a second metal. In another embodiment, a metal-insulator-metal capacitor includes a bottom electrode comprising a first metal, a protective layer deposited on the bottom electrode and comprising TiO2, a dielectric layer deposited on the protective layer and comprising a dielectric material, and a top electrode formed on the dielectric layer and comprising a second metal.

Abstract: A multilayer ceramic capacitor, having a plurality of electrode layers and a plurality of substantially titanium dioxide dielectric layers, wherein each respective titanium dioxide dielectric layer is substantially free of porosity, wherein each respective substantially titanium dioxide dielectric layer is positioned between two respective electrode layers, wherein each respective substantially titanium dioxide dielectric layer has an average grain size of between about 200 and about 400 nanometers, wherein each respective substantially titanium dioxide dielectric layer has maximum particle size of less than about 500 nanometers. Typically, each respective substantially titanium dioxide dielectric layer further includes at least one dopant selected from the group including P, V, Nb, Ta, Mo, W, and combinations thereof, and the included dopant is typically present in amounts of less than about 0.01 atomic percent.

Abstract: There is provided a multi-layered ceramic capacitor having a dual layer-electrode structure formed by applying a dual layer of electrode paste to the multi-layered ceramic capacitor. The multi-layered ceramic capacitor having a dual layer-electrode structure includes a capacitor body having a preset length and width and having a plurality dielectric layers stacked therein, an internal electrode unit formed on the plurality of dielectric layers and having a preset capacitance, and an external electrode unit including first external electrodes respectively formed on both sides of the capacitor body to be electrically connected to internal electrodes, and second external electrodes formed on the first external electrodes.

Abstract: An anchor group anchors organic dielectric compounds used in the production of organically based capacitors. The capacitors referred to are those that can be produced in a parallel process on a prepeg or other common printed circuit board substrate without additional metallization on copper. The pre-fabricated capacitor layer can then be built into the printed circuit board, thereby gaining on space and cost for the surface of the printed circuit board.

Abstract: A multilayer polymer dielectric film includes a coextruded first dielectric layer and second dielectric layer. The first dielectric includes a first polymer material and the second dielectric layer includes a second polymer material. The first dielectric layer and the second dielectric layer defining an interface between the layers that delocalizes charges in the layers.

Abstract: A method and apparatus for a reverse metal-insulator-metal (MIM) capacitor. The apparatus includes a lower metal layer, a bottom electrode, and an upper metal layer. The lower metal layer is disposed above a substrate layer. The bottom electrode is disposed above the lower metal layer and coupled to the lower metal layer. The upper metal layer is disposed above the bottom electrode. The upper metal layer comprises a top electrode of a metal-insulator-metal (MIM) capacitor.

Abstract: To provide a thin-film capacitor capable of improving the stability of electric connection between an internal electrode layer and a connection electrode. The thin-film capacitor comprises: two or more dielectric layers deposited above a base electrode; an internal electrode layer being deposited between the dielectric layers and having a projecting portion which projects from the dielectric layer when seen from a laminating direction; and a connection electrode electrically connected to the internal electrode layer via at least a part of a surface and an end face of the internal electrode layer included in the projecting portion, wherein a ratio L/t between a projection amount L of the projecting portion of the internal electrode layer with respect to the dielectric layer and a thickness t of the internal electrode layer is 0.5 to 120.

Abstract: An electrical multi-layered component includes a monolithic base member that has a plurality of ceramic layers and electrode layers disposed one on top of the other in alternating fashion. The base member includes two end surfaces opposite to one another and two side surfaces opposite to one another. The multi-layered component includes a plurality of external electrodes and a plurality of internal electrodes designed into the electrode layers. The internal electrodes at least partially overlap and form overlap areas. Each internal electrode is associated with a respective external electrode. At least one first internal electrode extending from an end surface overlaps with at least one second internal electrode (8) extending from an opposite end surface. At least a third internal electrode extends from an end surface.

Abstract: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Abstract: A stacked film capacitor including a resin protective film having excellent durability is provided which can stably secure desired properties. The stacked film capacitor includes a capacitor element including a plurality of dielectric layers, and a plurality of vapor-deposited metal film layers. Each dielectric layer and each vapor-deposited metal film layer are stacked with each other so as to be arranged alternately. The stacked film capacitor further includes a pair of external electrodes provided on opposing side surfaces of the capacitor element, and at least one resin protective film formed on at least one side surfaces other than the side surfaces on which the external electrodes are formed, in which the at least one resin protective film is provided by deposition polymerization.

Abstract: A metallized film capacitor includes a dielectric film and two metal vapor-deposition electrodes facing each other across the dielectric film. At least one of the metal vapor-deposition electrodes is made of substantially only aluminum and magnesium. This metallized film capacitor has superior leak current characteristics and moisture resistant performances, and can be used for forming a case mold type capacitor with a small size.

Abstract: In an electronic component, a laminate includes a plurality of laminated ceramic layers and a mounting surface defined by outer edges of the plurality of laminated ceramic layers, the outer edges being continuously located adjacent to each other. Capacitor conductors are disposed on the ceramic layers and include exposed portions that are exposed at the mounting surface between the ceramic layers. An electroconductive layer defining an external electrode is arranged to directly cover the exposed portions and is formed by plating so as to be made of plated material. Another electroconductive layer covers the above-mentioned electroconductive layer and partially covers surfaces of the laminate, and it is made of a material including metal and one of glass and resin.

Abstract: Systems and methods in accordance with embodiments of the invention implement micro- and nanoscale capacitors that incorporate a conductive element that conforms to the shape of an array elongated bodies. In one embodiment, a capacitor that incorporates a conductive element that conforms to the shape of an array of elongated bodies includes: a first conductive element that conforms to the shape of an array of elongated bodies; a second conductive element that conforms to the shape of an array of elongated bodies; and a dielectric material disposed in between the first conductive element and the second conductive element, and thereby physically separates them.

Abstract: There is provided a multilayer ceramic electronic part, including: a ceramic body including dielectric layers each having an average thickness of 0.6 ?m or less; and first and second internal electrodes disposed to face each other within the ceramic body with the dielectric layer interposed therebetween, wherein the ceramic body includes a capacitance forming part and non-capacitance forming parts, and when the capacitance forming part is divided into 2n+1 (n is 1 or more) regions in a thickness direction of the ceramic body, the dielectric layers of the capacitance forming part get thinner in directions from a central region toward upper and lower regions, whereby continuity of the internal electrode may be improved and a high-capacity multilayer ceramic electronic part may be realized.

Abstract: An on-chip capacitor includes a first layer first polarity conducting strip and a first layer second polarity conducting strip, wherein the first layer second polarity conducting strip is arranged adjacent to and spaced apart from the first layer first polarity conducting strip, a second layer first polarity conducting strip and a second layer second polarity conducting strip, wherein the second layer second polarity conducting strip is arranged adjacent to and spaced apart from the second layer first polarity conducting strip, wherein the second layer second polarity conducting strip is arranged overlying the first layer second polarity conducting strip, wherein the second layer first polarity conducting strip is arranged overlying the first layer first polarity conducting strip; wherein the first layer first-polarity conducting strip electrically couples with the second layer first polarity conducting strip; and wherein the first-layer second polarity conducting strip electrically couples with the second la

Abstract: Some embodiments include methods of forming capacitors. A metal oxide mixture may be formed over a first capacitor electrode. The metal oxide mixture may have a continuous concentration gradient of a second component relative to a first component. The continuous concentration gradient may correspond to a decreasing concentration of the second component as a distance from the first capacitor electrode increases. The first component may be selected from the group consisting of zirconium oxide, hafnium oxide and mixtures thereof; and the second component may be selected from the group consisting of niobium oxide, titanium oxide, strontium oxide and mixtures thereof. A second capacitor electrode may be formed over the first capacitor electrode. Some embodiments include capacitors that contain at least one metal oxide mixture having a continuous concentration gradient of the above-described second component relative to the above-described first component.

Abstract: A capacitor forming unit includes a dielectric plate, a first conductor film formed on a plate upper surface region other than front and rear end portions, a first insulator film formed on the upper surface front end portion, a second insulator film formed on the upper surface rear end portion, a second conductor film formed on a plate lower surface region other than front and rear end portion, a third insulator film formed on the front end portion lower surface, and a fourth insulator film formed on the lower surface rear end portion. One or more first electrode rods are disposed in through holes, and electrically connected to the first conductor film and electrically insulated from the second conductor film. One or more second electrode rods are disposed in other through holes, and electrically connected to the second conductor film and electrically insulated from the first conductor film.

Abstract: A multilayered ceramic electronic component includes: a ceramic element having a plurality of dielectric layers laminated therein; first inner electrodes formed on the dielectric layers disposed in upper and lower portions in the ceramic element, the width of a portion of each of the first inner electrodes exposed from one end face of the ceramic element being less than that of a portion thereof disposed within the ceramic element; and second inner electrodes formed on the dielectric layers disposed in the middle portion in the ceramic element, the width of a portion of each of the second inner electrodes exposed from one end face of the ceramic element being equal to that of a portion thereof disposed within the ceramic element.

Abstract: In a method of forming an external electrode by growing plated depositions on exposed ends of a plurality of internal electrodes in a component main body, the component main body is polished to increase exposure of the internal electrodes. To prevent decreased external electrode fixing strength, a radius of curvature is reduced to about 0.01 mm or less for an R chamfered section formed in a ridge section of the component main body during polishing by ion milling, and exposed ends of the internal electrodes are recessed from end surfaces of the component main body with a recess length of about 1 ?m or less. Plating films to serve as external electrodes are formed to extend from the end surfaces of the component main body across the R chamfered section, and include end edges located on at least one of the principal surfaces and the side surfaces.

Abstract: An object of the present invention is to provide a multi-layer ceramic capacitor that includes a laminated block 4 formed by laminating ceramic dielectric layers 2 and internal electrodes 3 alternately, a pair of cover layers 5 laminated on top and bottom of the laminated block, a ceramic body 6 formed on both side surfaces of the laminated block 4, and a pair of external electrodes 7 electrically connected to the internal electrodes 3 and that can effectively prevent an occurrence of a crack. In the multi-layer ceramic capacitor 1, a silicate crystal made of an oxide including Ba and Si or a silicate crystal made of an oxide including Ti and Si is formed in boundary portions between the laminated block 4 and the ceramic bodies 6.

Abstract: Disclosed are a multilayer ceramic condenser and a method of manufacturing a multilayer ceramic condenser. There is provided a method of manufacturing a multilayer ceramic condenser, including: printing a plurality of stripe-type inner electrode patterns on a ceramic green sheet in parallel; forming a laminate by stacking ceramic green sheets on which a plurality of stripe-type inner electrode patterns are formed; cutting the laminate so that a first inner electrode pattern and a second inner electrode pattern are alternately stacked; and forming a first side part and a second side part by applying ceramic slurry in order to cover the side of the laminate to which both the first inner electrode pattern and the second inner electrode pattern are exposed.

Abstract: A capacitor includes a first metal plate; a second metal plate in close proximity to the first metal plate; a third metal plate in close proximity to the first metal plate, and at least one dielectric layer interposed between the first, second and three vertical metal plates. The first, second and third metal plate are connected to three different terminals of an integrated circuit.

Abstract: In a capacitor structure and method of forming the same, a first electrode, a second electrode, and a first insulation layer are sequentially formed on a substrate. The first and second electrodes and the first insulation layer are covered with a second insulation layer on the substrate. A first plug is in contact with the second electrode through the second insulation layer. A second plug is in contact with the first electrode through the first and second insulation layer. A third insulation layer is formed on the second insulation layer. Third and fourth comb-shaped electrodes are formed in the third insulation layer. The third electrode is contact with the first plug and the fourth electrode is contact with the second plug while facing the third electrode. Thus, the teeth of the comb-shaped electrodes are alternately arranged and spaced apart in the third insulation layer.

Abstract: The use of a monolayer or partial monolayer sequencing process, such as atomic layer deposition, to form a dielectric layer of hafnium oxide doped with dysprosium and a method of fabricating such a combination produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure can include depositing hafnium oxide onto a substrate surface using precursor chemicals, followed by depositing dysprosium oxide onto the substrate using precursor chemicals, and repeating to form a thin laminate structure. A dielectric layer of dysprosium doped hafnium oxide may be used as the gate insulator of a MOSFET, as a capacitor dielectric in a DRAM, as a tunnel gate insulator in flash memories, or as a dielectric in NROM devices, because the high dielectric constant (high-k) of the film provides the functionality of a thinner silicon dioxide film, and because the reduced leakage current of the dielectric layer when the percentage of dysprosium doping is optimized improves memory function.

Abstract: A method and structure are provided for implementing surface mount components with symmetric reference balance. A first reference and an incoming signal are received in a surface mounted device (SMD) package and a second reference and the outgoing signal are output from the SMD package. A capacitor structure is defined within the SMD package between the first reference and the second reference. The capacitor structure includes a balanced impedance structure between the first reference and the second reference. A component connected between the received incoming signal and output signal is generally centrally located within the capacitor structure.

Abstract: A capacitor structure includes a plurality of conductive line levels located over the substrate. Each of the conductive line levels includes a first conductive line and a second conductive line. The first conductive lines in the conductive line levels form a first conductive line co-plane and the second conductive lines in the conductive line levels form a second conductive line co-plane. A first conductive end is electrically connected to the first conductive lines on the conductive line levels. A second conductive end is electrically connected to the second conductive lines on the conductive line levels. A plurality of vias are located between the neighboring conductive line levels and placed on only one of the first and second conductive line co-planes on a same level.

Abstract: In a ceramic capacitor according to the present invention, an interdiginated pair of internal electrodes are arranged, on a substrate, perpendicular to a surface of the substrate, and a ceramic dielectric member is filled into a gap between this pair of internal electrodes. For this reason, the dimensions of the internal electrodes do not substantially change before and/or after the formation of the ceramic dielectric member, whereby the dimensions formed at the time of internal electrode can be maintained. According to this ceramic capacitor, since the internal electrode dimensions can be easily controlled like this, dimensional control of internal electrode spacing can also be easily carried out.

Abstract: Dielectric ceramic composition includes a hexagonal type barium titanate as a main component shown by a generic formula of (Ba1-?M?)A(Ti1-?Mn?)BO3 and having hexagonal structure wherein an effective ionic radius of 12-coordinated “M” is ?20% or more to +20% or less with respect to an effective ionic radius of 12-coordinated Ba2+ and the A, B, ? and ? satisfy relations of 1.000<(A/B)?1.040, 0??<0.003, 0.03???0.2, and as subcomponents, with respect to the main component, certain contents of alkaline earth oxide such as MgO and the like, Mn3O4 and/or Cr2O3, and CuO and Al2O3 and rare earth element oxide and glass component including SiO2. According to the present invention, it can be provided the hexagonal type barium titanate powder and the dielectric ceramic composition which are preferable for producing electronic components such as a capacitor and the like showing comparatively high specific permittivity, having advantageous insulation property and having sufficient reliability.

Abstract: A low loss capacitance and low loss insulating dielectric material consisting of a thermosetting resin, thermoplastic resin, a cross-linker, and containing a quantity of ferroelectric ceramic nano-particles of barium titanate within. The combined low loss insulating dielectric layer and a low loss capacitive layer resulting from the material allows one continuous layer that can form internal capacitors and permit the modifying the dielectric thickness between signal layers for impedance matching within a layer of substrate. More significantly, the applied layer of low loss capacitive materials can simultaneously act as a capacitor as well as a dielectric for separation of signal layers.

Abstract: An electrical contact includes a body having a mating segment. At least a portion of the mating segment defines a first conductive element having a three-dimensional (3D) surface. A dielectric layer is formed directly on the 3D surface of the first conductive element in engagement with the 3D surface. A second conductive element is formed on the dielectric layer such that the dielectric layer extends between the first and second conductive elements. The first and second conductive elements and the dielectric layer form a capacitor.