Abstract: A collective component has a first region that intersects a conductive paste film for external terminal electrodes in a break line in which break leading holes are arranged and a second region that does not intersect a conductive paste film for external terminal electrodes in the break line. The first break leading holes are formed in the first region so as not to reach the second region. The second break leading holes are formed only in the second region or from the second region to a portion of the first region. The pitch of the first break leading holes is wider than the pitch of the second break leading holes.

Abstract: A metal capacitor in which an electric conductivity is significantly improved by applying a metal material, instead of a solid electrolyte and electrolyte of an aluminum electrolytic capacitor, and a manufacturing method thereof is provided. A metal capacitor 10 includes a metal member 11 including a plurality of grooves 11a on both surfaces of the metal member 11, a metal oxide film 12 being formed on the metal member 11, a seed electrode layer 13 being formed on the metal oxide film 12, a main electrode layer 14 being formed on the metal oxide film 12 to fill the plurality of grooves 11a, a plurality of lead terminals 15 being installed in the main electrode layer 14, and a molding member 16 being disposed so that the plurality of lead terminals may be externally protruded from the molding member 16, and the metal member 11, the metal oxide film 12, the seed electrode layer 13, and the main electrode layer 14 may be sealed.

Abstract: The present invention relates to a multi-layer ceramic capacitor printed simultaneously with internal electrode and external electrode by employing an inkjet printing. A method for manufacturing the multi-layer ceramic capacitor comprising first external electrode, dielectric, internal electrode and second external electrode prints simultaneously the first external electrode; the internal electrode which is connected with the first external electrode and formed at an invaginated portion of the dielectric invaginated to allow one side to be opened at one portion; and the second external electrode which is formed integrally with the internal electrode by employing an inkjet printing. According to the present invention, a method for manufacturing the multi-layer ceramic capacitor resolves contact problems by printing integrally the internal electrode and the external electrode and reduces the manufacturing process.

Abstract: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to form the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Abstract: A chip-type electronic component has: a ceramic element body; a plurality of first and second internal electrodes arranged in the ceramic element body so as to be opposed at least in part to each other; a first external connection conductor to which the plurality of first internal electrodes are connected; a second external connection conductor to which the plurality of second internal electrodes are connected; first and second terminal electrodes; a first internal connection conductor arranged in the ceramic element body and connecting the first external connection conductor and the first terminal electrode; and a second internal connection conductor arranged in the ceramic element body and connecting the second external connection conductor and the second terminal electrode.

Abstract: Density-conforming vertical plate capacitors exhibiting enhanced capacitance and methods for fabricating density-conforming vertical plate capacitors exhibiting enhanced capacitance are provided. An embodiment of the density-conforming vertical plate capacitor comprises a first conductive interconnect and a second conductive interconnect. The second conductive interconnect overlies the first conductive interconnect and is substantially aligned with the first conductive interconnect. A via bar electrically couples the first conductive interconnect and the second conductive interconnect. The via bar has a width and a length that is larger than the width and contributes to the capacitance of the vertical plate capacitor.

Abstract: Devices and methods for their formation, including electronic devices containing capacitors, are described. In one embodiment, a device includes a substrate and a capacitor is formed on the substrate. The capacitor includes first and second electrodes and a capacitor dielectric between the first and second electrodes. At least one of the first and second electrodes includes a metal layer having carbon nanotubes coupled thereto. In one aspect of certain embodiments, the carbon nanotubes are at least partially coated with an electrically conductive material. In another aspect of certain embodiments, the substrate comprises an organic substrate and the capacitor dielectric comprises a polymer material. Other embodiments are described and claimed.

Abstract: One embodiment includes an apparatus that includes an implantable device housing, a capacitor disposed in the implantable device housing, the capacitor including a dielectric comprising CaCu3Ti4O12 and BaTiO3, the dielectric insulating an anode from a cathode and pulse control electronics disposed in the implantable device housing and connected to the capacitor.

Abstract: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Abstract: A multilayer capacitor includes a dielectric body 12 formed by stacking a plurality of dielectric layers 12a; a first internal conductor layer 21 led out straddling three side faces 12A, 12C and 12D of said dielectric body 12; a second internal conductor layer 22, stacked in the dielectric body 12 via dielectric layers 12a to the first internal conductor layer 21, led out straddling three side faces 12B, 12C and 12D; a first and a second terminal electrodes 31 and 32 formed on an outer face of said dielectric body 12, straddling the three side faces 12A, 12C and 12D, and 12B, and 12C and 12D, respectively. A first space pattern 41 is formed on the first lead portion at a position along with the first side face 12A, not connected with the first terminal electrode 31.

Abstract: A laminated ceramic electronic component includes a ceramic element and two external electrodes on both end surfaces of the ceramic element. The ceramic element includes a function part and lead parts thinner than the function part. Internal electrode layers are provided facing each other via a ceramic layer therebetween in the function part. The internal electrode layers are drawn out of the function part in the lead part. The external electrode includes an extended part and a curled part. The extended part is formed from the lead part through the function part on the main face. On the main face, the part of the extended part in the lead part is lower than the part of the function part. The curled part is formed from the end face of the ceramic element through the surface of the part of the extended part in the lead part on the main face.

Abstract: A method for forming an alpha-tantalum layer comprising disposing a nitrogen containing base layer on a semiconductor substrate, bombarding the nitrogen containing base layer with a bombarding element, thereby forming an alpha-tantalum seed layer, and sputtering a layer of tantalum on the alpha-tantalum seed layer, thereby forming a surface layer of substantially alpha-tantalum.

Abstract: Disclosed is multilayer ceramic capacitor. The multilayer ceramic capacitor includes a capacitive part including dielectric layers and first and second internal electrodes alternately laminated therein, wherein the dielectric layers include first ceramic particles having an average particle size of 0.1 ?m to 0.3 ?m, and one set of ends of the first internal electrodes and one set of ends of the second internal electrodes are exposed in a lamination direction of the dielectric layers, a protective layer formed on at least one of top and bottom surfaces of the capacitive part, including second ceramic particles and having a porosity of 2% to 4%, wherein an average particle size ratio of the second ceramic particles to the first ceramic particles ranges from 1.1 to 1.3; and first and second external electrodes electrically connected to the first and second internal electrodes exposed in the lamination direction of the dielectric layers.

Abstract: At least one of a plurality of first internal electrodes and a second internal electrode are arranged as opposed with at least one of the dielectric layers in between. Third and fourth internal electrodes are arranged as opposed with at least one of the dielectric layers in between. The first internal electrodes are electrically connected to a first external connecting conductor through lead conductors. The second, third, and fourth internal electrodes are electrically connected to second, third, and fourth terminal conductors, respectively, through lead conductors. At last one but not all of the first internal electrodes are electrically connected to the first terminal conductor through a lead conductor.

Abstract: A semiconductor device is made by depositing an encapsulant material between first and second plates of a chase mold to form a molded substrate. A first conductive layer is formed over the molded substrate. A resistive layer is formed over the first conductive layer. A first insulating layer is formed over the resistive layer. A second insulating layer is formed over the first insulating layer, resistive layer, first conductive layer, and molded substrate. A second conductive layer is formed over the first insulating layer, resistive layer, and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. The first conductive layer, resistive layer, first insulating layer, and second conductive layer constitute a MIM capacitor. The second conductive layer is wound to exhibit inductive properties.

Abstract: Composite carbon electrodes for use in, for example, Capacitive Deionization (CDI) of a fluid stream or, for example, an electric double layer capacitor (EDLC) are described. Methods of making the composite carbon electrodes are also described. The composite carbon electrode comprises an electrically conductive porous matrix comprising carbon; and an electric double layer capacitor, comprising an activated carbonized material, dispersed throughout the pore volume of the electrically conductive porous matrix.

Abstract: A metalized film capacitor includes a first dielectric film, a first metal thin-film electrode provided on a surface of the first dielectric film, a second dielectric film provided on the first metal thin-film electrode, and a second metal thin-film electrode provided on the second dielectric film, such that the second metal thin-film electrode faces the first metal thin-film electrode across the second dielectric film. The surface of the first dielectric film has a surface energy ranging from 25 mN/m to 40 mN/m. The metalized film capacitor exhibits high heat resistance and a preferable self-healing effect.

Abstract: An improved technique for power distribution for use by high speed integrated circuit devices. A mixture of high dielectric constant, Er and low Er materials are used in a dielectric layer sandwiched between the voltage and ground planes of a printed circuit board that is used to fixture one or more integrated circuit devices. The low Er material is used in an area contained by the location of the integrated circuit device and its corresponding decoupling capacitors located nearby. High Er material is used in areas between the regions of low Er material. The low Er material improves that speed at which current from an adjoining decoupling capacitor can propagate to a power pin of the integrated circuit device. The high Er material mitigates cross-coupling of noise between the low Er regions.

Abstract: Disclosed is a laminated ceramic capacitor that comprises a capacitor body (1) comprising alternately stacked dielectric layers (5) and internal electrode layers (7), and an external electrode (3) provided on the end face of the capacitor body (1) on which the internal electrode layer (7) is exposed. The dielectric layers (5, 5) disposed on both respective sides of the internal electrode layer (7) held between the dielectric layers (5, 5) are formed integrally with a dielectric bonding material (8) disposed so as to extend through a part of the internal electrode layer (7). The dielectric layer (5) has a crystal phase, composed mainly of barium titanate, as a main crystal phase, The crystal phase has a crystal structure based on a cubic system. The average grain diameter of crystal grains constituting the crystal phase is 0.05 to 0.2 pm. The dielectric layer (5) is formed of a dielectric ceramic containing yttrium, manganese, magnesium, and ytterbium.

Abstract: The method for forming the microelectronic device having at least one two or three dimensional capacitor includes creating, on a substrate, a plurality of components and a number of superimposed metal interconnection levels. An insulating layer is formed above a metal interconnection level, and a horizontal metal zone of a next metal interconnection level in which one or more of the insulating blocks created from this insulating layer are incorporated is formed therein. The zone is designed to form a lower structural part of the capacitor.

Abstract: The present invention relates to a semiconductor device, and more particularly to a method for forming a metal/insulator/metal (MIM). The method comprises the steps of: forming a metal wiring surrounded by the inter-metal dielectric film; forming a plurality of insulating film on the metal wiring in sequence; and forming a metal barrier film on the insulating film, whereby the insulating film functioning as a buffer film can mitigate the stress between the films.

Abstract: A capacitor element includes a pair of conductor layers, a plurality of generally tube-shaped dielectric substances, a first electrode outside the dielectric substances and second electrodes in the insides thereof, and insulation caps for insulating the first electrode from the conductor layer, wherein an electrode material is filled in gaps of a structure of an oxide base material resulting from anodic oxidation of a metal, and then, the structure is removed and replaced by a high permittivity material.

Abstract: A thin-film capacitor and a method for making the thin-film capacitor having a structure that can prevent vertical stress acting on outer connecting terminals, such as bumps, from concentrating on electrode layers, and capable of easily increasing the equivalent series resistance to a desired value. The thin-film capacitor includes a substrate, a capacitor unit disposed above the substrate and composed of at least one dielectric thin film and two electrode layers, a protective layer covering at least part of the capacitor unit, a lead conductor electrically connected to one of the electrode layers of the capacitor unit, and a bump disposed above the lead conductor. The lead conductor includes a connecting part disposed in an opening in the protective layer and electrically connected to one of the electrode layers of the capacitor unit, and a wiring part extending over the protective layer. The bump is disposed above the wiring part.

Abstract: A film capacitor is provided which has a smaller size and improved capacity while securing a sufficient withstand voltage. The film capacitor comprising a basic element 10 containing a plurality of dielectric layers and at least one vapor-deposited metal film layer 14a, 14b, where the plurality of dielectric layers consisting of a resin film layer 12 and at least one vapor-deposited polymer film layer 16a, and the at least one vapor-deposited polymer film layer 16a is formed on at least one of the resin film layer 12 and the at least one vapor-deposited metal film layer 14a, 14.

Abstract: A low capacitance density, high voltage MIM capacitor and the high density MIM capacitor and a method of manufacture are provided. The method includes depositing a plurality of plates and a plurality of dielectric layers interleaved with one another. The method further includes etching a portion of an uppermost plate of the plurality of plates while protecting other portions of the uppermost plate. The protected other portions of the uppermost plate forms a top plate of a first metal-insulator-metal (MIM) capacitor and the etching exposes a top plate of a second MIM capacitor.

Abstract: A high density capacitor and low density capacitor simultaneously formed on a single wafer and a method of manufacture is provided. The method includes depositing a bottom plate on a dielectric material; depositing a low-k dielectric on the bottom plate; depositing a high-k dielectric on the low-k dielectric and the bottom plate; depositing a top plate on the high-k dielectric; and etching a portion of the bottom plate and the high-k dielectric to form a first metal-insulator-metal (MIM) capacitor having a dielectric stack with a first thickness and a second MIM capacitor having a dielectric stack with a second thickness different than the first thickness.

Abstract: A multi-segment capacitor fabricated on a semiconductor substrate includes M×N capacitor segments arranged in a matrix of M rows and N columns. Each capacitor segment includes two groups of conductive fingers preferably made of metal wires. The metal wire fingers are distributed within multiple metal layers in such a manner that two neighboring parallel metal wire fingers within a particular metal layer are electrically insulated and connected to different terminals of the capacitor. Further, at least the longitudinal axes of the parallel metal wire fingers within two different metal layers are not parallel to each other within the same capacitor segment.

Abstract: A feedthrough capacitor having a pair of first terminal electrodes and a second terminal electrode is mounted on a mounting surface of a substrate. The substrate is an insulating substrate internally having first and second conductor portions isolated from each other, and has a plurality of first via holes, a plurality of second via holes, a plurality of first land electrodes, and a second land electrode. The first via holes and the second via holes, when viewed from the mounting surface side, are arranged in a matrix pattern and alternately arranged in a row direction and in a column direction. The feedthrough capacitor, when viewed from the mounting surface side, is located between a pair of said first via holes adjacent to each other in a direction intersecting with the row direction and also adjacent to each other in a direction intersecting with the column direction.

Abstract: Disclosed is a multilayer chip capacitor including a capacitor body including a plurality of dielectric layers that are stacked, first and second outer electrodes of opposite polarity disposed on an outer face of the capacitor body, first and second inner electrodes opposing each other inside the capacitor body to interpose the dielectric layer therebetween, the first inner electrode comprising an electrode plate forming capacitance and a lead extending from the electrode plate and connected to the first outer electrode, and the second inner electrode comprising an electrode plate forming capacitance and a lead extending from the electrode plate and connected to the second outer electrode. The leads are bent at least once and each have an overlap portion overlapping a lead of an adjacent inner electrode of opposite or like polarity when viewed along a stacked direction in which the plurality of dielectric layers are stacked.

Abstract: A semiconductor ceramic comprising a donor element within the range of 0.8 to 2.0 mol relative to 100 mol of Ti element contained as a solid solution with crystal grains, a first acceptor element in an amount less than the amount of the donor element is contained as a solid solution with the crystal grains, a second acceptor element within the range of 0.3 to 1.0 mol relative to 100 mol of a Ti element is present in crystal grain boundaries, and the average grain size of the crystal grains is 1.0 ?m or less. A monolithic semiconductor ceramic capacitor is obtained by using this semiconductor ceramic. To form the semiconductor ceramic, in a first firing treatment to conduct reduction firing, a cooling treatment is conducted while the oxygen partial pressure at the time of starting the cooling is set at 1.0×104 times or more the oxygen partial pressure in the firing process.

Abstract: Film capacitor assembly has a plurality of film capacitive layers for storing an electric charge. The plurality of film capacitive layers have a first metal contact and a second metal contact. A heat sink removes heat from the plurality of film capacitive layers. The heat sink is in thermal conductive communication with at least one of the first metal contact and the second metal contact. A dielectric material is configured to prevent a transmission of electric current through the heat sink from the plurality of film capacitor capacitive layers.

Abstract: A capacitor device with a capacitance is introduced. The capacitor device includes at least one capacitive element. The at least capacitive element comprises a pair of first conductive layers being opposed to each other, at least one first dielectric layer formed on a surface of at least one of the first conductive layers, and a second dielectric layer being sandwiched between the first conductive layers. The first dielectric layer has a first dielectric constant and the second dielectric layer has a second dielectric constant. The capacitance of the capacitor device depends on dielectric parameters of the first dielectric layer and the second dielectric layer. The dielectric parameters comprise the first dielectric constant and thickness of the at least one first dielectric layer and the second dielectric constant and thickness of the second dielectric layer.

Abstract: Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10?7 amps/cm2 at from ?1.1V to +1.1V.

Abstract: A film capacitor including a pair of electrodes having multiple pores is provided. The film capacitor includes a polymer film deposited upon each of the pair of electrodes to form a dielectric layer.

Abstract: The disclosed is a capacitor substrate structure to reduce the high leakage current and low insulation resistance issue of organic/inorganic hybrid materials with ultra-high dielectric constant. The insulation layer, disposed between two conductive layers, includes multi-layered dielectric layers. At least one of the dielectric layers has high dielectric constant, including high dielectric constant ceramic powder and conductive powder evenly dispersed in organic resin. The other dielectric layers can be organic resin, or further include high dielectric constant ceramic powder dispersed in the organic resin. The substrate has an insulation resistance of about 50 K? and leakage current of below 100 ?Amp under operational voltage.

Abstract: One or more embodiments relate to a semiconductor chip including a capacitor arrangement, the capacitor arrangement comprising: a first capacitor; and a second capacitor stacked above the first capacitor, the first capacitor and the second capacitor coupled in series between a first metallization level and a second metallization level adjacent the first metallization level.

Abstract: The present invention aims to provide an electronic component capable of reducing the occurrence of cracks at the joining portion with a board etc. A capacitor 1 (laminated ceramic capacitor) being one example of the electronic component of the present invention is provided with an element assembly 10 (ceramic) and a pair of external electrodes 20 formed on both side surfaces of the element assembly. In the element assembly 10, a dielectric layer 12 and an internal electrode 14 are laminated alternately. The external electrode 14 has such constitution that a first electrode layer connected with the internal electrode 14, a second electrode layer (electroconductive resin layer) including a hardened product of epoxy resin containing an epoxy compound having a molecular weight of 2000 or more and plural epoxy groups as the base compound, a third electrode layer composed of Ni and a fourth electrode layer composed of Sn are formed in this order from the element assembly side.

Abstract: Some embodiments include methods of forming capacitors. A metal oxide mixture may be formed over a first capacitor electrode. The metal oxide mixture may have a continuous concentration gradient of a second component relative to a first component. The continuous concentration gradient may correspond to a decreasing concentration of the second component as a distance from the first capacitor electrode increases. The first component may be selected from the group consisting of zirconium oxide, hafnium oxide and mixtures thereof; and the second component may be selected from the group consisting of niobium oxide, titanium oxide, strontium oxide and mixtures thereof. A second capacitor electrode may be formed over the first capacitor electrode. Some embodiments include capacitors that contain at least one metal oxide mixture having a continuous concentration gradient of the above-described second component relative to the above-described first component.

Abstract: A solder joint between a capacitive element and a ferrule of a filtered feedthrough assembly for an implantable medical device is formed from a solder pre-form mounted on a portion of an external surface of the capacitive element, which portion of the external surface may be overlaid with a layer including a noble metal. Another solder joint may be formed between the capacitive member and each feedthrough pin; and, for an assembly including a plurality of feedthrough pins, each of the other solder joints may be formed from a solder pre-form mounted onto the external surface of the capacitive element by inserting each pin through a corresponding ring of a plurality of rings connected together to form the solder pre-form.

Abstract: A capacitor device, an electronic circuit comprising a capacitor device, an electronic component, and a method of forming a capacitor device are described. In the capacitor device, a current-path region extends from one of two trench capacitor electrodes to a respective contact structure. The current-path region is obtainable by thinning the substrate from an original substrate thickness down to reduced substrate thickness either in a lateral substrate portion containing the capacitor region or over the complete lateral extension of the substrate before forming the first and second contact structures. The capacitor device exhibits a reduced impedance in the current-path region. This reduced impedance implies a low self-inductance and self-resistance that is caused by the current-path region.

Abstract: There is a provided a magnetic and dielectric composite electronic device, comprising: a first region with a plurality of magnetic material sheets being layered; a second region with a plurality of dielectric material sheets being layered; and a third region as a middle layer interposed between the first region and the second region, including a Zn—Ti based material to prevent diffusion of the materials during co-firing of the first region and the second region, and the first region, the second region and the third region are integrally formed in a single body. In accordance with the present invention, the low pass filter including the function of the varistor is realized to obtain the EMI function and the ESD control effect.

Abstract: A capacitor includes a lower electrode, a dielectric structure over the lower electrode, the dielectric structure including at least one crystallized zirconium oxide (ZrO2) layer and at least one amorphous aluminum oxide (Al2O3) layer, and an upper electrode formed over the dielectric structure. A method for fabricating a capacitor includes forming a lower electrode over a certain structure, forming a dielectric structure including at least one crystallized zirconium oxide (ZrO2) layer and at least one amorphous aluminum oxide (Al2O3) layer over the lower electrode, and forming an upper electrode over the dielectric structure.

Abstract: A method of manufacturing a multilayer capacitor comprises a first layer forming step, a first electrode forming step, a second layer forming step, a second electrode forming step, a separation step, an element forming step and a terminal forming step. In the first layer forming step, a first ceramic green layer is formed on a supporting body. In the first electrode forming step, a first electrode pattern is formed on the first ceramic green layer. In the second layer forming step, a second ceramic green layer is formed laminated on the first ceramic green layer. In the second electrode forming step, a second electrode pattern is formed at the second ceramic green layer. In the separation step, the support body is separated from the laminated body. In the element forming step, elements are formed by laminating a plurality of the laminated bodies.

Abstract: A metal capacitor in which an electric conductivity is significantly improved by applying a metal material for an electrolyte and a manufacturing method thereof is provided.

Abstract: A metal capacitor in which an electric conductivity is significantly improved by applying a metal material for an electrolyte and a manufacturing method thereof is provided.

Abstract: A film capacitor including a first electrode is provided. The film capacitor also includes a first dielectric layer having a first dielectric constant disposed upon a first electrode, a second dielectric layer having a second dielectric constant disposed upon the first dielectric layer, wherein the second dielectric constant is at least fifty percent greater than the first dielectric constant, and a metalized film disposed upon the second dielectric layer. It further includes a second electrode disposed upon the metalized film.

Abstract: A dielectric device has a first conductor and a dielectric disposed thereon. An intermediate region is formed between the first conductor and dielectric. In the intermediate region, an additive different from the first conductor and dielectric and the dielectric are mixed with each other. The additive contains at least one element of Si, Al, P, Mg, Mn, Y, V, Mo, Co, Nb, Fe, and Cr.

Abstract: A thin-film device comprises a base electrode made of a metal, a first dielectric layer, a first inner electrode, a second dielectric layer, a second inner electrode, and a third dielectric layer. Letting T1 be the thickness of the lowermost first dielectric layer in contact with the base electrode in the plurality of dielectric layers, and Tmin be the thickness of the thinnest dielectric layer in the plurality of dielectric layers excluding the first dielectric layer, T1>Tmin. Making the first dielectric layer thicker than the thinnest, dielectric layer in the other dielectric layers can increase the distance between a metal part projecting from a metal surface because of the surface roughness of the base electrode and the inner electrode mounted on the lowermost dielectric layer, thereby reducing leakage currents.

Abstract: A thin film capacitor includes a metal foil, dielectric layers and internal electrode layers alternately disposed on the metal foil, and a top electrode layer on the topmost layer among the two or more dielectric layers. These layers have peripheries that define an outer profile flaring toward the metal foil as viewed from the stacking direction of the thin film capacitor, and at least one dielectric layer of two or more dielectric layers satisfies a relationship B>A>0 wherein A is a gap of the periphery of the internal electrode layer directly below the dielectric layer protruding from the periphery of the dielectric layer, and B is a gap of the periphery of the dielectric layer protruding from the periphery of the internal electrode layer or the top electrode layer directly above the dielectric layer. The thin film capacitor has a structure free from short-circuiting and reducing debris of broken dielectric material.

Abstract: A capacitor device with a capacitance is introduced. The capacitor device includes at least one capacitive element. The at least capacitive element comprises a pair of first conductive layers being opposed to each other, at least one first dielectric layer formed on a surface of at least one of the first conductive layers, and a second dielectric layer being sandwiched between the first conductive layers. The first dielectric layer has a first dielectric constant and the second dielectric layer has a second dielectric constant. The capacitance of the capacitor device depends on dielectric parameters of the first dielectric layer and the second dielectric layer. The dielectric parameters comprise the first dielectric constant and thickness of the at least one first dielectric layer and the second dielectric constant and thickness of the second dielectric layer.