Abstract: The present invention provides an anisotropic electrically conductive film with a structure, in which electrically conductive particles are disposed at lattice points of a planar lattice pattern in an electrically insulating adhesive base layer. A proportion of the lattice points, at which no electrically conductive particle is disposed, with respect to all the lattice points of the planar lattice pattern assumed as a reference region, is less than 20%. A proportion of the lattice points, at which plural electrically conductive particles are disposed in an aggregated state, with respect to all the lattice points of the planar lattice pattern, is not greater than 15%. A sum of omission of the electrically conductive particle and an aggregation of the electrically conductive particles is less than 25%.

Abstract: A power module of the invention includes a power semiconductor element mounted on a circuit board, and an adapter connected to a front-surface main electrode of the element, wherein the adapter includes a main-electrode wiring member which is connected to the front-surface main electrode of the element; and wherein the main-electrode wiring member includes: an element connection portion connected to the front-surface main electrode of the element; a board connection portion which is placed outside the element connection portion and connected to the circuit board; and a connector connection portion which is placed outside the element connection portion and connected to an external electrode through a connector.

Abstract: The present disclosure relates to systems and methods using thermal vias to increase the current-carrying capacity of conductive traces on a multilayered printed circuit board (PCB). In various embodiments, parameters associated with vias may be selected to control various electrical and thermal properties of the conductive trace. Such parameters include the via diameter, a plating thickness, a number of vias, a placement of the vias, an amount of conductive material to be added or removed from the conductive trace, a change in the resistance of the conductive trace, a change in a fusing measurement of the conductive trace, and the like.

Abstract: A microphone assembly including a main board and a microphone. The microphone includes a capacitor or a MEMS chip, a case accommodating the capacitor or the MEMS chip, and a microphone board electrically connected to the capacitor or the MEMS chip. The microphone board has a larger outer dimension than the case and includes a fixing portion and a connecting portion. The case is fixed onto the fixing portion. The connecting portion is a portion of the microphone board, the portion being located outside the case and electrically and mechanically connected to the main board.

Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

Abstract: To prevent degradation of electrical characteristics caused by a resin filled between electrodes in an ultraviolet light-emitting operation, the present invention provides a base 10 that comprises an insulating base material 11 and two or more metal films 12 and 13 that are formed on one side of the insulating base material 11 and electrically separated from each other. The two or more metal films are formed to include an upper surface and a side wall surface that are covered by gold or a platinum group metal, to be capable of mounting thereon one or more nitride semiconductor light-emitting elements and the like, and to have, as a whole, a predetermined planar view shape including two or more electrode pads.

Abstract: A printed circuit board assembly (PCBA) for downhole applications has a printed circuit board (PCB) and a plurality of electronic components installed on the PCB. The PCB comprises a polyimide substrate, a lead-free surface finish, a plurality of traces, a plurality of surface mount pads, and a plurality of VIAs. The ratio between the width of one of the plurality of surface mount pads to the width of the trace connected thereto is 2 or less.

Abstract: An electrical interconnect for an electronic package. The electrical interconnect includes a first dielectric layer; a second dielectric layer; a signal conductor positioned between the first dielectric layer and the second dielectric layer; and a conductive reference layer mounted on the first dielectric layer, and wherein the conductive reference layer does not cover the signal conductor. The conductive reference layer may be a first conductive reference layer and the electrical interconnect further comprises a second conductive reference layer mounted on the second dielectric layer. The second conductive reference layer does not cover the signal conductor. In addition, the signal conductor may be a first signal conductor and the electrical interconnect may further include a second signal conductor between the first dielectric layer and the second dielectric layer. The first and second signal conductors may form a differential pair of conductors.

Abstract: Provided are a power inductor including a body, a base disposed in the body, a coil disposed on the base, a first external electrode connected to the coil, the first external electrode being disposed on a side surface of the body, and a second external electrode connected to the first external electrode, the second external electrode being disposed on a bottom surface of the body and a method for manufacturing the same.

Abstract: The present invention provides an anisotropic electrically conductive film with a structure, in which electrically conductive particles are disposed at lattice points of a planar lattice pattern in an electrically insulating adhesive base layer. A proportion of the lattice points, at which no electrically conductive particle is disposed, with respect to all the lattice points of the planar lattice pattern assumed as a reference region, is less than 20%. A proportion of the lattice points, at which plural electrically conductive particles are disposed in an aggregated state, with respect to all the lattice points of the planar lattice pattern, is not greater than 15%. A sum of omission of the electrically conductive particle and an aggregation of the electrically conductive particles is less than 25%.

Abstract: Provided is an electronic control device that is easily assembled and with which it is possible to reduce the effects of vibration and external force applied from a connector. Electronic components are installed on a substrate. A base covers a surface of the substrate. A cover covers a surface of the substrate. A first connector, which is installed on the surface, connects to a connector fixed to an on-board transmission. A second connector, which is installed on the surface, connects to a connector of a harness. First vibration-suppressing parts, which are provided to the inside surface of the base facing the end surface of the first connector on the surface side, suppress the vibration of the first connector.

Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.

Abstract: Embodiments of the present disclosure relate to separating an integrated circuit (IC) structure from an adjacent chip. An IC structure according to embodiments of the disclosure may include: a semiconductor region including an interconnect pad positioned thereon, the interconnect pad electrically connected to a solder bump; and an ohmic heating wire positioned within the semiconductor region and in thermal communication with the interconnect pad, wherein the ohmic heating wire is configured to be heated above a melting temperature of the solder bump.

Abstract: A package substrate includes a substrate, a first connection terminal mounted over the substrate, the first connection terminal including a first land and a second land on the substrate, a first solder resist surrounding the first land and the second land, and a first solder ball formed straddling the first land and the second land; and a second connection terminal which is mounted over the substrate and disposed adjacent to the first connection terminal, the second connection terminal including a third land and a fourth land on the substrate, a second solder resist surrounding the third land and the fourth land, and a second solder ball formed straddling the third land and the fourth land.

Abstract: An electronic component unit of a wire harness includes a substrate on which an electronic component is mounted, a connector electrically connected to the substrate, and a connector fixing structure. The connector fixing structure includes a pair of notches that are provided facing each other on ends of the substrate in a long-side direction and that penetrate through the substrate in a plate thickness direction, a pair of press fitting plates that are provided on the connector and that are press-fitted into the respective notches, and a deformation acceptable space that is provided adjacent to each of both sides of the press fitting plates press-fitted into the respective notches in the long-side direction.

Abstract: An electronic apparatus is provided. The electronic apparatus includes an integrated fan-out package, a dielectric housing, and a plurality of conductive patterns. The dielectric housing is covering the integrated fan-out package, wherein a gap or a first dielectric layer is in between the dielectric housing and the integrated fan-out package. The plurality of conductive patterns is located on a surface of the dielectric housing, wherein the plurality of conductive patterns is located in between the dielectric housing and the integrated fan-out package.

Abstract: An electrical connector includes an insulating body, which has at least two body units. Each two body unit accommodates and is fixed with multiple terminals, and the at least two body units are spliced to each other. Each body unit has at least two edge portions, and the insulating body is provided with at least four fixing portions such that each of the edge portions is provided with at least one fixing portions. At least four metal members are correspondingly and fixedly provided on the at least four fixing portions respectively. At least two metal sheets are provided outside the at least two body units. Each metal sheet is soldered and fixed to at least one metal member provided on each body unit. By soldering and fixing the metal members and the metal sheets together, the overall structure of the electrical connector is firmer, and flatness is higher.

Abstract: An integrated circuit (IC) chip card includes a card body and an integrated IC chip module located in a recess provided by the card body on one side thereof. The IC chip module includes a substrate having outward-facing and inward-facing surfaces, and a first plurality of contact pads supportably interconnected to the outward-facing surface of the substrate for contact engagement with at least one appendage of a user. The IC chip module further includes a first IC chip supportably interconnected to the inward-facing surface of the substrate and electrically interconnected to the first plurality of contact pads for processing a biometric signal received therefrom.

Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.

Abstract: An electronic package is provided, which includes: a substrate, an electronic element disposed on the substrate, and an antenna structure disposed on the substrate. The antenna structure has a base portion and at least a support portion, the base portion including a plurality of openings and a frame separating the openings from one another, and the support portion supporting the base portion over the substrate. Therefore, no additional area is required to be defined on a surface of the substrate, and the miniaturization requirement of the electronic package is thus met.

Abstract: Devices and methods for routing cables through a printed circuit board (PCB) include an enclosure having at least one cable guide and a cable duct. A PCB is mounted in the enclosure, such that the cable duct penetrates the PCB through a hole in the PCB. At least one additional component is mounted in the enclosure and connected to at least one cable that is attached to the at least one cable guide and the cable duct. The at least one cable enters the duct on a first side of the PCB and exits the duct on a second side of the PCB.

Abstract: An assembly comprises: at least one element that is capable of transmitting heat; at least one electrically insulating substrate comprising at least one film of a polymer that is a good thermal conductor and electrical insulator; at least one sintered metal joint that is in contact with the polymer film; a main radiator; the radiator being in direct contact, or in contact via a sintered joint, with the substrate.

Abstract: A semiconductor device includes: a processor having a heat sink mounted thereon; and an optical module having a heat transfer interposer, wherein the heat sink and the optical module are coupled to each other via the heat transfer interposer. And a semiconductor device includes: a semiconductor chip mounted on a substrate; a lead that covers the semiconductor chip; a heat sink installed on the lead; and an optical module coupled to the heat sink via a heat transfer interposer.

Abstract: A touch panel having a cover plate, a sensor electrode layer, an insulating layer and a jumper layer is provided. The sensor electrode layer has first axis electrodes, second axis electrodes, bonding pads and first periphery traces. Each first axis electrode has first electrode blocks that are electrically connected to each other. Each second axis electrode has second electrode blocks that are electrically isolated from each other. The bonding pads are disposed on the periphery region of the cover plate. The first periphery traces are electrically connected to the bonding pads and the first axis electrodes or the second axis electrodes respectively. The insulating layer has first via holes and second via holes. The jumper layer has jumper traces and second periphery traces, wherein the second periphery traces are electrically connected to the first axis electrodes or the second axis electrodes through the first via holes.

Abstract: An assembly of a cable connection apparatus and an electrical connector, includes a mating plug having an insulating body and multiple terminals, a circuit board having a notch depressed from an edge at a side of the circuit board toward a center direction of the circuit board and a metal conductor disposed in the notch or at an edge of the notch, and a cable having at least one conducting wire. The terminals are conducted to the circuit board. The conducting wire is inserted into the corresponding notch along a depression direction of the notch, and conducted to the metal conductor, thereby reducing the height of a soldering end of the conducting wire protruding from a surface of the circuit board. Thus, a metal casing outside the circuit board may wrap the circuit board without having a protruding portion for reserving the soldering end.

Abstract: A touch panel having a cover plate, a sensor electrode layer, an insulating layer and a jumper layer is provided. The sensor electrode layer has first axis electrodes, second axis electrodes, bonding pads and first periphery traces. Each first axis electrode has first electrode blocks that are electrically connected to each other. Each second axis electrode has second electrode blocks that are electrically isolated from each other. The bonding pads are disposed on the periphery region of the cover plate. The first periphery traces are electrically connected to the bonding pads and the first axis electrodes or the second axis electrodes respectively. The insulating layer has first via holes and second via holes. The jumper layer has jumper traces and second periphery traces, wherein the second periphery traces are electrically connected to the first axis electrodes or the second axis electrodes through the first via holes.

Abstract: An electronic device connection unit includes a substrate and a plurality of signal pads on the substrate configured to send signals from an electronic device to a driving printed circuit board (PCB). One or more active ground pads on the substrate are configured to connect at least the driving PCB to a reference voltage of the electronic device. One or more dummy ground pads on the substrate are configured to connect to the reference voltage of the electronic device without extending onto the driving PCB. One or more connectors are connected to the one or more dummy ground pads, where each of the one or more connectors is configured to electrically couple at least a subset of the one or more dummy ground pads to the one or more active ground pads.

Abstract: An ultra-wideband assembly is provided. The assembly includes a non-conductive tapered core having a conductive wire wound on an outer surface of the non-conductive tapered core, a low-frequency inductor coupled to the non-conductive tapered core via the distal end of the conductive wire and configured to allow mounting of the non-conductive tapered core at an angle with respect to the circuit board. The low frequency inductor is being disposed on a dielectric board configured to be coupled to the circuit board. The assembly includes an ultra-wideband capacitor coupled to the non-conductive tapered core via the proximate end of the conductive wire, the ultra-wideband capacitor being also coupled to the transmission line on the dielectric board.

Abstract: An embodiment package on package (PoP) device includes a molding compound having a metal via embedded therein, a passivation layer disposed over the molding compound, the passivation layer including a passivation layer recess vertically aligned with the metal via, and a redistribution layer bond pad capping the metal via, a portion of the redistribution layer bond pad within the passivation layer recess projecting above a top surface of the molding compound.

Abstract: A method of a semiconductor package includes providing a substrate having a conductive trace coated with an organic solderability preservative (OSP) layer, removing the OSP layer from the conductive trace, and then coupling a chip to the substrate to form a semiconductor package.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.

Abstract: An integrated interposer may include a substrate and a resistive-type non-volatile memory (NVM) array(s). The integrated interposer may also include a contact layer on a first surface of the substrate. The contact layer may include interconnections configured to couple the resistive-type NVM array(s) to a die(s). The resistive-type NVM array(s) may be partially embedded within the contact layer of the integrated interposer.

Abstract: A fan-out wafer level package structure may include a multilayer redistribution layer (RDL). The multilayer RDL may be configured to couple with terminals of an embedded capacitor. The multilayer RDL may include sections with fewer layers than other sections of the multilayer RDL according to a selected equivalent series resistance (ESR) control pattern.

Abstract: Power may be supplied to an electronic module according to various techniques. In one general implementation, for example, a system for supplying power to an electronic module may include a printed circuit board, the electronic module, and a conductive foil. The board may include a number of contact locations on a first side, with at least one of the contact locations electrically coupled to a via to a second side of the board. The electronic module may be electrically coupled to the contact locations on the first side of the board and receive electrical power through the at least one contact location electrically coupled to a via. The foil may be adapted to convey electrical power for the electronic module and electrically coupled on the second side of circuit board to at least the via electrically coupled to a contact location that receives electrical power for the electronic module.

Abstract: An electrical connector is to be connected to a mating connector. The electrical connector includes a circuit board member formed of an insulation plate member; and a holding member for holding the circuit board member. The circuit board member includes a connecting portion to be connected with a mating connector of the mating connector. The connecting portion includes a pair of conductive band portions and a first insulation region disposed between the conductive band portions.

Abstract: A light emitting device package is provided. The light emitting device package comprises a package body comprising a first cavity, and a second cavity connected to the first cavity; a first lead electrode, at least a portion of which is disposed within the second cavity; a second lead electrode, at least a portion of which is disposed within the first cavity; a light emitting device disposed within the second cavity; a first wire disposed within the second cavity, the first wire electrically connecting the light emitting device to the first lead electrode; and a second wire electrically connecting the light emitting device to the second lead electrode.

Abstract: A system for assembling electronic devices includes at least one coating element for applying a moisture-resistant coating to surfaces of a device under assembly, or an electronic device under assembly. As components and one or more moisture-resistant coatings are added to the electronic device under assembly to form a finished electronic device, at least one surface on which the coating resides and, thus, at least a portion of the coating itself, is located internally within the finished electronic device. Methods for assembling electronic devices that include internally confined moisture-resistant coatings are also disclosed.

Abstract: A printed wiring board with a component connection pad, such as a solder pad, providing thermal stress compensation for a surface mount circuit component and method for making such a pad. The component connection pad includes opposed groups of multiple conductive fingers that are mutually connected at their far ends and separated at their near ends where they have surfaces for mounting a single surface mount circuit component.

Abstract: Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer.

Abstract: A printed circuit board according to an embodiment of the present invention includes an insulating layer, a pad formed on the insulating layer and exposed through an opening section of a solder resist, a bump formed by filling an opening portion of the solder resist from top of the pad and having an narrow width than the opening of the solder resist.

Abstract: Provided is a wiring board including: an insulating board having a mounting portion configured such that a semiconductor element is mounted on an upper surface thereof; a semiconductor element connection pad formed on the mounting portion; a conductor pillar formed on the semiconductor element connection pad; and a solder resist layer adhered on the insulating board. The solder resist layer has a first region with a thickness such that the semiconductor element connection pad and a lower end portion of the conductor pillar are embedded while an upper end portion of the conductor pillar protrudes, and a second region having a thickness larger than that of the first region and surrounding the first region.

Abstract: A circuit board for an image processing chip of a vision system of a vehicle is configured for a surface mount device to be attached thereto and includes at least one mounting location having a plurality of solder pads established thereat. The pads are arranged in a manner that enhances soldering of the device or component to the pad and circuit board. The pads may be arranged similarly in respective portions of the mounting location, such that the pads of one portion of the mounting location may be generally parallel to one another and may be generally orthogonal to the pads of another portion of the mounting location. Optionally, the pads may be generally tear-drop shaped, and the tear-drop shaped pads may be arranged so as to point generally towards or generally away from a center area of the mounting location of the circuit board.

Abstract: A light emitting device package is provided. The light emitting device package comprises a package body comprising a first cavity, and a second cavity connected to the first cavity; a first lead electrode, at least a portion of which is disposed within the second cavity; a second lead electrode, at least a portion of which is disposed within the first cavity; a light emitting device disposed within the second cavity; a first wire disposed within the second cavity, the first wire electrically connecting the light emitting device to the first lead electrode; and a second wire electrically connecting the light emitting device to the second lead electrode.

Abstract: A chip detecting system is disclosed. The system includes a ball grid array (BGA) chip and a circuit board, the BGA chip includes at least two functional pins being located at a corner of the BGA chip, the at least two functional pins are electrically connected to each other, the circuit board is provided with at least two solder pads and at least two testing pads, the at least two functional pins are electrically connected to the at least two solder pads by using solder balls separately, the solder pads are electrically connected to the testing pads separately, and the at least two testing pads are configured to electrically connect to a detector, so as to detect whether a crack exists between the at least two functional pins and the circuit board.

Abstract: A display device and a circuit board for it are provided. The circuit board includes a bare copper region which is positioned corresponding to a chip of a driver IC of the display device; the bare copper region resists the chip and is configured to conduct away the heat generated from the chip. The display device comprises a circuit board, a driver IC electrically connected to the circuit board and fixed on the circuit board, and a display screen electrically connected to the driver IC. The following advantageous effects can be achieved: the circuit board has a bare copper region resisting the chip of the driver IC, which can effectively conduct away the heat generated from the driver IC to make the heat-dissipating effect of the display device better, and thereby extending the lifetime of the display device.

Abstract: A method of applying inductive heating to join an integrated circuit chip to an electrical substrate using solder bumps including applying a magnetic field to a magnetic liner in thermal contact with a solder bump on the integrated circuit chip. The magnetic field causes Joule heating in the magnetic liner sufficient to melt the solder bump, which has a lower portion embedded in a first dielectric layer and an upper portion at least partially embedded in a second dielectric layer. The lower portion is in electrical contact with a conductive pad, the first dielectric layer is above the conductive pad and the second dielectric layer is on top of the first dielectric layer. The duration of application of the magnetic field is controlled to achieve a joining temperature that is approximately halfway between the storage and operating temperatures of the integrated circuit chip.

Abstract: A method of assembling a multi-chip electronic device into a thin electronic package entails inverting a flip-chip die arrangement over a hollow substrate, stacking additional dies on the hollow substrate to form a multi-chip electronic device, and encapsulating the multi-chip electronic device. Containment of the encapsulant can be achieved by joining split substrate portions, or by reinforcing a hollow unitary substrate, using a removable adhesive film. Use of the removable adhesive film facilitates surrounding the multi-chip electronic device with the encapsulant. The adhesive film can also prevent encapsulant from creeping around the substrate to an underside of the substrate that supports solder ball pads for subsequent attachment to a ball grid array (BGA) or a land grid array (LGA).

Abstract: A wiring board includes a first via hole in a first insulating layer to expose a first wiring layer. A first via in the first via hole includes an end surface. A second wiring layer is arranged on the first insulating layer and the end surface of the first via. A second insulating layer covers the second wiring layer. A second via hole in the second insulating layer exposes the second wiring layer. A second via in the second via hole is arranged above the first via through the second wiring layer. The outer surface of the first insulating layer is lower in surface roughness than an inner surface of the first via hole.

Abstract: A microelectronic assembly can include a first package comprising a processor and a second package electrically connected to the first package. The second package can include two or more microelectronic elements each having memory storage array function and contacts at a respective element face, upper and lower opposite package faces, upper and lower terminals at the respective upper and lower package faces, and electrically conductive structure extending through the second package. At least portions of edges of respective microelectronic elements of the two or more microelectronic elements can be spaced apart from one another, so as to define a central region between the edges that does not overlie any of the element faces of the microelectronic elements of the second package. The electrically conductive structure can be aligned with the central region and can electrically connect the lower terminals with at least one of: the upper terminals or the contacts.

Abstract: An improvement is achieved in the performance of an electronic device. A first semiconductor device and a second semiconductor device are mounted over the upper surface of a wiring board such that, e.g., in plan view, the orientation of the second semiconductor device intersects the orientation of the first semiconductor device. That is, the first semiconductor device is mounted over the upper surface of the wiring board such that a first emitter terminal and a first signal terminal are arranged along an x-direction in which the pair of shorter sides of the wiring board extend. On the other hand, the second semiconductor device is mounted over the upper surface of the wiring board such that a second emitter terminal and a second signal terminal are arranged along a y-direction in which the pair of longer sides of the wiring board extend.