Abstract: An object of the invention is to provide a semiconductor device and an adjusting method for a semiconductor device wherein power source noises and noises radiated as radio waves can be reduced and power source noises inside the semiconductor device can be cut. The open stub OS1 is formed in the upper wiring layer of the semiconductor device 1. The stub length L1 is set to a length of ¼ of the wavelength of the known frequency containing peak components of noises. The noise receiving part AT1 is disposed adjacent to the open stub OS1. The open stub OS1 is connected to the power source wiring 4 by an interlayer wiring 6. The noise receiving part AT1 is biased to a ground potential. The basic wave component and odd-number harmonic waves of noises that are generated from the PLL circuit 11 and propagate (the arrow Y1 of FIG. 2) in the power source wiring 4 are reflected (arrow Y2 of FIG. 2) by the open stub OS1 so as to return to the PLL circuit 11, and do not reach the filter circuit 12.

Abstract: A plurality of wiring patterns are formed so as to extend in parallel with each other. A plurality of test terminals are formed in a substantially rectangular shape such that respective widths thereof increase toward respective one sides from respective ends of the plurality of wiring patterns. The plurality of test terminals in each group are arranged so as to be aligned along a length direction of the wiring patterns. The wiring patterns are formed so as to be longer in the order, and the test terminals are further away from a mounting region in the order. An interval (width of a plating resist) between the test terminals in each group and the wiring patterns in the other group adjacent thereto is set to decrease in the order.

Abstract: A power module package structure is disclosed. The control circuits are fabricated on a circuit plate, instead of fabricating them directly on a main substrate. The fabrication cost is reduced because the size of the substrate is shrunk. Furthermore, the power chips are placed on a material with high thermal conductivity. The heat produced from the power chips can be transmitted quickly. Thus, the reliability of the power module package can be improved.

Abstract: Conductive patterns and methods of using and printing such conductive patterns are disclosed. In certain examples, the conductive patterns may be produced by disposing a conductive material between supports on a substrate. The supports may be removed to provide conductive patterns having a desired length and/or geometry.

Abstract: A circuit board containing a metal-insulator composite member including an insulator substrate and a metal layer having a pattern, the composite member having an area where the spacing between a lower part of adjacent elements of the pattern on the metal layer which is in contact with the insulator is not greater than the thickness of the metal layer. Also a power module containing such circuit board.

Abstract: Two coil forming elements (12, 14) formed of conductor layers and a contact means (19), which is formed in an interlayer dielectric film (13) interposed between the conductor layers and brings the upper and lower coil forming elements into contact with each other through a via hole form a stacked coil (10). One end of the stacked coil is connected to an upper grounding layer (27) of a strip line (20), and the other end of the stacked coil is connected to a strip conductor (23) of the strip line. The number of turns of the stacked coil is larger than 1. A magnetic flux penetrating through the stacked coil increases to be able to induce a relatively large electromotive force. Thus, a high spatial resolution can be obtained easily.

Abstract: A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.

Abstract: A printed wiring board includes a plurality of conductor plates that includes at least one conductor plate that is used as a lead for electrical connection with an external circuit, the conductor plates being separated spatially from one another; an insulating layer formed on or across the conductor plates or both on and across the conductor plates; and a plurality of wiring patterns formed on the insulating layer. At least one of the conductor plates is electrically connected with at least one of the wiring patterns through a via-hole.

Abstract: A mounting structure for electronic components is provided with a circuit board that has a step portion formed at one end portion thereof. The step portion is sandwiched by a lead of the electronic component so as to secure the lead to the step portion. The step portion is formed by perforating a region on one surface of the circuit board, and then peeling a part of the circuit board corresponding to the perforated region so as to reduce the thickness of the circuit board at the region.

Abstract: A printed board suitable for having a LSI surface-mounted thereto and improves high-speed transfer characteristic while maintaining the circumference of a pad formed on the printed board. The pad is a connector pad consisting of a conductor pattern, and the area of the conductor pattern forming the pad is smaller than an area determined based on the circumference of the conductor pattern that forms the pad.

Abstract: A method according to the present invention for producing a semiconductor-chip-mounting circuit 1 includes mainly three steps. In a first step, contacts 2 each in the form of a conical helix are formed by solder-plating the surface of connecting terminals 12 on a mounting circuit 10. In a second step, a continuity test is performed by pressing bumps 21 against the contacts 2. In a final third step, the contacts 2 pressed are melted to connect the connecting terminals 12 to the bumps 21. That is, the semiconductor chip 20 is connected to the mounting circuit 10 while maintaining a state in which they pass the continuity test, thereby significantly reducing the occurrence of defective continuity in the semiconductor-chip-mounting circuit 1.

Abstract: The present invention describes a pre-fabricated chip mount and a method for making the pre-fabricated mount. The mount includes a mount body and a protective ring attached to the body by a plurality of tabs. The mount also includes a plurality of inner leads in electrical communication with the wires of at least one leadframe and a receiving area for an integrated circuit chip. The present invention also describes chips mounted on the pre-fabricated mount and methods for mounting, wire-bonding and encapsulating the chip in the mount. The mounts of the present invention can also be adapted to accommodate multiple chips and multi-level bonding schemes to the chips.

Abstract: Provided is an electronic components assembly capable of effectively dealing with unwanted charge accumulated in a capacitor even when general-purpose components are used. An assembly 10 includes an electrolytic capacitor 1, a coil lead 4, and a circuit mounting board 5. The electrolytic capacitor 1 includes a main body 1a, an anode lead 2, and a cathode lead 3. The coil lead 4 is wrapped around the main body 1a. The circuit mounting board 5 has the electrolytic capacitor 1 and the coil lead 4 mounted thereon. The coil lead 4 is connected to a ground of the circuit mounting board 5.

Abstract: Provided is an electronic circuit module using a board having no cavity and a method for efficiently fabricating it. Electronic components are mounted on the front face of a module board 1, and an LSI chip 5 is die-bonded on the bottom face thereof in a bare-chip state with gold wires 8. Around the LSI chip 5, metal blocks 9 made of copper are mounted by soldering. The LSI chip 5, the gold wires 8, and the metal blocks 9 provided on the bottom face of the module board 1 are sealed with resin 10 with a motherboard-facing face 9a of each metal block 9 and a face 18 thereof flush with the corresponding side face of the module board 1 exposed from the resin 10. These exposed portions serve as electrode terminals when the module 11 is soldered to a motherboard. The module board 1 is obtained by cutting a sheet circuit board into individual unit module boards 1.

Abstract: A method of forming a plurality of elastic probes in a row is disclosed. Firstly, a substrate is provided, then, a shaping layer is formed on the substrate so as to offer two flat surfaces in parallel. A photoresist layer is formed on the substrate and on the shaping layer. Then, the photoresist layer is patterned to form a plurality of slots crossing an interface between the two flat surfaces where a plurality of elastic probes are formed in the slots. In one embodiment, the interface is an edge slope of the shaping layer so that each of the elastic probes has at least an elastic bending portion. During chip probing, the shifting direction of the elastic probes due to overdrives is perpendicular to the arranging direction of the bonding pads so that the elastic probes are suitable for probing chips with high-density and fine-pitch bonding pads.

Abstract: A method and apparatus to eliminate conductive contamination reliability problems for assembled substrates, such as electrical arcing in power semiconductor leads. One embodiment of the invention involves a method for assembling an electrical component having leads on a substrate having conductive contacts, wherein an elastomer part encapsulates the leads of the electrical component. A second embodiment of the invention involves assembling an electrical component having leads to a substrate having conductive contacts, wherein an elastomer shape cut by a punch die encapsulates the leads of the electrical component. A third embodiment of the invention involves an assembled substrate including an electrical component having leads, and an elastomer surrounding the leads to encapsulate the leads.

Abstract: A multiplicity of nanotubes are applied to at least one external chip metal contact of an electronic chip in order to make contact between the electronic chip and a further electronic chip.

Abstract: In a laser beam printer, an elastic conductive member is disposed between a rotating axis of a transfer roller and a land portion of a power supply circuit board and the transfer roller is electrically connected to the power supply circuit board through the elastic conductive member. A front end portion of the elastic conductive member is pressed onto the land portion by its elastic force to come into contact with a solder pad formed on the surface of the land portion for electrical connection. A resist film is partially formed on the surface of the land portion and the solder pad is formed on the region on the land portion that is not covered with the resist film. Thus, a large contact area between the front end portion of the elastic conductive member and the solder pad is ensured so as to address a high voltage applied to the transfer roller. As a result, the transfer roller, etc. can be electrically connected to the power supply circuit board with certainty without increasing the number of components.

Abstract: A circuit substrate includes a base and a plurality of conductive traces. The conductive traces are disposed on the base and on the same layer. The conductive traces include at least one first conductive trace. Wherein, the base has a cut region. The end of the first conductive trace is connected to the end portion of the cut region. The included angle between the rim of the end portion of the cut region and the first conductive trace is 75° to 105°.

Abstract: A substrate is made of resin or a composite material. Pins with Au plating on their surface are soldered, with a soldering material made of Sn and Sb, to a substrate body having a first main surface, and formed into substantially a rectangular shape to project over the first main surface of the substrate body. Wettability of the soldering material for securing the pins and the substrate body is relatively low as compared with that of a Pb—Sn soldering material. Therefore, the height of upward movement of the soldering material along the pin can be reduced. Thus, the pins can be deeply inserted into socket so that the gap between the first main surface of the substrate body and the upper surface of the socket is reduced. As a result, the overall height realized the substrate made of resin has been joined to the socket can be reduced.

Abstract: A circuit board including a signal transmission channel includes a dielectric substrate and a signal transmission channel which may be formed on the dielectric substrate. The signal transmission channel may include a conductor, a lossy dielectric material which may longitudinally encapsulate the conductor and a conductive material which may longitudinally encapsulate the lossy dielectric.

Abstract: An electronic package has a circuit board including a substrate electrical circuitry including circuit traces and first and second contacts for connecting to surface mount device(s). The first and second contacts each have multiple components including first and second pads. The first pad is separate from the second pad to allow for low cost and easy testing of the electrical circuit.

Abstract: A quad flat no-lead (QFN) grid array semiconductor package and method for making the same are provided. The package includes a semiconductor die and a lead frame having a plurality of conductive elements patterned in a grid-type array. A plurality of bond pads on the semiconductor die is coupled to the plurality of conductive elements, such as by wire bonding. The semiconductor die and at least a portion of the lead frame are encapsulated in an insulative material, leaving the conductive elements exposed along a bottom major surface of the package for subsequent electrical connection with higher-level packaging. Individual conductive lead elements, as well as the grid array pattern, are formed by wire bonding multiple bond pads to a single lead at different locations and subsequently severing the leads between the bonding locations to form multiple conductive elements from each individual lead.

Abstract: A power distribution system is provided for an automobile mirror assembly or the like, and includes a flexible membrane having electrical traces electrically connected to the vehicle electrical system, and connecting sites for electrically connecting to various power consumers in the mirror assembly.

Abstract: An integrated bus bar structure plate in which a plurality of bus bars are arranged on substantially the one plain face to form an electric power circuit, wherein after the bus bar structure plate having a whole shape in which a plurality of types of electric power circuits are formed by selecting any of the connection parts of the bus bars is separated is adhered to the control circuit board whereby, for example, a desired electric power circuit is formed among the connection parts of bus bars.

Abstract: A system and method provides an electrical contact assembly for an optical device useable in a three-dimensional optical display. The assembly includes a first conductor comprising a first intermediate section that includes a first contact for connecting to a contact of the optical device, where a first and second pair of tabs extend outwardly in opposite directions from the first intermediate section. The assembly also includes a second conductor comprising a second intermediate section including a second contact for connecting to an other contact of the optical device, where a third pair of tabs extend outwardly in opposite directions to the second intermediate section. The first and second conductors are positioned relative to each so that the first and second pair of tabs, and the third pair of tabs each extend in a different plane. The tabs are connected to tabs of other assemblies for creating a three-dimensional display.

Abstract: A circuit-constituting unit forming a distribution circuit or the like in a vehicle. The circuit-constituting unit includes a plurality of bus bars for constituting a power circuit; a semiconductor switching device provided in the power circuit; and a control circuit board. The bus bars are bonded to a surface of the control circuit board such that the bus bars are arranged to be generally coplanar with each other. The semiconductor switching device is mounted on both of the corresponding bus bars and the control circuit board. An opening may be formed through the control circuit board. In this case, one of terminals of the semiconductor switching device may be connected to a surface of the control circuit board facing away from the surface to which the bus bars are bonded. The other terminals may be connected respectively to the bus bar through the opening.

Abstract: The present invention provides a semiconductor device comprising a semiconductor substrate, and transistors formed on the semiconductor substrate, wherein control electrode terminals constituting external electrode terminals of the transistors, and first electrode terminals which transmit output signals, are provided on a main surface of the semiconductor substrate, wherein the control electrode terminals are provided at least one, and a plurality of the first electrode terminals are arranged on one side and a plurality of the first electrode terminals are arranged on the other side with the control electrode terminals being interposed therebetween, wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on one side of the control electrode terminals constitute a first transistor portion, and wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on the other side of the control electrode

Abstract: In a semiconductor package including at least one plate-like mount, a semiconductor chip has at least one electrode formed on a top surface thereof, and is mounted on the plate-like mount such that a bottom surface of the semiconductor chip is in contact with the plate-like mount. The semiconductor package also includes at least one lead element having an outer portion arranged to be flush with the plate-like mount, and an inner portion deformed and shaped to overhang the semiconductor chip such that an inner end of the lead element is spaced apart from the top surface of the semiconductor chip. The semiconductor package further includes a bonding-wire element bonded at ends thereof to the electrode of the semiconductor chip and the inner end of the lead element, an enveloper sealing and encapsulating the plate-like mount, the semiconductor chip, the inner portion of the lead element, and the bonding-wire element.

Abstract: The specification describes a leadframe that is aimed at high-performance digital IC devices with high-pin counts, and packaged using wire bond technology. According to the invention the configuration of the paddle is modified to add a new dimension to the leadframe design. In a preferred embodiment, one or more slots are formed in the paddle to allow the length of selected wire bonds to be reduced. This reduces the susceptibility of these selected leads to parasitic capacitances. The selected leads are typically those that carry very high-speed signals.

Abstract: In a drive circuit for an electric motor, there is provided a circuit board, at least one semiconductor device mounted to the circuit board and a spacer. The semiconductor device has a semiconductor chip, a chip package incorporating therein the semiconductor chip and comprising a mounting member for mounting on the circuit board, and terminals for connections of the semiconductor chip to the circuit board. The spacer is interposed between the circuit board and the mounting member of the chip package so as to provide a space between the circuit board and the chip package.

Abstract: A quad flat no-lead (QFN) grid array semiconductor package and method for making the same is disclosed. The package includes a semiconductor die and a lead frame having a plurality of conductive elements patterned in a grid-type array. A plurality of bond pads on the semiconductor die is coupled to the plurality of conductive elements, such as by wire bonding. The semiconductor die and at least a portion of the lead frame are encapsulated in an insulative material, leaving the conductive elements exposed along a bottom major surface of the package for subsequent electrical connection with higher-level packaging. Individual conductive lead elements, as well as the grid array pattern, are formed by wire bonding multiple bond pads to a single lead at different locations and subsequently severing the leads between the bonding locations to form multiple conductive elements from each individual lead.

Abstract: A leadless optical electronic package includes a lead frame having a die-attach pad and a plurality of leadless connection pads encapsulated in and extending through an encapsulation defining a planar mounting surface that can be soldered directly to a circuit board. The die-attach pad and connection pads define internal surfaces that remain partially exposed through the encapsulation. The internal surfaces are for attaching an electronic die and making electrical connections between the die and the connection pads. A die mounted on the die-attach pad is cooled more effectively and efficiently than dice in prior optical electronic packages. The leadless connection pads reduce the footprint and height of the package compared with prior optical electronic packages. The encapsulation is adapted for receiving a cover having a cover glass to allow light to pass though the cover and illuminate the die. The cover is adapted to receive an optics component for projecting light through the cover glass onto the die.

Abstract: A conductive sash is etched around the periphery of a land grid array interconnection on a carrier for dense integrated circuit connections. If the array comprises more than one module or module chip domain, the conductive sash is also positioned between the modules. The dimensions of the sash are such that it is slightly larger than a frame of an interposer or other electrical connector which is placed upon the array. In this fashion, the interposer or other electrical connector rests upon the sash and provides protection against particulate and gaseous contamination of the array.

Abstract: A connection component for use in making microelectronic element assemblies which has peelable leads that are formed on a dielectric support structure. One end of each lead is permanently connected to the support structure and the opposite end of the lead is releasably connected to the support structure. When the releasable end of the lead is bonded to a contact on a semiconductor chip, the releasable end of the lead can be peeled from the support structure such that the chip may be moved away from the support structure. A compliant layer may be disposed between the chip and the support structure. If a compliant material is injected between the chip and the support structure to form the compliant layer, the compliant material will lift the chip away from the support structure and facilitate the peeling of the leads from the support structure.

Abstract: In a flat pin to be used in a circuit board made of resin with pins comprising a rod portion having a diameter of not greater than 0.35 mm and a concentric tabular large diameter portion having a larger diameter than that of the rod portion formed on one end of the rod portion, the ratio (W/S) of the diameter of the large diameter portion to the rod portion is from not smaller than 2.16 to not greater than 2.67 and the ratio (T/S) of the thickness of the large diameter portion to the diameter of the rod portion is from not smaller than 0.40 to not greater than 0.67 supposing that the diameter of the rod portion and the large diameter portion of the flat pin are S and W, respectively, and the thickness of the large diameter portion is T.

Abstract: According to one embodiment, a printed circuit board (PCB) is disclosed. The PCB includes a first functional unit block (FUB) and differential traces coupled to the first FUB. The first FUB transmits high-speed serial data. The differential traces carry the high-speed serial data from the first FUB. In addition, the differential traces crossover on the same layer of the PCB while maintaining a constant impedance.

Abstract: A circuitized substrate has contact pads for mounting a Surface Mount Device (SMD). First and second contact pads are located on a surface of the substrate corresponding to a first terminal and a second terminal of the SMD. The first and the second contact pads have a plurality of expanded portion or diminished portions to form bead receptacles at the facing corners thereof. When solder paste is reflowed to electrically connect the SMD, solder beads formed from the solder paste can be fixed on the bead receptacles. Therefore, there is no free solder bead on the substrate causing short circuit for semiconductor packages.

Abstract: A method of flip-chip mounting a circuit device to a substrate in a manner that avoids damage and impairment of a fragile or otherwise sensitive element on the device facing the substrate, and a circuit assembly produced thereby. The assembly includes a substrate having at least two sets of bonding sites spaced apart from each other to define an intermediate surface region therebetween. The device is attached to the bonding sites with solder connections, with the solder connections being present on a surface of the device that faces the substrate and on which the element is present so that the element overlies the intermediate surface region of the substrate. An underfill material is present between the device and the substrate and encapsulates the solder connections. The underfill material is separated from the intermediate surface region of the substrate so that the underfill material does not contact the element.

Abstract: The invention relates to a method for making an integrated circuit (40) of the surface-mount type the comprising, first of all, manufacture of a package having a rear face and a pin grid array extending under this rear face perpendicular thereto, and a ball (44) of low melting point alloy is then formed at the end of each pin surrounding this end and soldered thereto. The invention also relates to an integrated circuit (40) of the surface-mount type, comprising a package having a rear face and a pin grid array, of a cross section roughly constant along the pin (42), extending under the rear face perpendicular thereto. A ball (44) of low melting point alloy is soldered to the end of each pin (42) surrounding this end.

Abstract: An insulating substrate (17) includes a surface conductive layer (25) fixedly laminated on a surface of the plate-like semiconductor body (21) via a surface side fixing member (24, 26). The surface side fixing member (24, 26) includes a first fixing portion (26) for fixing one part (25a) of the surface conductive layer (25) located underneath the joint portion (15) of the electrode terminal (14), and a second fixing portion (24) for fixing the other part (25b) of the surface conductive layer (25) which is not located underneath the joint portion (15), and a fixing strength exhibited by the first fixing portion (26) is smaller than that exhibited by the second fixing portion (24).

Abstract: A semiconductor device assembly including a semiconductor device having a plurality of bond pads on the active surface thereof and a lead frame having a portion of the plurality of lead fingers of the lead frame located below the semiconductor device in a substantially horizontal plane and another portion of the plurality of lead fingers of the lead frame located substantially in the same horizontal plane as the active surface of the semiconductor device. Both pluralities of lead fingers of the lead frame having their ends being located substantially adjacent the peripheral sides of the semiconductor device, rather than at the ends thereof.

Abstract: A resin-sealed semiconductor IC package of a large integration size having a size substantially equal to that of its component semiconductor IC chip. The resin-sealed semiconductor IC package includes a semiconductor IC chip, a plurality of leads arranged on the semiconductor IC chip and having end portions bent so as to extend perpendicularly to the major surface of the semiconductor IC chip, a resin molding sealing the semiconductor IC chip and the leads therein so that the tips of the end portions of the leads are exposed on one surface thereof, and conductive elements connected respectively to the exposed tips of the leads.

Abstract: The present invention provides an improved structure of gold fingers, which is to redesign a conventional gold finger on a packaging substrate into a gold finger set that contains a plurality of gold finger units. Between each single gold finger unit, there exists an electrical connection. Therefore, in the structure of stacked-chip packaging, each wire that is connected through wire bonding on the same gold finger of each layer chip can separately perform wire bonding on different gold finger units of the same gold finger set. Due to the improvement on the gold finger structure, the present invention can prevent the adhesive on a chip from flowing along the wire bonding path of a layer chip and smearing the whole gold finger. Thus, other layer chips can be prevented from being unable to perform wire bonding.

Abstract: A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.

Abstract: According to one embodiment, a printed circuit board (PCB) is disclosed. The PCB includes a first functional unit block (FUB) and differential traces coupled to the first FUB. The first FUB transmits high-speed serial data. The differential traces carry the high-speed serial data from the first FUB. In addition, the differential traces crossover on the same layer of the PCB while maintaining a constant impedance.

Abstract: A circuit board includes a substrate and electrical contacts to mate with a slot connector. The contacts include a first set of contacts that are associated with the communication of power and second set of contacts that are associated with the communication of signals and are not used to communicate power. Adjacent contacts of the first set have a first spacing, and adjacent contacts of the second set have a second spacing different from the first spacing. The circuit board has a retention profile to engage a retention mechanism of the slot connector. A housing of the slot connector may be made from a material that has a thermal conductivity of at least 0.27 W/m·K, and the slot connector housing may include fins that are formed on the slot connector to conduct heat away from circuitry of the circuit board.

Abstract: A semiconductor integrated circuit device, and method of manufacturing the same, having a conventional-type lead frame with the die paddle removed. In particular, the die paddle is replaced with a section of tape that is supported by the ends of the lead fingers. The semiconductor die is attached to the tape so that it may be wire bonded to the lead fingers. The tape contains at least one slot to allow for expansion and/or contraction of the tape due to various temperatures experienced during the manufacturing process so that the tape does not wrinkle or warp to alter the position of the die.

Abstract: The device has a package with a base plate, and at least two terminal pins perpendicularly protruding from the base plate of the package. At least one of the terminal pins is a high-frequency terminal pin that transmits a high-frequency signal. The device has a flexible conductor arrangement with a plurality of interconnects. The conductor arrangement provides an electrical connection between the terminal pins of the package and electrical contacts of a printed circuit board. The conductor arrangement has contact regions for electrically connecting the interconnects to a terminal pin and to a contact of a printed circuit board. At least the region of the conductor arrangement that provides a connection to high-frequency terminal pin lies in a plane aligned substantially perpendicular to the plane of the base plate.

Abstract: A reliable microchip controller board and a manufacturing method thereof suitable for mass production are provided. A board wherein a programmable microchip controller is mounted includes; terminals for writing a program into the microchip controller and a circuit pattern connecting an operating terminal to shared terminals which are disconnected. A non-programmed microchip controller is mounted on the board in a state where patterns are disconnected and then programmed. The disconnected portion is connected thereafter.