Having Backplane Connection Patents (Class 361/788)
  • Patent number: 6661675
    Abstract: Described is a computer having two circuit boards (10, 11) on which plug connectors (15) are present for plug-in cards (16) which project above the circuit boards (10, 11) to a first height (H1). There is a bridge card (19), which is plugged into the two circuit boards (10, 11), connecting the two circuit boards (10, 11) electrically, and which project above the circuit boards (10, 11) to a second height (H2). The bridge card (19) is connected to the two circuit boards independently of the plug connectors (15), and the first height (H1) is greater than the second height (H2).
    Type: Grant
    Filed: January 28, 2002
    Date of Patent: December 9, 2003
    Assignee: Hartmann Elektronik GmbH
    Inventor: Hans-Otto Brosowski
  • Patent number: 6657548
    Abstract: A system status light indicator device embedded in a connecting port is made up of an error message processor and a plurality of light emitting diodes (LED), suitable for use with a Basic Input-Output System (BIOS) program. When the BIOS examines a plurality of the peripheral devices on the computer, as soon as an error is found, the warning signals can be sent to the error message processor, and then the corresponding error message data is retrieved. Next, it outputs the error message data to the system status indicator devices embedded in a connecting port. Thus, the operators can know exactly where the problems are located via the indicated boot-up warning signals sent out that indicate system status, and the messages corresponding to the light indicators recorded in the user's manual. The above-described error message data uses the light indicators to display the various causes of breakdown.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: December 2, 2003
    Assignee: Asustek Computer Inc.
    Inventor: Ming-Hou Dai
  • Patent number: 6643141
    Abstract: A transmission apparatus which is capable of maintaining excellent EMC performances even if the number of cables to be connected thereto is increased. An electronic circuit unit is plugged into a subrack from the front of the subrack. A connector unit-receiving block is arranged on the rear surface of the subrack. A connector unit connectable with an external cable to be connected to the electronic circuit unit is plugged into the rear of the subrack at the rear of the electronic circuit unit, for being received within the connector unit-receiving block. The connector unit is configured such that a metal shield case covers a connector board having a connector mounted thereon.
    Type: Grant
    Filed: July 2, 2001
    Date of Patent: November 4, 2003
    Assignee: Fujitsu Limited
    Inventors: Mitsuo Kaetsu, Kazumasa Yoshito, Takashi Inoue, Tsutomu Takahashi
  • Publication number: 20030198035
    Abstract: A circuit card that includes a single ground plane connectable to a chassis-ground and a logic device having a ground pin connected to the single ground plane. The connection between the ground pin and the single ground plane provides a direct path between the logic device and the chassis-ground. A power supply is connected to an input pin of the logic device for providing a logic voltage to the logic device. The power supply is connectable to a battery.
    Type: Application
    Filed: April 22, 2002
    Publication date: October 23, 2003
    Applicant: ADC DSL Systems, Inc.
    Inventors: Donald J. Glaser, Douglas G. Gilliland, Dennis J. Vandenberg
  • Publication number: 20030198033
    Abstract: A processor mounted to a circuit board is provided with regulated voltage through lower-inductance circuit board traces by mounting a voltage regulator module for the processor, on the side of the circuit opposite to the processor. Current from the voltage regulator is provided to the processor by way of one or more conductors between the regulator and processor that extend through the circuit board from one side to the other. Inductance attributable to lead length is reduced by locating the voltage regulator close to its load. Circuit board space on the processor side of the circuit board is increased by moving the voltage regulator to the opposite side.
    Type: Application
    Filed: February 25, 2003
    Publication date: October 23, 2003
    Inventors: Augusto P. Panella, John E. Lopata, James L. McGrath, Arindum Dutta
  • Patent number: 6633490
    Abstract: An electronic board assembly carrying connectors on each side of its lower edge which is adapted to withstand the relatively strong forces required to insert or remove the assembly, e.g., from a backplane board, and yet provide many electrical contacts along the interconnection sites. The electronic board assembly comprises two symmetrical elementary PCBs electrically coupled together, each carrying a connector on its external lower edge. In one embodiment, these two PCBs are coupled together by a flexible adhesive insulative layer and maintained by mechanical devices such that the distance between these two connectors is set to a predetermined distance (to align precisely with the backplane board). The mechanical device used to maintain a predetermined distance between the two connectors of the assembly may comprise a U-shaped member, the upper part of this member being strategically inserted between these connectors.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: October 14, 2003
    Assignee: International Business Machines Corporation
    Inventors: Bruno Centola, Claude Gomez, Christian Ouazana
  • Patent number: 6628525
    Abstract: A telecommunications device including a chassis having a card housing for containing a plurality of splitter cards. The housing includes front and back ends. The front end defines an access opening for allowing the splitter cards to be inserted into or removed from the card housing. The device also includes a plurality of card edge connectors for providing electrical connections with the splitter cards. The card edge connectors are located within the card housing adjacent to the back end of the housing. The device further includes LINE, POTS and DATA connectors electrically connected to the card edge connectors. Guide members are located adjacent the back end of the housing for directing the splitter cards into the card edge connectors as the splitter cards are inserted into the card housing. The guide members include ramps aligned at oblique angles relative to a direction of insertion of the splitter cards.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: September 30, 2003
    Assignee: ADC Telecommunications, Inc.
    Inventors: Jennifer L. Miller, Jason S. Piehl
  • Publication number: 20030169577
    Abstract: A system and method for introducing user-defined (e.g., proprietary) signals into a standard backplane. In addition to standardized connectorization, at least one of the front side connector segments or at least one of the rear side connector segments is provided with additional non-standard connector holes, thereby forming an extra-wide segment. The inclusion of extra contact points in a connector segment allows for supporting an independent signal pathway to carry one or more user-defined signals across the backplane, in addition to the standard bus signals, without sacrificing compliance with the applicable bus standard.
    Type: Application
    Filed: March 5, 2002
    Publication date: September 11, 2003
    Inventors: Ignacio A. Linares, Robert S. Gammenthaler, Gerald R. Dubois
  • Publication number: 20030161126
    Abstract: In an active semiconductor backplane for a liquid crystal spatial light modulator, spacers (25) which are distributed over the backplane extend above an array of electrical and/or electronic elements and comprise at least two layers essentially of the same material and occuring in the same order as is found in at least one of the electrical or electronic elements, such as an NMOS transistor (52). The latter is formed from a stack of layers on a silicon substrate (51) comprising polysilicon (56), continuous silicon oxide (57) modified to include gate oxide GOX (55), metallic gate electrode (59), continuous silicon oxide (58) and a metallic drain electrode (60) which is coupled to a spaced mirror electrode over the layer (58). Likewise, spacer (25) comprises the layers (57 and 58) with metallic (67, 68) deposited simultaneously with electrodes (59, 60). The foot of layer (57) is differently modified to include field oxide layer (69) and polysilicon layers (70, 72) spaced by thin oxide (71).
    Type: Application
    Filed: February 28, 2002
    Publication date: August 28, 2003
    Inventors: Timothy D. Wilkinson, William A. Crossland, Tat C.B. Yu
  • Patent number: 6611433
    Abstract: A motherboard module includes a motherboard, a backboard, and a modular mechanism. The modular mechanism for fast assembly and disassembly of a motherboard includes an upright, an upstanding structure, and a fastener. The upstanding structure is used for positioning the motherboard. Since the upstanding structure is perpendicularly attached to the back edge of the motherboard and the backboard is adhered to one surface of the upstanding structure, the fastener presses and engages the backboard so that the upright clinches the slit in the motherboard and the motherboard is thus secured.
    Type: Grant
    Filed: June 5, 2002
    Date of Patent: August 26, 2003
    Assignee: Quanta Computer Inc.
    Inventors: Chih-Hsiang Lee, Guo-Ming Huang, Ching-Yuan Wang
  • Patent number: 6608761
    Abstract: In a Compact PCI system, a method and apparatus for bridging multiple PCI segments in a chassis utilizing backplane connections, instead of a front side component slot. Embodiments of the present invention may be used, with either a transparent or non-transparent bridging system, between multiple PCI segments, to increase the number of shared peripherals in a single Compact PCI chassis.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: August 19, 2003
    Assignee: Intel Corporation
    Inventor: Robert D. Wachel
  • Patent number: 6608762
    Abstract: A data processing apparatus, having a first plurality of circuit boards arranged generally side-by-side and a second plurality of circuit boards arranged generally side-by-side, the first plurality of circuit boards being mounted to the second plurality of circuit boards by a midplane. The midplane has a first main surface, a second main surface and a plurality of connector elements, each connector element including an array of electrical couplers that extend generally transversally to the main surfaces of the midplane. The array of electrical couplers connect data contacts on one circuit board mounted to the first surface of the midplane to data contacts of another circuit board mounted to the second surface of the midplane. The connection between the circuit boards is such that each data contact on one circuit board and the corresponding data contact of the other circuit board are in physical contact with a common electrical coupler.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: August 19, 2003
    Assignee: Hyperchip Inc.
    Inventor: Dorinel Patriche
  • Patent number: 6606656
    Abstract: A module connection assembly connects modules in a torus configuration that can be changed remotely. In particular, a single module can be added to or deleted from the configuration by remotely switching from conducting paths that provide end-around electrical paths to conducting paths that provide pass-through electrical paths. The assembly includes two backplanes, a first set of module connectors for electrically connecting modules to one of the backplanes, and a second set of module connectors for electrically connecting modules to the other backplane. The assembly further includes configuration controllers. Each configuration controller selects between end-around electrical paths that electrically connect multiple module connectors of the first set to each other, and pass-through electrical paths that electrically connect module connectors of the first set to module connectors of the second set.
    Type: Grant
    Filed: January 18, 2001
    Date of Patent: August 12, 2003
    Assignee: Avici Systems, Inc.
    Inventors: Philip P. Carvey, William J. Dally, Larry R. Dennison
  • Publication number: 20030142483
    Abstract: A switching device and a method for the configuration thereof is disclosed. A first aspect of the present invention comprises a switching device. The switching device comprises at least one line card and at least one switching card. The device includes a mid-plane coupled to the at least one line card and the at least one switching card. The A second aspect of the invention comprises a method for configuring a switching device. The method for configuring a switching device comprises providing a mid-plane, and providing at least one switching card and at least one line card on the mid-plane. The at least one switching card and the at least one line card are perpendicular to each other. Through the use of the present invention, line cards and/or switch cards can be connected to a mid-plane via a plurality of connectors wherein the line cards and switching cards are perpendicular to each other.
    Type: Application
    Filed: January 30, 2002
    Publication date: July 31, 2003
    Inventor: Ofer Iny
  • Patent number: 6600647
    Abstract: A computer system is provided comprising a support frame, a logic board mounted to the support frame, a processor on the logic board, a cathode ray tube mounted to the support frame above a plane of the logic board, and a transparent housing located over the cathode ray tube.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: July 29, 2003
    Assignee: Apple Computer, Inc.
    Inventors: Brian J. Girvin, Larry Forsblad, Brian H. Berkeley, Douglas L. Heirich, Steve Cabral, Robert Norman Olson, David Hoenig, Peter Krause
  • Patent number: 6594153
    Abstract: A circuit package has been described for routing long traces between an electronic circuit, such as a phase locked loop, and external circuit components. The traces are routed through two substrates. In each substrate, the traces are routed primarily on a layer adjacent to and between a pair ground planes located close to the traces. Degassing apertures are located to the side of the long traces to avoid interfering with the shielding provided by the grounds planes. The circuit package uses two power plated through holes and two ground plated through holes to reduce the noise on the power supply lines. The circuit package also separates the signal carrying plated through holes from the power plated through holes, which reduces noise on the long traces. Noise is further reduced on the long traces by using the ground plated through holes to shield the signal carrying plated through holes from noise generated at the power plated through holes.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: July 15, 2003
    Assignee: Intel Corporation
    Inventors: Longqiang L. Zu, Jennifer A. Hester
  • Patent number: 6587354
    Abstract: A telecommunication assembly having a plurality of slots for receiving a plurality of modules therein. The telecommunication assembly couples to a telecommunication network and includes a plurality of distinct backplane circuit boards secured therein for each coupling to one of the plurality of modules. Each of the plurality of distinct backplane circuit boards includes a bounding edge, a back side partially encompassed by the bounding edge, a plurality of first connectors coupled to the back side for receiving a telecommunication signal from the telecommunication network, a front side coupled to the back side, and a second connector mounted on the front side and spaced apart from the at least one jack for coupling to one of the plurality of modules. The telecommunication assembly is operable with one or more of the plurality of distinct backplane circuit boards removed from the assembly.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: July 1, 2003
    Inventors: Duane B. Kutsch, Loren M. Borg, Merril R. Gordon, Gary M. Peterson, Charles William “Bill” White
  • Patent number: 6582133
    Abstract: An interconnection module for holding and interconnecting optoelectronic cards is provided. It includes an optical midplane which accommodates and flexibly interconnects N optoelectronic cards on one side of the midplane and M cards on the other side of the midplane. Optical connectors, which are arranged on the midplane and on the cards, provide arrangement of cards on the midplane in one of the two positions, in the first position the cards on opposite sides of the midplane being parallel to each other, and in the second position the cards being perpendicular to each other. Preferably, each of the N cards on one side is connected to a subset of cards on the other side, the number of cards in the subset being variable for each of the N cards and less or equal to M in total. Additionally, a backplane section of the module, having a plurality of connectors joined via laminated strands, may be added as an extension of the midplane to interconnect any required number of cards on same side of the midplane.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: June 24, 2003
    Assignee: Tropic Networks Inc.
    Inventors: Mark Roy Harris, David Andrew Knox
  • Patent number: 6574726
    Abstract: A computer system architecture in which functionally compatible electronic components are located on modular printed circuit boards. Thus, a type of processor used by the system can be changed by replacing the printed circuit board incorporating the processor. Similarly a type of peripheral bus used can be changed simply by replacing the printed circuit board containing the peripheral controller. High-density connectors connect the circuit boards. Some embodiments of the invention use a single backplane. Other embodiments place peripheral slots on a second, passive backplane.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: June 3, 2003
    Assignee: Silicon Bandwidth, Inc.
    Inventor: Stanford W. Crane, Jr.
  • Patent number: 6563714
    Abstract: A mobile rack with IDE and USB interfaces comprises an outer frame, and an outer circuit board. The outer frame has a central frame chamber. The outer circuit board is attached to the rear side of the outer frame with a 40-pin IDE interface connector and a power input socket at the outer side thereof respectively.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: May 13, 2003
    Inventor: Cheng-Chun Chang
  • Patent number: 6538899
    Abstract: A traceless midplane contains substantially no traces, pins, or active components and includes a front portion and a back portion. The front portion includes first connectors. The back portion includes second connectors arranged in a grid pattern. Each of the second connectors includes electrically-conductive conduits that connect the second connector to a corresponding one of the first connectors through the midplane. The second connectors include data connection points, ground connection points, and clock connection points. At least some of the data connection points are separated from each other and from the clock connection points by the ground connection points.
    Type: Grant
    Filed: January 2, 2001
    Date of Patent: March 25, 2003
    Assignee: Juniper Networks, Inc.
    Inventors: Ashok Krishnamurthi, Ramalingam K. Anand
  • Patent number: 6535397
    Abstract: An interconnect structure interconnects electronic modules and includes a backplane assembly formed from a substantially rigid backplane plate that carries RF connectors and a digital motherboard having digital connectors for mating with digital connectors of electronic modules. A controlled impedance interconnect circuit is positioned on the rear surface of the backplane plate and interconnects the RF connectors carried by the backplane plate and digital connectors of the digital motherboard. A rack receives the backplane assembly and supports a plurality of electronic modules that are interconnected to each other via the backplane assembly.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: March 18, 2003
    Assignee: Harris Corporation
    Inventors: William Clark, Douglas Heckaman, Edward Bajgrowicz
  • Patent number: 6533587
    Abstract: A riser card, such as a peripheral component interconnect (PCI) card, attaches to a circuit board such as a mother board in a transverse orientation and has a first connector and a second connector attached to opposing sides of the card for receiving expansion cards. In one embodiment, the first connector is offset from the second connector with respect to an axis in the plane of the riser card. In another embodiment, the first and second connectors each have a first and last pin, and the first pin of the first card is opposite the first pin of the second connector. The riser card may mount one expansion board right side up, and the second board upside down. The first and second connectors can be female connectors which are each matable with a male connector on the corresponding expansion board, or can be card edge connectors. The expansion boards, when mated with the connectors, are substantially parallel to, but offset from the circuit board.
    Type: Grant
    Filed: July 5, 2001
    Date of Patent: March 18, 2003
    Assignee: Network Engines, Inc.
    Inventors: David Potter, Jerry Jarvis, Robert Wiley
  • Patent number: 6528737
    Abstract: A midplane board adapted for use in an electronic equipment shelf is provided. The midplane board includes a first surface having a plurality of contact elements adapted to engage corresponding contact elements on a first circuit board. The midplane board also includes a second surface in opposite relationship with the first surface. The second surface has a plurality of contact elements adapted to engage corresponding contact elements on a second circuit board in such a manner that at least a portion of a side of the first circuit board is opposed to at least a portion of a side of the second circuit board. The midplane includes at least one signal connection path including a buried via suitable for establishing a connection between a contact element on the first surface and a contact element on the second surface. The contact elements on the first surface define a first pattern while the contact elements on the second surface define a second pattern.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: March 4, 2003
    Assignee: Nortel Networks Limited
    Inventors: Herman Kwong, Richard R. Goulette
  • Patent number: 6512396
    Abstract: A backplane of a data processing system is configured to include a current boost circuit for each net. The boost circuit is coupled to a common point for the net and is triggered to provide a boost current in response to a detected change in a signal on the net. The boost circuit has the capacity to provide a considerably larger drive current than does the conventional driver on the circuit board connected to the backplane. Thus when a conventional driver starts to drive a signal on the net from one logic state to the other, the boost circuit detects the initiation of change and supplies a boost current to cause a rapid change in logic state. Preferably each terminal on the net is coupled to the common point by a trace which includes both a highly conductive portion and a portion including a damping impedance. The damping impedance is chosen to approximate the characteristic impedance of the trace coupling the terminal to the common point and the associated loading of that trace.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: January 28, 2003
    Assignee: Arizona Digital, Inc.
    Inventor: Andrew R. Berding
  • Publication number: 20030016513
    Abstract: In some embodiments, the invention includes a system having first and second modules, the first module having a first group of chips and the second module having a second group of chips, and a circuit board including first and second module connectors to receive the first and second modules, respectively. The system also includes a first buffer on the first module and a second buffer on the second module, and a path including conductors in a first section that splits into a second section and third section, wherein the second section couples to the first buffer and the third section couples to the second buffer, and wherein impedances of the second and third sections are at least 50% greater than impedances of the first section.
    Type: Application
    Filed: July 23, 2001
    Publication date: January 23, 2003
    Inventors: James A. McCall, Hing Thomas Y. To
  • Publication number: 20030007338
    Abstract: A device is described for a computer having two circuit boards (10, 11) on which plug connectors (15) are present for plug-in cards (16) which project above the circuit boards (10, 11) with a first height (H1). There is a bridge card (19), which is plugged into the two circuit boards (10, 11), connecting the two circuit boards (10, 11) electrically and projecting above the circuit boards (10, 11) with a second height (H2). According to this invention, the bridge card (19) is connected to the two circuit boards independently of the plug connectors (15), and the first height (H1) is greater than the second height (H2).
    Type: Application
    Filed: January 28, 2002
    Publication date: January 9, 2003
    Inventor: Hans-Otto Brosowski
  • Publication number: 20030007339
    Abstract: A stacked backplane assembly, including two or more backplanes or midplanes having different functionality and combined together so as to form an integral unit, is provided. The backplanes forming the assembly are manufactured with prime and secondary manufacturing holes to enable alignment, so that the resulting tolerance build-up of the assembly is similar to that of a single backplane. Connectors can be arranged on the backplanes of the assembly so that an electronic or optical card can be simultaneously plugged in to one or more of the backplanes that comprise the stacked backplane assembly. The stacked backplane assembly of the embodiments of the invention is illustrated by having power and signal backplanes and midplanes, but can be equally applied to backplanes that provide other types of functionality.
    Type: Application
    Filed: February 5, 2002
    Publication date: January 9, 2003
    Inventors: Mark Roy Harris, Rodney Stephen Batterton
  • Patent number: 6504725
    Abstract: The present invention provides a compact riser card system which provides two or more PCI connectors to couple one or more peripheral boards to a PCI bus on a computer board while satisfying the height requirements for 1U systems. In one embodiment, this invention provides two 64-bit connectors on two riser cards coupled to a single connector on a 66 MHz PCI bus.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: January 7, 2003
    Assignee: Intel Corporation
    Inventor: Don T. Lam
  • Patent number: 6504730
    Abstract: A power distribution assembly (PDA) includes AC and/or DC power modules and control modules that are installed within a chassis that is mounted to a vehicle, such as an aircraft. Each module includes a wiring harness connector and a control connector for attachment to a motherboard. A wiring harness is externally mounted to the chassis to provide a simplified connection for the wiring harness connector. The modules can be individually and selectively removed from the chassis for repair or replacement without having to remove the entire PDA from the aircraft. This is accomplished by simply removing the module from the chassis, thereby disconnecting the aircraft interface and motherboard connectors for the selected modules. Also, a common PDA can be utilized on different types of aircraft by installing desired modules within the chassis. Thus, the number and type of modules are selected to meet predetermined specifications for a specific aircraft and then installed within a PDA common to all aircraft.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: January 7, 2003
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Robert C. Cooney, John A. Dickey, Mark W. Metzler, Bruce D. Beneditz
  • Patent number: 6498728
    Abstract: A modular structure for carrying a printed circuit board, having to be connected to an electronic installation. The modular structure includes two cover plates opposite each other, contributing to defining a housing for at least one printed circuit board. The cover plates engage one another by sandwiching, via a first edge, a support for one or more connection blocks for the connection and, via a second edge, a support for a locking mechanism in order to hold the structure in a connected position. The support for the locking mechanism and for the connection blocks have ends which are separate before the assembly of the cover plate. Such a modular structure may find particular application to electronic installations of the integrated modular avionics type.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: December 24, 2002
    Assignee: Thomson-CSF Sextant
    Inventors: Claude Sarno, Henri Bouteille
  • Patent number: 6496380
    Abstract: The present invention features a memory module for use in conjunction with high speed, impedance-controlled buses. Each memory card may be a conventional printed circuit card with memory chips attached directly thereto. Alternately, high density memory modules assembled from pluggable sub-modules may be used. These sub-modules may be temporarily assembled for testing and/or burn-in. Bus terminations mounted directly on the memory card or the memory module eliminate the need for bus exit connections, allowing the freed-up connection capacity to be used to address additional memory capacity on the module. An innovative pin-in-hole contact system is used both to connect sub-modules to the memory module and, optionally, to connect the memory module to a motherboard or similar structure. A thermal control structure may be placed in the memory module, cooling the increased number of memory chips to prevent excess heat build-up and ensure reliable memory operation.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: December 17, 2002
    Assignee: High Connection Density, Inc.
    Inventors: Che-Yu Li, David A. Lysack, Thomas L. Sly
  • Patent number: 6496376
    Abstract: A set of modules from which custom passive backplanes can be assembled coplanarly couple together and are mounted on a rigid base plate which holds them coupled and coplanar. Each module has a plurality of orthogonally oriented card connectors. Preferably there is a CPU module into which is plugged a CPU card from which an ISA and a PCI originates. On one edge of the CPU module is an connector communicating with the ISA bus. This connector is for chaining together one or more ISA modules, each of which expands the ISA bus to three more ISA connectors. On an opposite edge of the CPU module is an connector communicating with the PCI bus. This connector is for chaining together one or more PCI modules, either 32-bit or 64-bit, each of which expands the PCI bus to three more PCI connectors. Power and ground can be jumpered from module to module or can be directly connected to any module.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: December 17, 2002
    Inventors: John Plunkett, Travis Evans, Mark Perona, Robert Wilson
  • Publication number: 20020181215
    Abstract: A reconfigurable logic structure utilizes a midplane circuit board assembly having a plurality of reprogrammable logic boards mounted in a first direction on one side of the midplane circuit board and a plurality of programmable interconnect boards mounted in a second direction on an opposite side of the midplane circuit board. The logic and interconnect boards attach to the midplane circuit board through connectors which are surface mounted to the front and back sides of the midplane circuit board. The surface mounting of the midplane board connectors allows more dense electrical connections and increased density of midplane board routing compared to the prior art and is particularly useful in the construction of reprogrammable logic emulators and logic simulators because of the particular nature of the interconnects often needed in the construction of such machines.
    Type: Application
    Filed: July 24, 2002
    Publication date: December 5, 2002
    Inventor: Russell W. Guenthner
  • Patent number: 6490169
    Abstract: An electrically conductive circuit conductor 2 is disposed on an insulating resin substrate 1, an electrically conductive surface 3 of the circuit conductor is exposed from the resin substrate continuously in a longitudinal direction, and both side portions 4 of the conductive surface are covered and fixed by collar walls 5 of the resin substrate. A bus bar or an electrically conductive resin material is used as the circuit conductor 2. The bus bar 2 is insert-molded onto the resin substrate. The electrically conductive resin material is poured and solidified in a groove portion in the resin substrate. A contact terminal on a mating circuit side or electrical component side is brought into contact with the conductive surface of the circuit conductor 2. A second circuit board is laminated on the resin substrate, and an insertion hole for allowing the conductive surface of the circuit conductor 2 to be exposed is provided in the second circuit board, and the contact terminal is inserted in the insertion hole.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: December 3, 2002
    Assignee: Yazaki Corporation
    Inventor: Hiroshi Watanabe
  • Patent number: 6487086
    Abstract: A memory module (10) having a module bus line (15) that can be electrically connected to a main board bus line (22) by a contact terminal (12). Main board bus line (22) can be discontinuous at a module socket. Module bus line (15) can be configured on a front and back side of memory module (10) and electrically connected to the discontinued main board bus line (22) by contact terminals (12) configured on both sides of memory module (10). The front and back side module bus lines (15) can be electrically connected by a module bus through wiring (19′). Characteristic impedance matching between the main board and memory module (10) may be improved.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: November 26, 2002
    Assignee: NEC Corporation
    Inventor: Hiroaki Ikeda
  • Patent number: 6483709
    Abstract: The present disclosure provides a cable management solution for rack mounted computing components. In one embodiment, a backplate is preferably fixedly coupled to a rack structure. One face of the backplate is preferably operable to maintain connection with the preferred operating cables, such as, I/O devices, network, etc., which would typically couple directly to the computing component. On an opposite face of the backplate, is at least one plug operable to couple the various cable connections maintained by the backplate to at least one jack on the computing component engaged therewith. A series of alignment posts and alignment slots enable a computing component to be easily slid into and out of the rack as well as simplify engagement with and disengagement from the plug or plugs on the backplate.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: November 19, 2002
    Assignee: Dell Products L.P.
    Inventor: Jeffrey Scott Layton
  • Patent number: 6480391
    Abstract: A cage for an electronic component includes two spaced apart cast walls, and a roof member and a floor member connected to the two spaced apart cast walls. The walls are substantially identical, and the roof member and the floor member are each formed of a damped metallic laminate panel.
    Type: Grant
    Filed: January 12, 2000
    Date of Patent: November 12, 2002
    Assignee: International Business Machines Corporation
    Inventors: William Michael Monson, John Lee Colbert, Steven Dale Greseth, Mark G. Clark
  • Publication number: 20020166040
    Abstract: A computer system architecture in which functionally compatible electronic components are located on modular printed circuit boards. Thus, a type of processor used by the system can be changed by replacing the printed circuit board incorporating the processor. Similarly a type of peripheral bus used can be changed simply by replacing the printed circuit board containing the peripheral controller. High-density connectors connect the circuit boards. Some embodiments of the invention use a single backplane. Other embodiments place peripheral slots on a second, passive backplane.
    Type: Application
    Filed: March 28, 2000
    Publication date: November 7, 2002
    Inventors: Stanford W. Crane, Maria M. Portuondo, Willard Erickson, Maurice Bizzarri
  • Patent number: 6462956
    Abstract: An arrangement for a motherboard having a connector for a removable module is disclosed which increases the aggregate current carrying capacity of the connector by reducing the difference in current flow between power pins of the connector having the highest current flow and power pins of the connector having the lowest current flow. The current flow through all the power pins may then be operated nearer to the design maximum of the particular connector used. Thicker power planes within the motherboard (as well as within the module) reduce the effective resistance per square of the power plane, and help distribute the current more uniformly to a greater number of power pins of the connector. The use of multiple power planes in parallel also achieves a lower effective resistance. Multiple power terminals connecting the source of regulated power supply voltage (or reference voltage, such as ground) to the power plane may be used instead of just one power terminal.
    Type: Grant
    Filed: August 9, 2000
    Date of Patent: October 8, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dennis J. Herrell, Thomas P. Dolbear
  • Patent number: 6457978
    Abstract: A cable modern termination system (CMTS) having front and rear sides is disclosed. A rear panel receives a plurality of connector cards. At least one first connector card wherein each first connector card has a row of connectors. At least one second connector cards, wherein each second connector card has a row of connectors, wherein connectors on the first connector cards are staggered from connectors on the second connector cards when the connector cards are inserted into the rear panel.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: October 1, 2002
    Assignee: Cadent, Inc.
    Inventors: Thomas J. Cloonan, Daniel W. Hickey, Thomas J. Mack, David R. Johnson
  • Patent number: 6456495
    Abstract: A logic controller formed by self-contained device modules plugged onto a DIN rail and onto a backplane contained in the DIN rail, the modules variously comprising a power supply, a logic control, I/O devices and gateways, each I/O device having microprocessor power, and the modules having a sliding lock movable into position adjacent DIN-rail-engaging flexible tabs to block deflection of the tabs and removal of the module from the DIN rail.
    Type: Grant
    Filed: March 13, 2000
    Date of Patent: September 24, 2002
    Assignee: Eaton Corporation
    Inventors: Christopher John Wieloch, Anthony Edward Develice, Michael Thomas Little
  • Patent number: 6456498
    Abstract: A CompactPCI-based computer system including a chassis and a mid-plane board. The mid-plane board forms bus circuitry, and is positioned between a front and back of the chassis. The chassis and the mid-plane board combine to define a plurality of CompactPCI form factor slots, including front slots and back slots. At least one of the front slots and at least one of the back slots are system slots configured to receive and provide independent bus connections for respective CompactPCI form factor system processor cards. In one preferred embodiment, the mid-plane board is configured to provide a bussed connector at a first front slot and at a second back slot, and a transition connection at a first back slot and a second front slot. With this one preferred embodiment, a one- or two-unit wide system processor card can be loaded into the first front slot, and another one- or two-unit wide system processor card can be loaded into the second back slot.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: September 24, 2002
    Assignee: Hewlett-Packard Co.
    Inventors: Thane M. Larson, Kirk Bresniker
  • Patent number: 6452789
    Abstract: The inventive system uses a backplane to interconnect a plurality of modular cell boards. Each cell board comprises a plurality of processors, a processor controller chip, a memory subsystem, and a power subsystem. The processor controller chip manages communications between components on the cell board. A mechanical subassembly provides support for the cell board, as well as ventilation passages for cooling. Controller chips are connected to one side of the backplane, while the cell boards are connected to the other side. The controller chips manage cell board to cell board communications, and communications between the backplane and the computer system. The cell boards are arranged in back to back pairs, with the outer most cell boards having their components extend beyond the height of the backplane. This allows for an increase of spacing between the front to front interface of adjacent cell boards.
    Type: Grant
    Filed: April 29, 2000
    Date of Patent: September 17, 2002
    Assignee: Hewlett-Packard Company
    Inventors: Lisa Heid Pallotti, Eric C. Peterson, Christian L Belady, Terrel L. Morris, Michael C. Day
  • Patent number: 6449166
    Abstract: The present invention provides a double-sided memory module with improved memory device density and improved manufacturability, and with optional bus terminations mounted directly on the memory module for use with high speed, impedance-controlled memory buses. It also allows the same memory devices to be used on both sides of the card, instead of requiring memory devices with mirrored I/O connections on a second side as on prior art double-sided memory cards. The memory module may be formed on a conventional printed circuit card using cost-effective printed circuit board line widths and spaces with unpacked or packed memory chips attached directly to the memory module, while maintaining good signal integrity. Using memory modules with bus terminations mounted directly on the module improves the signal quality and integrity even further and therefore enhances system performance.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: September 10, 2002
    Assignee: High Connection Density, Inc.
    Inventors: Thomas R. Sly, Kevin M. Quinn
  • Patent number: 6437992
    Abstract: An insulating guard is mounted over a backplane or motherboard in an electronic system that accepts hot pluggable circuit cards. The insulating guard has openings that expose only the connectors and allow a hot pluggable circuit card to be inserted without the possibility of shorting the backplane. In order to prevent contact between a card being inserted and adjacent cards that have already been connected to the system, the invention provides for insulating card dividers which are connected to the insulating guard and fit between adjacent cards. The card dividers can be attached to the insulating guard by parts which snap together, fasteners or adhesives.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: August 20, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: James M. Carney, William A. Izzicupo, Robert S. Antonuccio, Timothy M. Holland
  • Patent number: 6437660
    Abstract: In a backplane interconnect configuration for use in a high-speed data processing system, a plurality of connector slots include an array of connector terminals. First conductive traces electrically couple at least two terminals of adjacent slots, the terminals being coupled by the first conductive traces to form multiple clusters. Each of the plurality of the clusters are in turn electrically coupled by separate conductive traces to at least one common node. This configuration allows for a reduction in the propagation delay of signals propagating between connector slots.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: August 20, 2002
    Assignee: Hybricon Corporation
    Inventor: Robert C. Sullivan
  • Patent number: 6438625
    Abstract: A computer controlled system has two or more secondary backplanes that are plugged into slots in a primary backplane. Board slots in the secondary backplanes are assigned unique addresses, and the range of addresses for each secondary backplane is contiguous with the range of addresses for a neighboring secondary backplane. Each slot in the primary backplane has one or more primary address pins. The primary address pins in the primary backplane slots are coupled so as to set the primary address pins in each primary backplane slot to a unique value. Each secondary backplane has a bus line for each primary address pin of the primary backplane slot into which it is plugged. The bus lines couple the primary address pins to board address identification pins, also called address pins, in certain of the board slots. Address pins are provided for each board slot, and are set to selected values for each board slot.
    Type: Grant
    Filed: October 21, 1999
    Date of Patent: August 20, 2002
    Assignee: Centigram Communications Corporation
    Inventor: Philip D. Olson
  • Publication number: 20020097564
    Abstract: There is disclosed a system and method for providing an improved common control bus for use in the on-line insertion of line replaceable units (such as circuit board cards) into a backplane of a processor shelf, a modem shelf, or a similar type of equipment. The present invention increases the number of device locations that a common control bus can access. The present invention comprises a complex programmable logic device on a circuit board card that is coupled to a common control bus. The complex programmable logic device is capable of selectively coupling to the common control bus each one of a plurality of device locations on the circuit board card. The complex programmable logic device controls data access to and from each device that is coupled to the common control bus.
    Type: Application
    Filed: April 20, 2001
    Publication date: July 25, 2002
    Applicant: Raze Technologies, Inc.
    Inventors: Paul F. Struhsaker, James S. Denton, Gregory L. McGee
  • Patent number: 6421251
    Abstract: The FPGA array in the Simulation system is provided on the motherboard through a particular board interconnect structure to provide easy expandability and maximize packaging density with a single PCB design. Each chip may have up to eight sets of interconnections, where the interconnections are arranged according to adjacent direct-neighbor interconnects (i.e., N[73:0], S[73:0], W[73:0], E[73:0]), and one-hope neighbor interconnects (i.e., NH[27:0], SH[27:0], XH[36:0], XH[72:37]), excluding the local bus connections, within a single board and across different boards. Each chip is capable of being interconnected directly to adjacent neighbor chips, or in one hop to a non-adjacent chip located above, below, left, and right. In the X direction (east-west), the array is connected in a torus. In the Y direction (north-south), the array is connected in a column.
    Type: Grant
    Filed: February 5, 1998
    Date of Patent: July 16, 2002
    Inventor: Sharon Sheau-Pyng Lin