Plural Contiguous Boards Patents (Class 361/792)
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Patent number: 8609998Abstract: A wiring board (package) has a structure in which multiple wiring layers are stacked one on top of another with insulating layers each interposed between corresponding two of the wiring layers, and the wiring layers are connected to one another through vias formed in each of the insulating layers. In a peripheral region of the package, reinforcing patterns are provided on the same surfaces where the corresponding wiring layers are provided, respectively. Each of the reinforcing patterns is formed of a conductive layer formed on the same surface where the corresponding one of the wiring layers is provided, and is provided in an intermittent ring-like shape when viewed in a planar view.Type: GrantFiled: January 13, 2010Date of Patent: December 17, 2013Assignee: Shinko Electric Industries Co., Ltd.Inventors: Toshiji Miyasaka, Akio Horiuchi
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Patent number: 8605448Abstract: A printed wiring board includes a bridge located in a surface layer, a noise absorber located on the bridge, a plurality of grounds directly connected or high-frequency-connected to the bridge, a first device using one of the plurality of grounds as a reference potential, a second device using one of the plurality of grounds other than the ground for the first device as a reference potential, and a high-speed signal line that connects the first device and the second device. The high-speed signal line is routed through a layer adjacent to the bridge in a layer direction of the printed wiring board to form a transmission line structure.Type: GrantFiled: March 9, 2011Date of Patent: December 10, 2013Assignee: Ricoh Company, LimitedInventors: Kenji Motohashi, Hideji Miyanishi, Kazumasa Aoki
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Patent number: 8592692Abstract: A substrate is provided that includes a plurality of substrate layers and a plural diameter via having a first via portion and a second via portion. The first via portion is formed in a first substrate layer, has a first diameter, and extends along a first axis. The second via portion is formed in a second substrate layer, has a second diameter that is different than the first diameter of the first via portion, and extends along a second axis that is offset from the first axis of the first via portion. Optionally, the first via portion and the second via portion may have a common edge that is spaced the same distance from an edge of another via extending through the substrate.Type: GrantFiled: July 22, 2011Date of Patent: November 26, 2013Assignee: Tyco Electronics CorporationInventors: Alex Michael Sharf, Jie Qin
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Patent number: 8586873Abstract: A circuit board includes a pair of differential signal lines and a pair of test point pads, one test point pad coupled to one of the signal lines and another of the test point pads coupled to another of the signal lines. The two test point pads are staggered relative to each other and the two signal lines. The circuit board includes a plurality of conductive layers and a plurality of insulating layers. The conductive layers can be etched into conductive patterns, or traces, for connecting the electronic components, which are soldered to the circuit board. The conductive layers may be selectively connected together by vias. One or more of the conductive layers may be a metal plane for providing a ground plane and/or a power plane. To minimize or eliminate the capacitance generated between the test point pad and an underlying ground plane and/or power plane, portions of the ground plane and/or the portion of the power plane directly aligned with each test point pad are removed.Type: GrantFiled: February 23, 2010Date of Patent: November 19, 2013Assignee: Flextronics AP, LLCInventor: Leon Wu
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Patent number: 8582312Abstract: A highly reliable electronic circuit board for suppressing propagation of noise and a power line communication apparatus using it are provided. An electronic circuit board of the invention is connected to a different electronic circuit board and including a first board having a first face and a second face opposed to the first face and a second board having a third face and a fourth face opposed to the third face.Type: GrantFiled: March 24, 2009Date of Patent: November 12, 2013Assignee: Panasonic CorporationInventors: Hiroshi Kawano, Shuichiro Yamaguchi, Takumi Naruse, Toshihiro Yamauchi
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Patent number: 8563868Abstract: An electronic device (100) includes a first plane (102) and a second plane (103) where one of the planes can be deformed under mechanical pressure. A common contact region forms a cavity (145) on at least one of the first and second planes. An electrical connection (110) is configured to complete an electrical connection between the first and second planes wherein the electrical connection includes a solidified form of a liquid conductor dispensed in the cavity to complete an electrical path between the first and second planes.Type: GrantFiled: June 28, 2007Date of Patent: October 22, 2013Assignee: Creator Technology B.V.Inventors: Fredericus J. Touwslager, Gerwin Gelinck, Petrus Cornelis Paulus Bouten
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Patent number: 8564970Abstract: This invention discloses a display device mother substrate, a display device substrate and a manufacture method of display device substrate thereof. The display device mother substrate includes a first substrate, a second substrate, a first active area circuit and a first transmission line, wherein a first cutting line is defined between the first substrate and the second substrate. The first active area circuit is disposed on the first substrate and is electrically connected to the first transmission line. The first transmission line includes a display line portion, an end line portion and a middle line portion, wherein the display line portion is electrically connected to the first active area circuit. The middle line portion is disposed on the second substrate, wherein two ends of the middle line portion are electrically connected to the display line portion and the end line portion respectively at the first cutting line.Type: GrantFiled: March 12, 2010Date of Patent: October 22, 2013Assignee: AU Optronics CorporationInventors: Hung-Kun Chen, Chi-Chin Lin
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Patent number: 8552312Abstract: A printed wiring board including a substrate having first and second surfaces and a penetrating hole extending through the substrate between the surfaces, a first conductive circuit on the first surface, a second conductive circuit on the second surface, and a through-hole conductor in the hole and connecting the first and second conductive circuits. The conductor includes an electroless plated film on the inner-wall surface of the hole, a first electrolytic plated film formed on the electroless plated film and forming a first opening portion opening on the first surface and a second opening portion opening on the second surface, a second electrolytic plated film filling the first portion, and a third electrolytic plated film filling the second portion. The first and second portions taper toward the central portion of the hole with respect to the axis direction of the hole and have cross sections forming a substantially U-shape, respectively.Type: GrantFiled: November 12, 2010Date of Patent: October 8, 2013Assignee: Ibiden Co., Ltd.Inventors: Satoru Kawai, Yasuki Kimishima
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Patent number: 8552310Abstract: A mounting structure of an electronic component includes: a bump electrode included in the electronic component, the bump electrode having an internal resin as a core and a conductive film covering a surface of the internal resin, and elastically deforming so as to follow a shape of at least one corner of a terminal so that the conductive film makes direct conductive contact with at least part of a top surface of the terminal and at least part of a surface along a thickness direction of the terminal; a substrate having the terminal and the electronic component that is mounted on the substrate; and a holding unit provided to the substrate and the electronic component so as to hold a state in which the bump electrode electrically deformed makes conductive contact with the terminal.Type: GrantFiled: January 9, 2012Date of Patent: October 8, 2013Assignee: Seiko Epson CorporationInventor: Nobuaki Hashimoto
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Patent number: 8553387Abstract: This invention provides an electronic device including a casing and a circuit board. The casing has an opening. The circuit board is located in the casing and at least includes a conductive layer and a surface insulating layer. The conductive layer includes a signal transmission portion and a static induction portion. The static induction portion is electrically disconnected with the signal transmission portion at the conductive layer, and the static induction portion is closer to the opening than the signal transmission portion. The surface insulating layer covers the signal transmission portion on the circuit board and exposes the static induction portion.Type: GrantFiled: March 7, 2011Date of Patent: October 8, 2013Assignee: PegatronInventors: Ching-Jen Wang, Fang-Teng Chung, Wen-Hsieh Hsieh
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Patent number: 8553427Abstract: A motherboard includes a first circuit board, a second circuit board, and wiring. The first circuit board includes at least a programmable chip, a programming interface, a first data interface, and at least one jumper corresponding to the programmable chip. The second circuit board includes a CPU (central processing unit), a RAM unit, and at least a second data interface corresponding to the programmable chip. The motherboard of the present disclosure concentrates programmable chips on the first circuit board, thereby providing a unified programming interface to enhance the convenience of programming multiple programmable chips.Type: GrantFiled: March 28, 2011Date of Patent: October 8, 2013Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Meng-Zhou Liu, Wen-Wu Wu
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Patent number: 8546700Abstract: A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.Type: GrantFiled: March 8, 2011Date of Patent: October 1, 2013Assignee: NGK Spark Plug Co., Ltd.Inventors: Hiroshi Yamamoto, Toshitake Seki, Shinji Yuri, Masaki Muramatsu, Motohiko Sato, Kazuhiro Hayashi, Jun Otsuka, Manabu Sato
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Patent number: 8541884Abstract: A TSV structure suitable for high speed signal transmission includes a metal strip portion that extends through a long and small diameter hole in a substrate. In one example, the metal strip portion is formed by laser ablating away portions of a metal sheath that lines a cylindrical sidewall of the hole, thereby leaving a longitudinal section of metal that is the metal strip portion. A second metal strip portion, that extends in a direction perpendicular to the hole axis, is contiguous with the metal strip portion that extends through the hole such that the two metal strip portions together form a single metal strip. Throughout its length, the single metal strip has a uniform width and thickness and therefore can have a controlled and uniform impedance. In some embodiments, multiple metal strips pass through the same TSV hole. In some embodiments, the structure is a coaxial TSV.Type: GrantFiled: June 28, 2012Date of Patent: September 24, 2013Assignee: Research Triangle InstituteInventors: Robert O. Conn, David F. Myers, Daniel S. Stevenson
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Patent number: 8536462Abstract: A flex circuit package includes a package body enclosing an electronic component and a first surface of the substrate. Columns are physically and electrically connected to first traces of the substrate, the columns extending through the package body. A flexible circuit connector has first terminals connected to the columns. The flexible circuit connector further includes second terminals that provide an electrical interconnection structure for electrical connection to a second electronic component structure. By connecting the flexible circuit connector to the columns extending through the package body, special routing of traces of the substrate of the flex circuit package to provide an interface for the flexible circuit connector is avoided.Type: GrantFiled: January 22, 2010Date of Patent: September 17, 2013Assignee: Amkor Technology, Inc.Inventors: Robert Francis Darveaux, Ludovico E. Bancod, Marnie Ann Mattei, Timothy Lee Olson
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Patent number: 8526192Abstract: A boss for securing a pair of mainboards includes a circular top and a plurality of first flexible legs. The first flexible legs are disposed on one side of the circular top and are separated from each other. Each of the first flexible legs includes a tilted wall and a pressing component. The tilted wall is formed on a surface of the first flexible leg that faces another first flexible leg. The pressing component is formed on one end of the first flexible leg away from the circular top. The tilted walls of all the first flexible legs cooperatively define a tapered channel. The tapered channel can be expanded.Type: GrantFiled: January 16, 2012Date of Patent: September 3, 2013Assignee: Inventec CorporationInventors: Pin-Cheng Chen, Te-Cheng Lee, Hung-Pin Lin, Yao-Yu Lai, Cheng-Hsin Chen
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Patent number: 8523391Abstract: A flat light source apparatus has a light source board which comprises unit boards, each unit board having a printed circuit board and a light source formed on the printed circuit board, wherein the unit boards are arranged adjacent to each other at least in one direction, and any pair of the unit boards adjacent to each other is integrated by a connecting portion provided therebetween. The apparatus also has a main wire which extends along a plane of the light source board, wherein the main wire extends between adjacent unit boards via the connecting portion such that all of the unit boards are electrically connected to each other by the main wire. The apparatus further has a branch wire for supplying electric power to the light source, the branch wire being provided in each unit board and branching from the main wire in each unit board.Type: GrantFiled: February 3, 2006Date of Patent: September 3, 2013Assignee: NEC CorporationInventors: Masahiro Ishizuka, Katsuyuki Okimura, Yoshinori Ueji, Ryuichiro Morinaka, Naoki Tatsumi, Tomoyuki Fukuda
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Patent number: 8520401Abstract: A motherboard assembly includes a motherboard and a serial advanced technology attachment dual-in-line memory module (SATA DIMM) module with a circuit board. The motherboard includes an expansion slot and a storage device interface. An edge connector is set on a bottom edge of the circuit board to be detachably engaged in the expansion slot, and a notch is set on a bottom edge of the circuit board to engage in a protrusion of the expansion slot. A SATA connector of the circuit board is connected to the storage device interface of the motherboard.Type: GrantFiled: August 31, 2011Date of Patent: August 27, 2013Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Bo Tian, Guo-Yi Chen
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Patent number: 8513533Abstract: A multilayer stacked circuit arrangement with localized separation section, has a first flat cable and first signal transmission lines arranged on the first flat cable. A second flat cable is stacked on and bonded to the first flat cable. The second flat cable further has signal transmission lines arranged on it. A bonding substance layer is formed between a first non-separation section of the first flat cable and a second non-separation section of the second flat cable for properly stacking the first and second flat cables where the separation sections are spaced apart from each other. A conductive via extends between the first non-separation section and the second non-separation section. At least some of the second signal transmission lines of the second flat cable are connected through the conductive via to the first signal transmission lines of the first flat cable.Type: GrantFiled: September 6, 2011Date of Patent: August 20, 2013Assignee: Advanced Flexible Circuits Co., Ltd.Inventors: Gwun-Jin Lin, Kuo-Fu Su, Chih-Heng Chuo
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Patent number: 8508954Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.Type: GrantFiled: October 22, 2010Date of Patent: August 13, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Heung-Kyu Kwon, Min-Ok Na, Sung-Woo Park, Ji-Hyun Park, Su-Min Park
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Patent number: 8502085Abstract: A multi-layer substrate includes a plurality of substrate main bodies, a plurality of layers which are alternately layered with the main bodies, a signal via hole which is connected with a signal line and includes a signal column which passes through at least one substrate main body; and a sub via hole which includes a sub column which surrounds the signal column, and a pair of sub pads which extend from end parts of the sub column to be formed to the layers, the layers which are formed with the sub pads being disposed in the same layer as the layers which are formed with the signal line of the signal via hole, or being disposed outside the layers which are formed with the signal line which is connected with the signal via hole.Type: GrantFiled: September 14, 2007Date of Patent: August 6, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Young-seok Kim
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Patent number: 8493747Abstract: A flex-rigid wiring board including an insulative substrate, a flexible wiring board positioned beside the insulative substrate, an insulation layer positioned over the insulative substrate and the flexible wiring board and exposing a portion of the flexible wiring board, and a wiring layer made of a conductor and formed on the insulation layer. The insulation layer has a tapered portion which becomes thinner toward an end surface of the insulation layer in the direction of the portion of the flexible wiring board exposed by the insulation layer. The wiring layer has a sloping portion formed on the tapered portion of the insulation layer.Type: GrantFiled: November 18, 2010Date of Patent: July 23, 2013Assignee: Ibiden Co., Ltd.Inventors: Nobuyuki Naganuma, Michimasa Takahashi, Masakazu Aoyama
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Patent number: 8467194Abstract: An AC adapter including an electronic device, a first circuit board on which the electronic device is mounted, a second circuit board separated from the first circuit board, a connector mounted on the second circuit board and electrically connected to the second circuit board, first and second metal wirings that electrically connect the first and the second circuit boards, and an insulation case installing the first circuit board, the electronic device, the second circuit board, and the connector therein and including a projecting part interposed between the first and second metal wirings.Type: GrantFiled: February 15, 2011Date of Patent: June 18, 2013Assignee: Mitsumi Electric Co., Ltd.Inventors: Dai Sasaki, Taisuke Koga
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Patent number: 8456857Abstract: A backplane arrangement is provided for an electronic mounting rack with a base backplane with several contact strips, wherein a free space, into which at least one additional backplane can be inserted, is provided on the base backplane.Type: GrantFiled: March 21, 2007Date of Patent: June 4, 2013Assignee: ADVA Optical Networking SEInventors: Uwe Gröschner, Falk Steiner, Stefan Asch
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Patent number: 8456855Abstract: A printed circuit board includes a first to a fifth connector pads, a first to an eighth coupling capacitor pads, a first to a tenth transmission lines, a first via and a second via, a first to a fourth sharing pads, and a voltage converting circuit. The printed circuit board is operable to selectively support different types of connectors.Type: GrantFiled: August 18, 2011Date of Patent: June 4, 2013Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Yung-Chieh Chen, Duen-Yi Ho, Shou-Kuo Hsu
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Patent number: 8450615Abstract: A ceramic multilayer substrate in which cracks resulting from the difference in shrinkage caused by heat or thermal shrinkage caused by firing can be prevented effectively between an end surface electrode and a substrate main body. The substrate main body includes alternately stacked first and second ceramic layers, and including first recesses provided in end surfaces of at least two adjacent ceramic layers so as to communicate with each other, and an electroconductive end surface electrode is disposed in the first recesses in the substrate main body. The first and the second ceramic layer each have a sintering start temperature and a sintering end temperature, and at least one of the sintering start temperature and the sintering end temperature is different between the first and the second ceramic layer. The substrate main body has a second recess in at least one of the ceramic layers having the first recesses so as to communicate with the first recess and lie between other ceramic layers.Type: GrantFiled: February 26, 2010Date of Patent: May 28, 2013Assignee: Murata Manufacturing Co., Ltd.Inventor: Masato Nomiya
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Patent number: 8446738Abstract: A system, method, and motherboard assembly are described for interconnecting and distributing signals and power between co-planar boards that function as a single motherboard. The motherboard assembly includes a multilayered first printed circuit board having opposed parallel first and second surfaces, each having at least one land grid array (LGA) disposed thereon. The assembly further includes at least one wiring layer (Y) designed to only electrically interconnect components on or within the first PCB, and at least one wiring layer (X) designed to only electrically connect the components on the first PCB to a multilayered second PCB. The multilayered second PCB has opposed parallel first and second surfaces, the first surface having at least one LGA disposed thereon.Type: GrantFiled: October 14, 2009Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: John L. Colbert, Arvind K. Sinha, Roger D. Weekly
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Patent number: 8440916Abstract: A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof and the second supplemental patterned conductive layer at another side thereof.Type: GrantFiled: June 28, 2007Date of Patent: May 14, 2013Assignee: Intel CorporationInventors: Yonggang Li, Islam Salama, Charan Gurumurthy, Hamid Azimi
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Patent number: 8432706Abstract: A printed circuit board and an electronic product are disclosed. In accordance with an embodiment of the present invention, the printed circuit board includes a first board, which has an electronic component mounted thereon, and a second board, which is positioned on an upper side of the first board and covers at least a portion of an upper surface of the first board and in which an EBG structure is inserted into the second board such that a noise radiating upwards from the first board is shielded. Thus, the printed circuit board can readily absorb various frequencies, be easily applied without any antenna effect and be cost-effective in manufacturing.Type: GrantFiled: December 22, 2009Date of Patent: April 30, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Han Kim, Chang-Sup Ryu
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Publication number: 20130100628Abstract: An electronic device having a press-fit connection for connecting a connector and an electronic part mounted on a printed circuit board which is possible to enable high density mounting. Viewing the printed circuit board from an upper surface, between adjacent through holes on which a compressive force acts upon insertion of the press-fit terminal, among the large number of through holes, a land or a conductor film connected to the conductor film formed on the inner wall surface of the through hole or the conductor film not connected to the conductor film formed on the inner wall surface of the through hole, formed in the circuit board held between the top layer circuit board and the bottom layer circuit board, exists in a width equal to or wider than the diameter of the through hole.Type: ApplicationFiled: October 18, 2012Publication date: April 25, 2013Inventor: Hitachi Automotive Systems, Ltd.
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Patent number: 8416577Abstract: The present invention relates to a coreless substrate and a method for making the same. The method for making the coreless substrate includes: (a) providing a carrier and a first conductive layer, wherein the carrier has a first surface and a second surface, and the first conductive layer is disposed on the first surface of the carrier; (b) forming a first embedded circuit on the first conductive layer; (c) forming a first dielectric layer so as to cover the first embedded circuit; (d) removing the carrier; (e) removing part of the first conductive layer so as to form at least one first pad; and (f) forming a first solder mask so as to cover the first embedded circuit and the first dielectric layer and to expose the first pad. Therefore, the coreless substrate of the present invention has high density of layout and involves low manufacturing cost.Type: GrantFiled: January 21, 2010Date of Patent: April 9, 2013Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Hao Wang, Ming-Chiang Lee
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Patent number: 8411460Abstract: A printed circuit board includes a power layer, a ground layer, a signal layer, and a backboard. The backboard is arranged below the signal layer opposite to the ground layer. A number of vias are formed from the backboard through the signal layer, and then connected to the ground layer.Type: GrantFiled: September 23, 2010Date of Patent: April 2, 2013Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Guang-Feng Ou, Yong-Zhao Huang
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Patent number: 8404981Abstract: A process of copper plating a through-hole in a printed circuit board, and the printed circuit board made from such process. The process comprises: providing a printed circuit board with at least two copper interconnect lines separated by an insulator in the vertical direction; providing a through-hole in the printed circuit board in the vertical direction such that the interconnect lines provide a copper land in the through-hole; applying a seed layer to an interior surface of the through-hole; removing an outermost portion of the seed layer from the interior surface of the through-hole with a laser; applying copper on the seed layer.Type: GrantFiled: July 21, 2008Date of Patent: March 26, 2013Assignee: International Business Machines CorporationInventors: Stephen L. Buchwalter, Russell Alan Budd
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Patent number: 8400782Abstract: A wiring board has a first rigid wiring board having an accommodation section, a second rigid wiring board to be accommodated in the accommodation section, and an insulation layer formed on the first rigid wiring board and the second rigid wiring board. Here, a conductor of the first rigid wiring board and a conductor of the second rigid wiring board are electrically connected to each other, and at least either a side surface of the second rigid wiring board or a wall surface of the accommodation section has a concave-convex portion.Type: GrantFiled: January 27, 2010Date of Patent: March 19, 2013Assignee: Ibiden Co., Ltd.Inventors: Masakazu Aoyama, Hidetoshi Noguchi
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Patent number: 8395906Abstract: A high-speed transmission circuit board connection structure includes a first high-speed transmission circuit board including a laminated substrate including a first signal transmission wiring formed on a surface thereof and a ground plane formed inside thereof, a second high-speed transmission circuit board including a circuit substrate and a second signal transmission wiring formed on a surface of the circuit substrate, a conductive board connecting member for fixing the first and second high-speed transmission circuit boards to a surface thereof, and a bonding wire for electrically connecting the first signal transmission wiring and the second signal transmission wiring. The ground plane is exposed on a side end face of the laminated substrate, and a conductive film is formed on the side end face such that the ground plane of the first high-speed transmission circuit board is electrically connected to the board connecting member with the conductive film.Type: GrantFiled: June 1, 2010Date of Patent: March 12, 2013Assignee: Hitachi Cable, Ltd.Inventors: Masayuki Nikaido, Yoshiaki Ishigami, Kenichi Tamura, Takehiko Tokoro
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Patent number: 8395053Abstract: A circuit system comprising: forming a lower electrode over a substrate; forming a resistive film over the lower electrode; forming a multi-layered insulating stack over a portion of the resistive film; and forming an upper electrode over a portion of the multi-layered insulating stack.Type: GrantFiled: June 27, 2007Date of Patent: March 12, 2013Assignee: Stats Chippac Ltd.Inventors: Yaojian Lin, Haijing Cao, Qing Zhang
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Patent number: 8391018Abstract: An electronic system includes a system board and a packaging substrate mounted on the system board. One or more semiconductor dies are mounted on the packaging substrate and coupled to the system board. The system also includes one or more semiconductor die-based packaging interconnects between the system board and the packaging substrate. The semiconductor die-based packaging interconnect has a first face coupled to the system board and a second face coupled to the packaging substrate. Through silicon vias located in the semiconductor die-based packaging interconnect enable communication between the system board and the one or more semiconductor dies. The semiconductor die-based packaging interconnects may include passive devices, active devices, and/or circuitry. For example, the semiconductor die-based packaging interconnect may provide impedance matching, decoupling capacitance, and/or amplifiers for minimizing insertion loss.Type: GrantFiled: September 28, 2009Date of Patent: March 5, 2013Assignee: QUALCOMM IncorporatedInventors: Arvind Chandrasekaran, Jonghae Kim
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Patent number: 8391022Abstract: A mezzanine board alignment and mounting device includes a multi-stage pin connected to a main board near a mezzanine board connector disposed on the main board. The multistage pin includes a base adapted to connect to the main board, a point distal to the base adapted to pass through an opening on a mezzanine board, and a support disposed between the base and the point. A diameter of the point widens towards the support. A diameter of the support is wider than a diameter of the opening. When the point is fully inserted through the opening in the mezzanine board, the mezzanine board is aligned properly to connect with the mezzanine board connector on the main board.Type: GrantFiled: March 6, 2008Date of Patent: March 5, 2013Assignee: Oracle America, Inc.Inventors: Timothy W. Olesiewicz, David W. Hartwell, Brett C. Ong
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Patent number: 8385081Abstract: A stacked mounting structure includes a first substrate which includes a first electronic component, a second substrate disposed facing the first substrate and including a second electronic component, an intermediate member having a space for accommodating the second electronic component, an electroconductive member provided to the intermediate member, a first electrode for testing electrically connected to the first electronic component, as an electrode for testing an operation of the first electronic component, a connecting electrode toward the second substrate electrically connected to the second electronic component, as an electrode for electrically connecting to the electroconductive member, and a second electrode for testing provided to the first substrate as an electrode for testing an operation of the second electronic component and electrically connected to the second electronic component via the electroconductive member and the connecting electrode toward the second substrate.Type: GrantFiled: July 21, 2010Date of Patent: February 26, 2013Assignee: Olympus CorporationInventor: Hiroyuki Motohara
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Patent number: 8383955Abstract: A printed circuit board (PCB) includes first to fourth layers. A power supply is arranged on the first layer. An electronic component is arranged on the fourth layer. A first via and a second via extend through the PCB and are electrically connected to the electronic component. The PCB further includes third to seventh vias. A length of a transmission path of the current flows from the power supply to electronic component through the third via and the seventh via is almost the same as a length of a transmission path of the current flows from the power supply to the electronic component through the fourth to sixth vias.Type: GrantFiled: April 29, 2011Date of Patent: February 26, 2013Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Tsung-Sheng Huang, Chun-Jen Chen, Duen-Yi Ho, Wei-Chieh Chou
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Patent number: 8378229Abstract: A circuit board includes a substrate made principally of metal. An opening is provided on the substrate. A first wiring layer is provided on one surface of the substrate via a first insulating layer, and a second wiring layer is provided on the other surface of the substrate via a second insulating layer. A conductor penetrates the substrate via the opening and connects the first wiring layer with the second wiring layer. An end of the opening at one surface side of the substrate has a tapering form on a surface layer thereof, and the first insulating layer has a recess on an upper surface thereof in an upper region of the opening.Type: GrantFiled: June 11, 2010Date of Patent: February 19, 2013Assignee: Sanyo Electric Co., Ltd.Inventors: Mayumi Nakasato, Hideki Mizuhara
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Patent number: 8379400Abstract: An interposer mounted wiring board includes a wiring board including outermost wiring layers respectively on both surfaces thereof, the outermost wiring layers being electrically connected to each other through an inside of the board, and first and second interposers electrically connected to the outermost wiring layers on the both surfaces of the board, respectively. Each of the first and second interposers has a value of a coefficient of thermal expansion (CTE), the value being equal or close to a value of a CTE of a corresponding one of first and second electronic components to be mounted respectively on the first and second interposers. The base member of each of the interposers is preferably formed of silicon, and the base member of the wiring board is preferably formed of resin. Further, the electronic components are mounted respectively on surfaces of the interposers and thus form a semiconductor device, the surfaces being opposite to the surfaces of the interposers facing the wiring board.Type: GrantFiled: October 4, 2010Date of Patent: February 19, 2013Assignee: Shinko Electric Industries Co., Ltd.Inventor: Masahiro Sunohara
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Patent number: 8357859Abstract: Disclosed is an insulating resin sheet laminate (an insulating resin sheet with a film or a metal foil) including an insulating resin layer with a uniform thickness that is formed without repulsion or unevenness in a process of forming the insulating resin layer on a film or a metal foil, and a multi-layer printed circuit board that includes the insulating resin sheet laminate and possesses high insulating reliability. The present invention provides an insulating resin sheet laminate (an insulating resin sheet with a film or a metal foil) obtained by forming an insulating resin layer made of a resin composition on a film or a metal foil, and the resin composition includes an acrylic surfactant.Type: GrantFiled: January 16, 2008Date of Patent: January 22, 2013Assignee: Sumitomo Bakelite Co., Ltd.Inventors: Hiroaki Wakabayashi, Noriyuki Ohigashi
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Patent number: 8358510Abstract: A power distribution apparatus includes an outlet board, a fuse board, and at least one connector. The outlet board is connected to the fuse board through the at least one connector.Type: GrantFiled: September 3, 2010Date of Patent: January 22, 2013Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Yang-Yuan Chen, Heng-Chen Kuo
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Patent number: 8351216Abstract: The present invention relates to a layered structure assembly (1) for a DC to AC inverter comprising: a first layered structure (10) with first (12) and second (13) conductive layers, a second layered structure (14) with third (16) and fourth (17) conductive layers, and at least one connector (21) providing a low resistance/inductance interconnection between layered structures (10, 14), the connecter (21) comprising a rod (23) inside a sleeve (26).Type: GrantFiled: June 10, 2008Date of Patent: January 8, 2013Assignee: Power Concepts NZ LimitedInventor: Christopher William Fotherby
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Patent number: 8350161Abstract: According to one of the invention, a circuit board comprises a conductive layer. The conductive layer includes a first land portion, a second land portion apart from the first land portion in a plan view, and a line portion connecting the first land portion and the second land portion to each other. The line portion includes lead portions through which a current is to flow and an opening portion arranged between the lead portions. The opening portion penetrates the conductive layer in a thickness direction.Type: GrantFiled: January 29, 2010Date of Patent: January 8, 2013Assignee: Kycera CorporationInventors: Kimihiro Yamanaka, Manabu Ichinose, Satoshi Nakamura
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Patent number: 8345439Abstract: A modular packet network device has a chassis in which multiple logic cards mate to the front side of an electrical signaling backplane. Logic power for the logic cards is supplied from a group of power converter cards that convert primary power to the logic voltages required by the logic cards. The power converter cards lie in a separate cooling path behind the backplane. Advantages achieved in at least some of the embodiments include removing primary power planes from the signaling backplane or portion of the backplane, providing redundant, upgradeable power modules whose individual failure does not cause logic card failure, and providing cool air to power converter circuits that would be subject to only heated air if located on the logic cards. Other embodiments are also described and claimed.Type: GrantFiled: November 18, 2008Date of Patent: January 1, 2013Assignee: Force10 Networks, Inc.Inventors: Joel R. Goergen, Donald Lewis
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Patent number: 8345433Abstract: Organic laminate stack ups are disclosed for a variety of applications, including high frequency RF applications. One or more inner core layers may be disposed between outer layers along with bondply or prepreg layers as needed. Discrete devices, including surface mount components and flip chips, may be embedded within the organic laminate stack up structures. The embedding of the discrete devices, which may be active or passive devices, may be in the form of a layer of bondply or prepreg encapsulating the discrete devices. In addition or in the alternative, cavities may be formed in at least the outer layers for housing discrete devices, which include surface mount components, flip chips, and wire bonded integrated circuits. A variety of caps may be utilized to seal the cavities. Further, shielding may be provided for the organic laminate stack up structure, including through a wall of vias or a plated trench cut along at least one side of the stack up structure.Type: GrantFiled: July 8, 2005Date of Patent: January 1, 2013Assignee: AVX CorporationInventors: George E. White, Sidharth Dalmia, Venkatesh Sundaram, Madhavan Swaminathan
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Patent number: 8345437Abstract: A connection structure for connecting a wiring board to a to-be-connected body having electric contacts, the wiring board including: a base having board-side contacts provided on its facing surface that is to face the to-be-connected body; and a cover film which covers the facing surface except the board-side contacts and a non-covered partial region of the facing surface, the connection structure including: conduction portions formed of electrically conductive resin, for bonding the electric contacts and the board-side contacts to permit electrical conduction therebetween; and a reinforcement portion formed of the same resin as the conduction portions and disposed at a position which is different from positions of the conductive portions and at which the reinforcement portion extends across both of a surface of the cover film and a surface of the non-covered partial region of the base, the reinforcement portion bonding the to-be-connected body and the wiring board for reinforcing connection therebetween.Type: GrantFiled: March 28, 2011Date of Patent: January 1, 2013Assignee: Brother Kogyo Kabushiki KaishaInventors: Tomoyuki Kubo, Yuji Shinkai
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Patent number: 8334466Abstract: A multilayer printed wiring board including a core substrate, a built-up wiring layer having a first surface in contact with the substrate and a second surface, the second surface including a mounting area for mounting a semiconductor device, the built-up layer including circuits and insulating layers, first through-hole conductors formed in a first portion of the substrate which corresponds to the mounting area, second through-hole conductors formed in a second portion of the substrate which corresponds to an area of the second surface other than the mounting area, third through-hole conductors formed in a processor core area of the first portion of the substrate which corresponds to a processor core section of the device, and pads provided on the second surface. The first conductors have a pitch smaller than a pitch of the second conductors, and the third conductors have a pitch smaller than the pitch of the first conductors.Type: GrantFiled: July 23, 2010Date of Patent: December 18, 2012Assignee: Ibiden Co., Ltd.Inventor: Takashi Kariya
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Patent number: 8330051Abstract: A multi-layer circuit board, a method of manufacturing the same, and a communication device are provided. As for the multi-layer circuit board, a slot segment is opened on at least one daughter board to form a first daughter board. At least one daughter board and medium layers are stacked together. The daughter boards include first daughter boards. The first daughter boards are placed in such a way that the slot segments of the first daughter boards are communicated. The slot segments are communicated to form a receiving slot. A heat conducting block is placed within the receiving slot. Each medium layer is sandwiched between the daughter boards. The stacked daughter boards, medium layers, and heat conducting block are pressed together, and the pressed daughter boards and heat conducting block are made into a multi-layer circuit board. The heat conducting block is embedded when the circuit board is pressed, thereby simplifying the assembling process of the heat conducting block.Type: GrantFiled: April 26, 2010Date of Patent: December 11, 2012Assignee: Huawei Technologies Co., Ltd.Inventors: Mingli Huang, Shun Zhang, Xichen Yang, Junying Zhao, Bing Luo, Zhihai Li