Abstract: A printed circuit board having a dielectric layer is disclosed. At least one signal trace is disposed adjacent a first surface of the dielectric layer in a first signal area. A reference plane is disposed adjacent a second surface of the dielectric layer in a first reference area positioned opposite the first signal area. The reference plane is configured to carry a reference potential for signals on the signal trace. At least one other signal trace is disposed adjacent the second surface of the dielectric layer in a second signal area and coupled to the signal trace in said first signal area. A second reference plane is disposed adjacent the first surface of the first dielectric layer in a second reference area positioned opposite the second signal area. The second reference plane is configured to carry the reference potential for signals on the other signal trace.

Abstract: An electronic device has a plurality of capacitors in an ultra-small integrated package. The device has a plurality of terminal structures on one terminal side of the package to permit inverted mounting to a printed circuit board. The terminals are widely spaced, with the individual capacitors being located entirely in between. The device is produced on a suitable substrate using thin film manufacturing techniques. A lead-based dielectric having a high dielectric constant is preferably utilized for each capacitor to provide a relatively high-capacitance value in a relatively small plate area.

Abstract: An integrated circuit substrate having embedded wire conductors provides high-density interconnect structure for integrated circuits. Wires are shaped to form a conductive pattern and placed atop a dielectric substrate layer. Additional dielectric is electro-deposited over the wires to form an insulating layer that encapsulates the wires. One or more power planes may be embedded within the substrate and wires within the conductive pattern may be laser-welded to vertical wire stubs previously attached to a power plane. Vias may be formed by mechanically or laser drilling (or plasma or chemical etching) through any power planes and screening a copper paste into the drilled holes to form conductive paths through the holes. Via conductors may then be exposed by a plasma operation that removes dielectric, leaving the ends of the via conductors exposed. Wires within the conductive pattern may then be laser-welded to the via conductor ends.

Abstract: An interconnection substrate comprises an uppermost interconnection layer having a plurality of terminal pads located at positions corresponding to a plurality of solder bumps (external connection terminals) provided on a semiconductor element which is to be mounted on the interconnection substrate. The interconnection substrate also has a metal column formed on each of the terminal pads and has a resin film covering a side surface of the metal column. The interconnection substrate further has an insulating layer formed on the uppermost interconnection layer so that a gap is formed between the insulating layer and an outer peripheral surface of the resin film.

Abstract: A multilayered PCB including two multilayered portions, one of these able to electrically connect electronic components mounted on the PCB to assure high frequency connections therebetween. The PCB further includes a conventional PCB portion to reduce costs while assuring a structure having a satisfactory overall thickness for use in the PCB field. Coupling is also possible to the internal portion from these components. Methods of making these structures have also been provided.

Abstract: A high-speed router backplane is disclosed. Because of the large number of high-speed conductive traces present in such a backplane, electromagnetic interference (EMI) can be a serious issue. And because such a router consumes significant amounts of power, some provision must exist (e.g., bus bars in the prior art) within the router for distributing power to the router components. In preferred embodiments, power distribution is accomplished using relatively thick (e.g., three- or four-ounce copper) power distribution planes within the same backplane used for high-speed signaling. To shield these planes from EMI, they are preferably placed near the center of the material stack, shielded from the signaling layers by adjacent digital ground planes. Also, where two power supply planes exist, the power supply planes are placed adjacent, further shielded by their respective power return planes.

Abstract: An apparatus and method that permits signal traces of different widths and the same impedance to be placed on the same layer of a printed circuit board (PCB). Alternatively, signal traces of different impedances but the same width may be placed on the same layer of the PCB. Ground and power planes are paired on adjacent layers of the PCB with a portion of the power plane relative to the ground plane removed. Signal traces of the same width and different impedances or vice-versa can be placed on the same layer because each signal trace is referenced to different planes.

Abstract: A layer allocating apparatus for a multi-layer circuit board is disclosed. In a preferred embodiment, the layer allocating apparatus arranged from top to bottom as a component layer, a ground layer, a power layer, and a solder layer. The powerlayer is sliced into a plurality of reference ground areas each is located at somewhere to correspond to signal layout areas of the solder layer, so as to allow signal lines of the component layer and solder layer to take reference to the reference ground areas on the adjacent power layer. The power layer also includes a plurality of power layers each provides different operating voltages, and electrically couples with corresponding power layouts of the solder layer and component layer through vias, thereby enlarging the total area of power planes, so as to provide a table power source and attenuate the ground/bounce effect.

Abstract: A multilayer printed wiring board of the present invention includes, e.g., an electrical insulating layer, a plurality of wiring layers arranged alternately with the electrical insulating layer, and a plurality of conductors passing through the electrical insulating layer in its thickness direction for electrically connecting the wiring layers. A plating layer is formed so as to cover the side of the electrical insulating layer and electrically connected to ground wiring. The impedance of a signal transmission conductor arranged in the edge portion of the electrical insulating layer is controlled by a ground conductor arranged opposite to the plating layer with this signal transmission conductor sandwiched between them and the plating layer.

Abstract: A multilayer PCB has first and second signal transmission lines and first and second ground layers. A signal via is connected between the first and second transmission lines. Ground vias extending parallel to the signal via are connected between the first and second ground layers. The end of the first ground layer protrudes with respect to the second ground layer and extends nearer to the signal via than the second ground layer. Thus, it is possible to stabilize the characteristic impedance of the first transmission line.

Abstract: A connector, particularly suited for use in a digital camera, having electrostatic discharge features that prevent the occurrence of electrostatic discharge events. The connector comprises a printed circuit board that includes a ground contact, a power contact, and a plurality of signal contacts that are offset from an edge of the printed circuit board. A row of vias are disposed between the signal contacts and the edge of the printed circuit board, and adjacent opposite sides of each of the signal contacts, that attract electrostatic energy before it can reach the signal contacts. The signal contacts have different lengths and shapes, depending upon their purpose. An electrostatic discharge protection method and digital camera are also disclosed.

Abstract: A multi-layered printed wiring board capable of securing required wiring density even with a decreased number of wiring layers and reducing radiation noises. The multi-layered printed wiring board has at least three wiring layers each at least having at least one power supply line or a ground line, and another kind of line, said wiring layers each having an outer edge. A ground line is formed at the outer edge of at least one of the wiring layers. A basic power supply line is formed inside the ground line. At least one power supply line extends from the basic power supply line. A plurality of electronic parts are mounted on at least one of the wiring layers. The at least one power supply line is wired to mounting positions of the electronic parts via at least one of the wiring layers.

Abstract: A multilayer circuit assembly includes a power circuit and a numerical data circuit. The power circuit includes a power layer and power components. The numerical data circuit includes a numerical data layer and numerical data components. Power components and numerical data components are incorporated on an external surface of the numerical data layer. Preferably, all of the power components are incorporated on an external face of a numerical data layer. The numerical data layer may be a different thickness than the power circuit layer, and is generally thinner. The assembly may also include an insulating substrate disposed between the power circuit layer and the numerical data layer. The numerical data layer and the power circuit layer may be etched on opposite sides of the insulating substrate. The assembly can also include additional numerical and/or power circuit layers. The power components are typically connected to the power layer using blind vias.

Abstract: An interconnect module for an integrated circuit chip incorporates a thin, high dielectric constant embedded capacitor structure to provide reduced power distribution impedance, and thereby promote higher frequency operation. The interconnect module is capable of reliably attaching an integrated circuit chip to a printed wiring board via solder ball connections, while providing reduced power distribution impedance of less than or equal to approximately 0.60 ohms at operating frequencies in excess of 1.0 gigahertz.

Abstract: A circuit assembly (1) and electronic device (30) having a printed circuit board (2), with conductive runners (3) and a ground plane (4). There is electronic circuitry (5) mounted to the circuit board (2) and electrically coupled to the runners (3). The circuit assembly (1) also has a Liquid Crystal Display (6) electrically coupled to the electronic circuitry (5), and a monopole element (7) is mounted on a surface of the Liquid Crystal Display (6) by a dielectric mount (10) that is proximal to an edge (11) of the printed circuit board (2).

Abstract: A printed circuit board (PCB) has a plurality of electromagnetic interference (EMI) reducing circuits, which reduce electromagnetic waves emitted from the PCB, and a plurality of switching devices, such as MOS transistors, relays and DIP switches, to enable and disable the EMI reducing circuits. The EMI reducing circuits connected between border portions of a voltage and a ground layers in the PCB include at least a capacitor. A combination of the EMI reducing circuits which gives a minimum amount of electromagnetic waves emitted from an apparatus including the PCB is selected as a suitable combination of EMI reducing circuits. An information processing apparatus having the printed circuit boards has means for selecting a combination of the EMI reducing circuits which allow the minimum EMI emitted for the apparatus.

Abstract: A substrate of the present invention includes pads which are provided on the surface of said substrate; and surface layers which are kept to the ground potential and cover the surface of said substrate except said pads and their peripheral. Another substrate of the present invention includes a part of circuit which is provided on the surface of said substrate; and a surface layers which are kept to the ground potential and cover the surface of said substrate except said part of circuit and its peripheral.

Abstract: In the present radio frequency device, a radio frequency circuit part and a transmission line are disposed on the top surface of a circuit board on the surface of which a ground pattern is provided, and a metal shielding cap is fixed to the circuit board so as to cover the radio frequency circuit part and the transmission path. The metal shielding cap includes: a top plate disposed above the radio frequency circuit part and substantially parallel to the circuit board; a grounded side wall being provided so as to hang down from a part of an edge of the top plate, having a spring property and being joined to the ground pattern of the circuit board, and a side wall is open except for the grounded side wall.

Abstract: A circuit board includes two planes. A via spans the planes, and an impedance component is placed in the via. The impedance component is coupled to both of the planes. The impedance component provides an impedance between the planes without the use of traces or hand soldering of components.

Abstract: A printed wiring board having differential pair signal traces has increased spacing between signal-carrying vias and ground or power planes and/or is equipped with selectively placed ground vias to enhance the impedance matching of the signal traces.

Abstract: A packaged die (112) for an integrated circuit (62) that eliminates the wire bonds required in the prior art, and provides integrated circuit packaging while the circuit (62) is still in a wafer format. A wafer substrate (64) on which the integrated circuits (62) have been fabricated is patterned and etched to form signal and ground vias (74, 72) through the substrate (64). A back-side ground plane (82) is deposited in contact with the ground vias (72). A protective layer (90) is formed on the top surface (76) of the substrate (64), and a protective layer (98) is formed on the bottom surface (84) of the substrate (64), where the bottom protective layer (98) fills in removed substrate material between the integrated circuits (62). Vias (106) are formed through the bottom protective layer (98), and the wafer substrate (64) is diced between the integrated circuits (62).

Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).

Abstract: The inductance of the capacitor is reduced by connecting the capacitor directly to a via. In one embodiment inductance of a capacitor is reduced by a plurality of via, the number of via greater than the number of electrical couplings from the voltage pad to the voltage plane. In one embodiment the capacitor has a ground pad of a minimum size. In another embodiment the capacitor is electrically coupled to a trace having a length reduced to minimize inductance.

Abstract: An apparatus is disclosed. The apparatus has a printed circuit board and one or several integrated circuit substrates mounted to the printed circuit board. At least one SMT component with two or more terminals is arranged between the printed circuit board and the package. In one embodiment, the SMT component replaces interconnects in the ball grid array used to mount the substrate to the printed circuit board while simultaneously connecting the SMT terminals to the substrate and the printed circuit board. The disclosed apparatus of SMT components mount results in significant reduction of inductance of the SMT connection to the substrate.

Abstract: Disclosed is a printed circuit board which is advantageous in terms of high capacitance by embedding capacitors comprising polymer capacitor pastes with high-dielectric constant coated on an inner layer of the printed circuit board and then semi-dried to a state of B-stage.

Abstract: The present invention is a reconfigurable substrate which includes at least one signal line layer stack. Each signal line layer stack is defined to include two substantially parallel insulating layers and a signal line layer interposed between the two insulating layers and substantially parallel to the insulating layers. The substrate includes at least one conductive isolation layer adjacent to at least one signal line layer stack and substantially parallel to the at least one signal line layer stack. The substrate is reconfigurable to different performance levels by adding or removing at least one conductive isolation layer.

Abstract: A high frequency semiconductor device includes a ground plate, an insulating layer, a power-supply conductor, an insulating interlayer, and a strip line as a line conductor. The power-supply conductor is disposed above the ground plate, with the insulating layer provided therebetween. The ground plate and the power-supply conductor have a capacitance formed therebetween. Thus, the line conductor regards the power-supply conductor as having a potential identical to that of the ground plate. This makes it possible to lay out the line conductor without considering the arrangement of the power-supply conductor. In other words, by two-dimensionally overlapping a microstrip line and a power-supply conductor in an MMIC, the degree of freedom in the device layout can be increased.

Abstract: A power amplifier assembly combines a single printed circuit board with a housing for providing isolation between subcircuits of the circuit board. The printed circuit board is provided with four conductive layers and contains a power supply subcircuit, an upconverter subcircuit, a monitor and control subcircuit, a low power gain subcircuit, and a high power gain subcircuit. The printed circuit board is further provided with plated-through vias in an isolation path which, in conjunction with internal chassis lid walls, serves to increase electromagnetic and radio frequency isolation between subcircuits on the printed circuit board.

Abstract: Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.

Abstract: A surface laminar circuit board includes an insulating layer, and a signal ground conductive layer disposed on an upper surface of the insulating layer. The conductive layer has a hole formed therein. A photosensitive dielectric layer is disposed on an upper surface of the signal ground conductive layer. The dielectric layer has a photo micro-via formed therein. A signal trace is disposed on the photosensitive dielectric layer, and is electrically coupled with the signal ground conductive layer by way of the photo micro-via. A conductive pad is provided, which has a majority thereof within an area defined by an outer periphery of the hole. The conductive pad is electrically coupled with the signal trace. A surface mounted component is mounted on the conductive pad.

Abstract: Solder bumps are created on a substrate of an electronic assembly having lengths that are longer than the widths. The solder bumps are created by locating solder balls of power or ground connections close to one another so that, upon reflow, the solder balls combine. Signal solder balls however remain separated. Capacitors are created by locating power solder bumps adjacent ground solder bumps and extending parallel to one another.

Abstract: A high-frequency wiring board of the present invention is characterized in that W1>W2 and S1≧S2 are satisfied in which W1 is a line width of a portion having a predetermined characteristic impedance of a line conductor, W2 is a conductor width of the line conductor in proximity to a connection of one end of the line conductor to a through conductor, S1 is an interval between the portion having the line width W1 of the line conductor and a same plane ground conductor, and S2 is an interval between the portion of the one end of the line conductor in proximity to the connection to the through conductor and the same plane ground conductor.

Abstract: A voltage controlled oscillator is provided. The oscillator includes a surface acoustic wave element for forming a feedback circuit for an amplifier, and a phase adjustment circuit including a filter which is interposed in the feedback circuit. The oscillator also has a phase shifter including a hybrid coupler to which an additional control part is attached for changing a phase value within an oscillation loop with a control voltage supplied from an external source. An equal power divider equally distributes output power within the oscillation loop and supplies the output power outside the oscillation loop. A multi-layer board is used for mounting the amplifier, surface acoustic wave element, phase adjustment circuit, phase shifter, and equal power divider in at least two separate layers.

Abstract: A multi-layered circuitized substrate for high-frequency applications. Conductive via-holes extend between two non-adjacent conductive layers for transmitting high-frequency signals therebetween. For each via-hole, shielding rings connectable to a reference voltage are provided, each ring formed in a corresponding intermediate conductive layer between the two non-adjacent conductive layers. The rings define a shielding coaxial structure for the via-hole. Preferably, the intermediate conductive layers are spaced apart from the via-hole, and particularly from respective lands at the ends thereof, in order to reduce stray capacitance associated with the via-hole without losing the shielding effect provided by the rings.

Abstract: A multi-layer wiring board comprises an insulating substrate having, on a central part of its top surface, a semiconductor device mounting portion and having, on its under surface, an external electrode. The insulating substrate includes a multilayered wiring having a first group of parallel wiring lines; a second group of parallel wiring lines arranged orthogonal thereto; and a group of through conductors for providing electrical connection therebetween. Power is supplied from the external electrode to the semiconductor device through built-in capacitors formed therewithin. The built-in capacitors are connected in parallel that have different resonance frequencies within a range from an operating frequency band for the semiconductor device to a frequency band for a harmonic component, and at an anti-resonance frequency occurring between the different resonance frequencies, a composite impedance is equal to or below a predetermined value.

Abstract: The covering sheet includes at least one magnetic material layer made of a resin compound having an oxide magnetic material or a metal magnetic material mixed therein, a ground conductor layer laminated on one surface of the magnetic material layer, and a plurality of via holes for passing conducting unit for grounding the ground conductor layer, or includes a laminate consisting of at least one magnetic material layer made of a resin compound having an oxide magnetic material or a metal magnetic material mixed therein and at least one dielectric layer having a permittivity lower than that of the magnetic material layer, and a ground conductor layer laminated on one surface of the laminate.

Abstract: There has been a problem that a mode (a high-order mode) different from a basic propagation mode occurs at a point of a through conductor and a transmission characteristic deteriorates greatly. The present invention is a high-frequency wiring board wherein L>&lgr;/4 and &pgr;(A+B)≦&lgr; are satisfied in which L is a length of a through conductor, A is a diameter of the through conductor, B is shortest distances between the through conductor and a plurality of ground through conductors, &pgr; is a circle ratio and &lgr; is an effective wavelength of a high-frequency signal transmitted by the through conductor. It is possible to inhibit a high-order mode which occurs at a point of the through conductor.

Abstract: An electronic module includes an interconnect module having a plurality of metal layers separated by a plurality of dielectric layers in a stacked structure with electronic components mounted on one surface of the module. The electronic components are selectively interconnected by drilling via holes completely through all dielectric layers with a conductive material such as solder in each via contacting metal layers to be interconnected and each metal layer which is not connected by a via having a metal pattern devoid of metal at the via location. For via connecting non-ground layers, there will be a patch of solder mask on the backside ground layer to electrically prevent this via from inadvertently connecting to ground.

Abstract: In a circuit board comprising multiple layers and having an integrated circuit mounted on the outer layer thereof, a main power supply plane and a sub-power supply plane, which is disposed in an island fashion with a clearance that terminates electric connection with the main power supply plane, are formed on the same layer. The main power supply plane and the sub-power supply plane are connected by first power supply patterns that are formed on a layer different from the layer on which the power supply planes are formed and to which bypass condensers are connected. Power supply to some power supply terminals is achieved via second power supply patterns that are connected to the sub-power supply plane. The leakage of noise from the power supply terminals connected to the second power supply patterns is controlled by the first power supply patterns. Through this construction, the EMI noise radiated from the circuit board can be reduced while minimizing the number of bypass condensers.

Abstract: This disclosure describes use of dielectric islands embedded in metallized regions of a semiconductor device. The islands are formed in a cavity of a dielectric layer, as upright pillars attached at their base to an underlying dielectric. The islands break up the metal-dielectric interface and thus resist delamination of metal at this interface. The top of each island pillar is recessed from the cavity entrance by a selected vertical distance. This distance may be varied within certain ranges, to place the island tops in optimal positions below the top surface plane of the dielectric. Metallization introduced into the cavity containing the islands, submerges the island tops to at least a minimum distance to provide a needed minimum thickness of continuous metal. The continuous metal surface serves favorably as a last metal layer for attaching solder or for bump-bonding package to the IC; and also serves as an intermediate test or probe pad in an interior layer.

Abstract: A two layer PBGA which includes a metal ground plane at its bottom layer. The ground plane is preferably a metal plane which is connected to ground through a metal connection to a ball pad at the center of the package and a ball pad proximate the edge of the package. The ground plane is voided around the signal and power balls, via and “dog bones”. The PBGA is configured such that the ground plane serves effectively the same function as the second layer ground plane in a conventional four layer PBGA. The PBGA provides a cheaper alternative to the generally more expensive four layer PBGA, and provides better cross talk performance (especially for high frequency signaling) as well as better thermal performance as a result of having more metal at the bottom layer of the package.

Abstract: An interconnect module for an integrated circuit chip incorporates a thin, high dielectric constant embedded capacitor structure to provide reduced power distribution impedance, and thereby promote higher frequency operation. The interconnect module is capable of reliably attaching an integrated circuit chip to a printed wiring board via solder ball connections, while providing reduced power distribution impedance of less than or equal to approximately 0.60 ohms at operating frequencies in excess of 1.0 gigahertz.

Abstract: An insulation layer is formed on a ground layer. The insulation layer includes first and second regions for forming wiring layers. The impedance of a wiring layer formed on the second region is lower than that of a wiring layer formed on the first region. A signal line pattern is formed on the wiring layer on the first region of the insulation layer. A power supply plane is formed on the wiring layer on the second region of the insulation layer in order to feed power to the signal line pattern through a termination resistor connected to the signal line pattern.

Abstract: An output of a voltage regulator is a core voltage line that runs adjacent to a die attach area on a packaging substrate. An input of the voltage regulator is typically coupled to a power supply which, in one embodiment, is also an I/O voltage line that runs adjacent to the die attach area. In one embodiment, the core voltage line is shaped as a ring encircling the die attach area on the packaging substrate. In another embodiment, the I/O voltage line is also shaped as a ring encircling the die attach area on the packaging substrate. Further, a semiconductor die having at least one I/O Vdd bond pad and at least one core Vdd bond pad can be mounted in the die attach area. The I/O Vdd bond pad and the core Vdd bond pad can be connected, respectively, to the I/O voltage ring and the core voltage ring.

Abstract: A multi-layer printed circuit board includes at least a ground plane for providing a ground level, at least a signal plane having a plurality of trace regions for transmitting signals, at least a power plane region having a plurality of power blocks for individually providing a plurality of voltage levels, and at least a via for electrically connecting the trace regions with the power plane region or the ground plane. Two adjacent power blocks with different voltage levels are separated by an insulating line. The insulating line has a plurality of first insulating sectors, and a plurality of second insulating sectors for connecting two adjacent first insulating sectors when an included angle of the adjacent first insulating sectors is greater than a predetermined value.

Abstract: A multilayer ceramic semiconductor chip carrier is provided by a method of interconnecting ground, signal and power lines in a semiconductor chip carrier. The method involves forming a plurality of insulating layers with conductor lines comprising power and ground lines connected in parallel in a single plane formed in planes between the insulating layers. The parallel lines are directed in orthogonal directions in parallel between any two of the insulating layers with alternation successively between planes of X-directed lines and planes of Y-directed coplanar signal, power and ground lines. There are via connections formed between planes connecting a power line in one plane to another power line in another plane. Other via connections between planes connect a ground line in a first plane to another ground line in a second plane, and signal lines are formed in parallel between a ground line and a power line in a given plane.

Abstract: A power distribution system for distributing external power across a die is disclosed, wherein the die has horizontal and vertical centerlines. The system and method include providing a power mesh that includes a plurality of V-shaped trunks patterned as concentric diagonal trunks extending from the horizontal and vertical centerlines of the die towards the periphery of the die.

Abstract: A multi-layer printed circuit board (PCB) has a plated through hole for receiving a pin of a component. The plated through hole passes through all layers of the PCB and includes a first conductive portion on a first surface of the PCB and a second conductive portion on a second surface of the PCB. At least one layer of the PCB includes a planar conductive material disposed over a planar insulating material. The conductive material surrounds the plated through hole and is separated therefrom by a gap.

Abstract: The present invention relates to multi-cell regulator systems and methods. Power supply delivery and regulation is provided to electronic devices disposed on a PCB board. A voltage regulator cell system is provided for a respective voltage regulation cell region, such that the supply voltage is regulated over the area of the power plane and the ground plane. The voltage regulator cell systems are provided with feedback loops at corresponding voltage regulation cell regions, which are compared with a reference voltage to adjust for difference errors. Various systems and methodologies are provided to obtain a desired reference voltage. Power supply delivery performance is further improved by accurate current sharing between voltage regulator cell systems.

Abstract: A circuit board includes (i) a section of circuit board material having a signal conductor, a ground conductor, and dielectric material that separates the signal conductor and the ground conductor, and (ii) a signal launch. The signal launch includes a signal via that contacts the signal conductor and the dielectric material of the section of circuit board material, a first set of ground vias and a second set of ground vias. The ground vias contact the ground conductor and the dielectric material of the section of circuit board material. The first set of ground vias is disposed a first radial distance from the signal via. The second set of ground vias is disposed a second radial distance from the signal via. A coaxial connector mounts to the signal launch of the circuit board in order to provide electrical access to the signal and ground conductors.