Interconnection Details Patents (Class 361/803)
  • Publication number: 20100202126
    Abstract: There is provided a stacked mounting structure in which, it is possible to realize a narrowing of pitch and to secure a height which enables to mount components to be mounted, and a method of manufacturing stacked mounting structure. The stacked mounting structure includes a plurality of members provided with a mounting area which is necessary for installing and operating components to be mounted on at least one principal surface, and an area for connections for signal transfer for operating the components to be mounted, and an electroconductive member which is disposed on the area for connections between the mutually facing members, and a cross section of the electroconductive member is same as or smaller than the area for connections, and an end portion of the electroconductive member is extended from a principal surface of one member up to a principal surface of the other member, and a height of the electroconductive member regulates a distance of the mounting area.
    Type: Application
    Filed: September 16, 2008
    Publication date: August 12, 2010
    Applicant: OLYMPUS CORPORATION
    Inventors: Mikio Nakamura, Yu Kondo
  • Patent number: 7768796
    Abstract: A flex circuit is populated on one or both sides with plural integrated circuit die. In a preferred mode, the flex circuit is populated with flip-chip die. One side of the flex circuit has a connective facility implemented in a preferred mode with edge connector contacts. The flex circuit is disposed about a substrate to form a circuit module that may be inserted into an edge connector such as ones typically found on a computer board.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: August 3, 2010
    Assignee: Entorian Technologies L.P.
    Inventors: James W. Cady, Paul Goodwin
  • Patent number: 7768795
    Abstract: Electronic circuit device (100) is structured so that a substrate module unit that are formed by stacking substrate modules made of a first resin sheet with electronic component (190) embedded thereinto is inserted into housing (150) including connecting terminal (120), control circuit (130), and first wiring pattern (140), where the substrate modules are connected to each other electrically and mechanically. This electronic circuit device (100) dispenses with a mother substrate. Further, with slimming down of a substrate module, a substrate module unit with a large number of substrate modules stacked can be loaded in a limited packaging space, thus mounting greater storage capacity and higher functionality.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: August 3, 2010
    Assignee: Panasonic Corporation
    Inventors: Daisuke Sakurai, Masahiro Ono, Kazuhiro Nishikawa
  • Patent number: 7760513
    Abstract: Flexible circuitry is populated with integrated circuitry (ICs) disposed along one or both of its major sides. The populated flexible circuitry is disposed proximal to a rigid substrate to place the integrated circuitry on one or both sides of the substrate with one or two layers of integrated circuitry on one or both sides of the substrate. The rigid substrate exhibits adhesion features that allow more advantageous use of thermoplastic adhesives with concomitant rework advantages and while providing flexibility in meeting dimensional specifications such as those promulgated by JEDEC, for example.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: July 20, 2010
    Assignee: Entorian Technologies LP
    Inventors: Julian Partridge, David Roper, Paul Goodwin
  • Patent number: 7755881
    Abstract: A modular server system includes a midplane having a system management bus and a plurality of blade interfaces on the midplane. The blade interfaces are in electrical communication with each other. A server blade is removeably connectable to one of the plurality of blade interfaces on the midplane. The server blade has a server blade system management bus in electrical communication with the system management bus of the midplane, and a network interface to connect to a network. A media blade is removeably connectable to one of the plurality of blade interfaces on the midplane, and the media blade has at least one storage medium device.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: July 13, 2010
    Assignee: Intel Corporation
    Inventors: David A. Bottom, Tim Harvey
  • Patent number: 7754978
    Abstract: A multilayer printed wiring board 10 includes: a core substrate 20; a build-up layer 30 formed on the core substrate 20 and having a conductor pattern 32 on an upper surface; a low elastic modulus layer 40 formed on the build-up layer 30; lands 52 that are disposed on an upper surface of the low elastic modulus layer 40 and connected via solder bumps 66 to a semiconductor chip 70; and conductor posts 50 that are passing through the low elastic modulus layer 40 and electrically connecting lands 52 with conductor patterns 32. The conductor posts 50 are formed to have the diameters of an upper portion and a lower portion of 80 ?m, the diameter of an intermediate portion of 35 ?m, the height of 200 ?m, and the aspect ratio Rasp (height/minimum diameter) of 5.7 and the maximum diameter/minimum diameter of 2.3.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: July 13, 2010
    Assignee: Ibiden Co., Ltd.
    Inventors: Takashi Kariya, Toshiki Furutani
  • Patent number: 7755912
    Abstract: A printed circuit board unit includes a first board and a second board. First electrically-conductive terminals are fixed and exposed on the front surface of the first board in a matrix. Second electrically-conductive terminals are arranged in a matrix and supported on the front surface of the second board. The second electrically-conductive terminals have flexibility. Each of the second electrically-conductive terminals is disengageably brought in contact with the corresponding first electrically-conductive terminal. A static pressure member is received on the back surface of the first board within an area corresponding to the specific area to generate a static pressure. An urging plate is overlaid on the static pressure member so that the static pressure member is interposed between the urging plate and the first board. The urging plate exhibits an urging force applied to the first board toward the second board.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: July 13, 2010
    Assignee: Fujitsu Limited
    Inventor: Yoshihiro Morita
  • Patent number: 7749592
    Abstract: A multilayer ceramic substrate includes a plurality of stacked glass ceramic layers and internal conductors. The glass ceramic layers contain at least one diffusion element selected from the group consisting of Ti, Zr and Mn. The internal conductors contain Ag as a conductive material. The multilayer ceramic substrate is produced by the steps of adding at least one diffusion element selected from the group consisting of Ti, Zr and Mn to conductive paste and diffusing the diffusion element in the glass ceramic layers around the conductive paste. As a result, defects otherwise possibly generated around the internal conductors can be eliminated with exactitude.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: July 6, 2010
    Assignee: TDK Corpoation
    Inventors: Tomoko Nakamura, Katsuhiko Igarashi
  • Publication number: 20100165185
    Abstract: A circuit board assembly includes a circuit board and at least one electrical element. The circuit board includes a dielectric substrate including a supporting surface, and at least one connecting part formed on the supporting surface. The at least one electrical element is electrically connected to the at least one connecting part via a connecting media. At least one air-exhaust hole extends through the connecting part and the dielectric substrate. The at least one air-exhaust hole is configured for exhausting air from the connecting media.
    Type: Application
    Filed: March 9, 2010
    Publication date: July 1, 2010
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: FU-YEN TSENG
  • Publication number: 20100159755
    Abstract: High density electronic device assemblies and techniques for forming high density electronic device assemblies are disclosed. These assemblies and techniques can be used to form compact electronic devices. In one embodiment, substrate arrangements that include a multiple-part substrate can be used to form a high density electronic device assembly. In another embodiment, one or more clips can be used in a high density electronic device assembly to provide mechanical and electrical interconnection between electrical structures that are to be removably coupled together as parts of the high density electronic device assembly. In still another embodiment, a removable cap (and a method for forming the removable cap) can be used for an electronic device housing.
    Type: Application
    Filed: June 23, 2009
    Publication date: June 24, 2010
    Inventors: Wey-Jiun Lin, Kevin Pan, CONRADO SACLUTI DE LA CRUZ
  • Publication number: 20100157560
    Abstract: A wired circuit board for electrically connecting a suspension board with circuit comprising a metal supporting layer, an insulating base layer, a conductive layer, and an insulating cover layer, and an external circuit, includes a first wired circuit board electrically connected with the suspension board with circuit; and a second wired circuit board for electrically connecting with the external circuit. The first wired circuit board and the second wired circuit board are electrically connected through a preamplifier. The first wired circuit board includes a first metal supporting layer; a first insulating base layer; a first conductive layer and a first insulating cover layer.
    Type: Application
    Filed: December 8, 2009
    Publication date: June 24, 2010
    Applicant: Nitto Denko Corporation
    Inventors: Hitoki Kanagawa, Akinori Itokawa, Naotaka Higuchi
  • Patent number: 7742310
    Abstract: Various apparatus and methods relating to a sequencer for connecting an electronic device to a circuit board are disclosed.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: June 22, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Matthew D. Neumann, Bryan Bolich
  • Patent number: 7729127
    Abstract: A mounting mechanism for mounting an electronic device to a chassis, the electronic device defining a first securing hole, and the chassis defining a second securing hole, includes a securing member having a base. A plurality of elastic hooks extends from a bottom of the base. At least one blocking portion protrudes laterally from the base. The elastic hooks extend through the first securing hole and the second securing hole and are engaged with a bottom side of one of the chassis and the electronic device. The at least one blocking portion abuts on the other one of the chassis and the electronic device, for sandwiching the electronic device and the chassis between the hooks and the at least one blocking portion.
    Type: Grant
    Filed: December 29, 2007
    Date of Patent: June 1, 2010
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Chin-Wen Yeh, Zhen-Neng Lin
  • Patent number: 7719850
    Abstract: A power supply module arrangement with an integrated circuit mounted on a bearing unit and a power supply includes an integrated circuit mounted on a bearing unit and a power supply module arrangement that is placed on the combination of bearing unit and integrated circuit. The power supply module arrangement includes a base extending at least partially over the base of the integrated circuit and/or all around the base of the integrated circuit. The power supply module arrangement allows for greater permissible load jumps, greater permissible current change rates and ever tighter tolerances regarding the constancy of the supply voltage.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: May 18, 2010
    Assignee: NXP B.V.
    Inventors: Thomas Duerbaum, Reinhold Elferich
  • Publication number: 20100118505
    Abstract: The disclosure involves the efficient termination of a winding PCB of a planar inductive component to a main PCB, using relatively little space and providing a low-resistance connection. The disclosed methods are especially suitable for planar structures where several winding PCBs, and/or winding PCBs and a main PCB, are all enclosed by the magnetic path components. The methods allow for a winding PCB to simply rest on the main PCB, or other winding PCBs, without any clearance. The disclosure employs mating sets of conductive annular rings with an optional interlocking terminal pin that allows two PCBs to be fixedly coupled together, while preserving a minimum distance between the solder-mask layers of the two PCBs in order to prevent the formation of unwanted electrical connections between the two PCBs. Solder is used to ensure effective coupling in each assembly of mating annular rings and optional terminal pin.
    Type: Application
    Filed: October 6, 2008
    Publication date: May 13, 2010
    Applicant: BATTERY-BIZĀ® INC.
    Inventors: Victor Marten, Aakar Patel, Mark Vanstone
  • Patent number: 7715206
    Abstract: A system comprises a chassis and a system board contained within the chassis. The system board has an edge connector adapted to receive an add-in card in a configuration in which the system board and add-in card are substantially co-planar.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: May 11, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Thomas H. Szolyga, Jean-Paul Moiroux
  • Patent number: 7715200
    Abstract: A stacked semiconductor module, a method of fabricating the same, and an electronic system using the module are provided. A first semiconductor module having a plurality of semiconductor devices mounted on a rigid printed circuit board (PCB) and a second semiconductor module having a plurality of other semiconductor devices mounted on a flexible PCB are provided. On the rigid PCB a number L of first tabs may be disposed on a first surface, and a number K of second tabs may be disposed on a second surface of the rigid PCB. The flexible PCB may have a number M of third tabs on a third surface, and a number N of fourth tabs on a fourth surface of the flexible PCB. The second tabs may be combined with the third tabs using a conductive adhesive. The third tabs may be electrically connected to corresponding ones of the second tabs.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: May 11, 2010
    Assignees: Samsung Electronics Co., Ltd., Samsung Electro-Mechanics
    Inventors: Jung-Chan Cho, Yang-Je Lee, Hyun-Seok Choi, Yong-Hyun Kim, Jung-Hyeon Kim, Hyo-Jae Bang, Do-Hyung Kim, Kyoung-Sun Kim, Young-Ho Lee, Jae-Sang Baik, Yong-Jin Kim
  • Patent number: 7715207
    Abstract: One embodiment of the invention provides a fully distributed, scaleable and modular rack architecture and management system. One feature of the invention provides device management throughout the rack system with a vertical interface column integrated into the rack cabinet. Within each rack unit (U) of the vertical interface column, the vertical interface column may deliver connectivity to a device housed within the rack cabinet thereby eliminating runs of cable typically necessary for management of such devices. The vertical interface column can be expanded as necessary to provide connectivity to more devices using hot-swappable interface modules. A rack management system allows both local and remote management access to all devices mounted in the rack cabinet and coupled to the vertical interface column. The rack management system may also access to devices mounted in other rack cabinets.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: May 11, 2010
    Assignee: Epicenter, Inc.
    Inventors: Edward Behrens, Tho Tu, Van T. Hua, David Wang
  • Patent number: 7710741
    Abstract: One embodiment of a reconfigurable graphics processing system includes a first MXM edge connector and a second MXM edge connector affixed to an interposer board and a first MXM board and a second MXM board coupled to the interposer board via the first and second MXM edge connectors, respectively. Each MXM board includes a GPU and other elements necessary to process graphics data. The system couples to the motherboard of a computing device through an interface connector on the interposer board. One advantage of such a system is that it may be configured to deliver more performance than a standard desktop graphics board, while occupying substantially the same volume, through the use of multiple, small form factor MXM boards.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: May 4, 2010
    Assignee: NVIDIA Corporation
    Inventors: Brian M. Kelleher, Ludger Mimberg, Anthony M. Tamasi
  • Publication number: 20100103634
    Abstract: A circuit board includes a functional device, a circuit board embedding therein the functional device, and first and second conductive-wiring layers formed on the front and rear surfaces of the circuit board to sandwich therebetween the functional device and each include at least one conductor layer. The surface of each of the outermost patterned interconnections of the first conductive-wiring layer is exposed, and the surface of a first dielectric layer isolating the outermost patterned interconnections from one another protrudes from the surface of the each of the patterned interconnections. The patterned interconnections of the second conductive-wiring layer are connected to respective electrode terminals of the functional device, and the surface of a second dielectric layer isolating the electrode terminals from one another is substrate within the same plane as the surface of the electrode terminals disposed adjacent to the second dielectric layer.
    Type: Application
    Filed: March 28, 2008
    Publication date: April 29, 2010
    Inventors: Takuo Funaya, Shintaro Yamamichi, Hideya Murai, Kentaro Mori, Katsumi Kikuchi
  • Publication number: 20100103651
    Abstract: The LED module comprises a first and a second printed circuit boards comprising one surface formed with at least one of concave and convex parts so that the first and the second printed circuit boards are coupled to each other, and an LED on at least one of the first and the second printed circuit boards, in which a concave part is formed at a portion of a coupling surface of the second printed circuit board corresponding to a convex part formed at a portion of a coupling surface of the first printed circuit board, and an insulating layer is formed at a portion of the coupling surface of the second printed circuit board so as to support a convex part of the first printed circuit board.
    Type: Application
    Filed: March 18, 2008
    Publication date: April 29, 2010
    Applicant: LG Innotek Co., Ltd.
    Inventor: Jun Seok Park
  • Patent number: 7706148
    Abstract: A stack structure of circuit boards embedded with semiconductor chips is proposed. At least two circuit boards are provided. Each of the circuit boards includes circuit layers formed on surfaces thereof and at least one opening embedded with a semiconductor chip, wherein, the circuit layers have a plurality of conductive structures and electrically conductive pads, and the semiconductor chip has a plurality of electrode pads, and the conductive structures of the circuit layers are electrically conductive to the electrode pads of the semiconductor chip. At least one adhesive layer is formed between the two circuit boards and disposed with a conductive material corresponding in position to the electrically conductive pads of the circuit boards. Thus, a conductive path can be formed by the conductive material between the electrically conductive pads of the circuit boards, thereby establishing electrical connection between the two circuit boards.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: April 27, 2010
    Assignee: Phoenix Precision Technology Corporation
    Inventors: Shih Ping Hsu, Chung Cheng Lien, Chia Wei Chang
  • Publication number: 20100097772
    Abstract: A display device includes a circuit board connecting structure. The circuit board connecting structure includes a first circuit board, a soldering layer, and a second circuit board. The first circuit board includes a baseboard and a plurality of parallel elongate first electrodes defined at a predetermined area. The second circuit board includes a plurality of parallel elongate second electrodes positioned at the predetermined area. The second electrodes are electrically connected to the corresponding first electrodes via the soldering layer. A space defined by the projection of the second electrodes to the baseboard of the first circuit board is filled in by the soldering layer.
    Type: Application
    Filed: October 19, 2009
    Publication date: April 22, 2010
    Inventors: Po-Shan Huang, Jia-Shyong Cheng
  • Patent number: 7701722
    Abstract: An object of the present invention is to provide a flexible printed wiring board which relaxes stress concentration in the flexible printed wiring board during production steps, thereby preventing wire breakage in inner lead portions and cracking in solder resist which would otherwise be caused during mounting of devices such as IC chips and LSI chips. The flexible printed wiring board of the present invention includes an insulating layer; a wiring pattern formed of a plurality of wirings being juxtaposed, which wiring pattern is formed through patterning a conductor layer stacked on at least one surface of the insulating layer and on which wiring pattern a semiconductor chip is to be mounted; and grid-like dummy patterns formed in a blank area where the wiring pattern is not provided, wherein the dummy patterns are formed in a width direction generally symmetrically with respect to the longitudinal direction of the flexible printed wiring board.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: April 20, 2010
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventor: Kota Hagiwara
  • Patent number: 7692102
    Abstract: An electronic circuit device includes at least two circuit substrates for mounting electronic components and a flexible board for external electrical connection disposed between the circuit substrates. The flexible board is electrically connected to at least the surface of one circuit substrate opposed to another circuit substrate.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: April 6, 2010
    Assignee: Sony Corporation
    Inventors: Yoshiteru Kawakami, Yasuharu Nakamura
  • Patent number: 7692931
    Abstract: Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods are disclosed. A system in accordance with one embodiment includes a support member having first package bond sites electrically coupled to leadframe bond sites. A microelectronic die can be carried by the support member and electrically coupled to the first packaged bond sites. A leadframe can be attached to the leadframe bond sites so as to extend adjacent to the microelectronic die, with the die positioned between the leadframe and the support member. The leadframe can include second package bond sites facing away from the first package bond sites. An encapsulant can at least partially surround the leadframe and the microelectronic die, with the first and second package bond sites accessible from outside the encapsulant.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: April 6, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Chin Hui Chong, Choon Kuan Lee, David J. Corisis
  • Publication number: 20100079969
    Abstract: A function expansion device is electrically connected to an electronic apparatus by being inserted in a socket included in the electronic apparatus and expands a function of the electronic apparatus. The function expansion device includes a substrate on which a component is mounted, a first connecting terminal that is formed at an end portion of the substrate and is electrically connected to a first signal line that connects the electronic apparatus and the component in a one-to-one fashion, a second connecting terminal that is formed at the end portion of the substrate and is electrically connected to a second signal line that connects the electronic apparatus and the component redundantly, and a protection member that is formed to cover only the second connecting terminal.
    Type: Application
    Filed: September 25, 2009
    Publication date: April 1, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Susumu Eguchi, Hiroshi Shimamori, Yusaku Fujiishi
  • Publication number: 20100079967
    Abstract: An electronic device is provided which makes it possible to reduce noise generated from a signal line around a connecting portion connecting a first body and a second body. The connecting portion has a first metallic portion. A first circuit board provided in the first body and a second circuit board provided in the second body. The signal line that electrically connects the first circuit board and the second circuit board via the connecting portion, in which the signal line is wound around the first metallic portion.
    Type: Application
    Filed: March 26, 2009
    Publication date: April 1, 2010
    Applicant: KYOCERA CORPORATIION
    Inventor: Yoshiaki HIRAOKA
  • Publication number: 20100079968
    Abstract: An improved upright circuit board assembly structure includes: an electronic component to be mounted on an external device so as for electrical functions of the electronic component to be used; and at least one circuit board including at least one first electrical connection portion and at least one second electrical connection portion. The first electrical connection portion and the second electrical connection portion are coupled to the external device by soldering with a solder paste. By soldering the circuit board to the external device in a double-sided, multi-point manner, the electronic component is mounted securely on the external device, and electric connection between the electronic component and the external device is enhanced.
    Type: Application
    Filed: September 7, 2009
    Publication date: April 1, 2010
    Applicant: KINGBRIGHT ELECTRONICS CO., LTD.
    Inventor: Wen-Joe Song
  • Patent number: 7688599
    Abstract: A lead frame module integrally formed from a single thin metal sheet includes: parallel first and second rails extending in a first direction; and first and second lead frame sets connected to the first and second rails, respectively. The first and second lead frame sets respectively include a plurality of lead frames extending in a second direction perpendicular to the first direction. Each of the lead frames of the first and second lead frame sets has a pair of connecting leads and a pair of packaging leads. Each of the packaging leads is connected to a respective one of the connecting leads. The connecting leads of the lead frames of the first lead frame set are interdigitated with and are connected to the connecting leads of the lead frames of the second lead frame set.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: March 30, 2010
    Assignees: Silitek Electronic (Guangzhou) Co., Ltd., Lite-On Technology Corp.
    Inventor: Cheng-Hong Su
  • Publication number: 20100073896
    Abstract: An RF blind-mate connection device disclosed herein includes a duplexer, a power amplification circuit board, a transceiver, an RF signal connector, and a power connector. The duplexer and the transceiver are located at one end of the RF blind-mate connection device, and the transceiver is fixed on the duplexer; the power amplification circuit board is located at the other end of the RF blind-mate connection device, and the location of the power amplification circuit board corresponds to that of the duplexer; the RF signal connector is fixed on the duplexer and the power amplification circuit board; the power connector is fixed on the transceiver and the power amplification circuit board; and the RF signal connector and the power connector transmit both the power signal and the RF signal in a blind-mate way. A board hardware device is disclosed herein to transmit RF signals and power signals inside the RF module through the connector.
    Type: Application
    Filed: December 3, 2009
    Publication date: March 25, 2010
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Chenggang TANG, Hao LI, Haitao LI, Xiaohui SHEN
  • Patent number: 7681309
    Abstract: A method is disclosed that can be used to interconnect an integrated circuit (IC) multiple die assembly to conductors on a substrate such that signals can be conveyed between the dies and the conductors on the substrate. The multiple die assembly can include a first IC die and at least one secondary IC die, which can be mounted on a surface of the first IC die. Signal paths can be provided between the first IC die and the secondary IC die. The method can include providing conductive contacts on the surface of the first IC die. Each such conductive contact can have a free end extending outward from the surface beyond the secondary IC die. The method can also include mounting the multiple die assembly on the substrate such that the free end of each contact is brought into contact with the conductors on the substrate. The secondary IC die can reside between the surface of the first IC die and the substrate, and the contacts can convey signals between the first IC die and the conductors on the substrate.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: March 23, 2010
    Assignee: FormFactor, Inc.
    Inventor: Charles A. Miller
  • Publication number: 20100067208
    Abstract: A method includes forming grooves in first regions included in a first wafer to form wiring regions defined by the grooves; forming insulating portions in the grooves; joining a surface of the first wafer on which the wiring regions are formed to a first surface of a device wafer including device forming regions after forming the insulating portions; forming through holes in the wiring regions of the first wafer after joining the first wafer to the device wafer, the holes extending through the first wafer; filling the holes with a conductive material; joining a second wafer to a second surface of the device wafer opposite the first surface, the second wafer including second regions; exposing the wiring regions by thinning the first wafer after joining the first wafer to the device wafer; and cutting the device wafer, the first wafer, and the second wafer after thinning the first wafer.
    Type: Application
    Filed: July 16, 2009
    Publication date: March 18, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Hiroaki INOUE, Takashi KATSUKI, Fumihiko NAKAZAWA
  • Patent number: 7679928
    Abstract: Provided is a system-in-package module including a system circuit board; a first element that is disposed on the system circuit board; a second element that is disposed on the first element so as to be shifted to one side from the center of the first element, while partially exposing the first element; a third element that is electrically connected to the system circuit board and is disposed on the second element; and a plurality of bump pads that are disposed on the bottom surface of the system circuit board.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: March 16, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Tae Hyun Kim, Sung Taek Kwon, Tae Ha Lee, Dong Kuk Kim
  • Publication number: 20100061072
    Abstract: Ground via provided in an end portion of a multi-layer printed circuit board so as to suppress a leakage of magnetic field from the end portion of the board causes a problem that a digital circuit of high density cannot be mounted on the board due to necessity of area for locating the ground via. Further, a case of using solder plating for the end portion of the board causes a problem that manufacturing process is added and that numbers of days and costs for manufacturing the multi-layer printed circuit board are increased. In a multi-layer printed circuit board has a plurality of ground layers and at least one signal layer, the signal layer in which a signal pattern is wired at an end portion of the multi-layer printed circuit board is sandwiched between upper adjacent and lower adjacent ground layers, and the upper adjacent and lower adjacent ground layers are connected to each other by recessed conductors at the end portion thereof.
    Type: Application
    Filed: July 11, 2007
    Publication date: March 11, 2010
    Applicants: NEC CORPORATION, ELPIDA MEMORY, INC.
    Inventors: Masaharu Imazato, Takao Ono
  • Patent number: 7672140
    Abstract: A circuit board configuration and method of packaging electronic component embedded into the circuit board in a manner that supports the electronic component thermally, electrically, and mechanically thereof, comprising a circuit board having a first surface and a circuit trace on the first surface; a recess or slot formed on the first surface defined by at least one sidewall that is oblique to the first surface of the circuit board; two or more plated surfaces on the at least one oblique sidewall and electrically connected to the circuit trace; and an electronic component having two or more electrical contact surfaces mounted to the two or more plated surfaces such that the electronic component is physically mounted to the oblique sidewall and in electrical communication with the circuit trace.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: March 2, 2010
    Assignee: Tensolite LLC
    Inventor: Bruce Lane
  • Publication number: 20100046187
    Abstract: A cable connects a circuit board mounted with an electronic circuit to a BT module that controls wireless communications compliant with Bluetooth (Registered Trademark). The cable is a connection cable that elastically deforms and applies pushing force in a direction to make the BT module leave away from the circuit board. A second holding piece, which is cantilever-shaped, moves to a releasing position at which holding the BT module is released by elastic deformation as well as moves to a supporting position at which the second holding piece presses the BT module by release of elastic deformation.
    Type: Application
    Filed: October 27, 2009
    Publication date: February 25, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Takeshi Murakami
  • Publication number: 20100046182
    Abstract: A circuit board interconnection system is disclosed according to the embodiments of the present invention. The system includes a first circuit board, a second circuit board, a third circuit board, a first connector and a second connector. The first connector and the second connector are mounted at two sides of the first circuit board respectively so that the second circuit board mounted on the first connector is perpendicular to the third circuit board on the second connector. The first connector and the second connector mounted respectively at two sides of the first circuit board are coupled to each other via an impedance controlled mechanism on the first circuit board. Another circuit board interconnection system, a circuit board, a connector assembly and a method for manufacturing a circuit board are disclosed according to the present invention.
    Type: Application
    Filed: October 28, 2009
    Publication date: February 25, 2010
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Gongxian Jia
  • Patent number: 7667982
    Abstract: An LSI package includes an interface module having first and second surfaces and including a wiring board having a first through hole, a driver selectively provided on the second surface, a transmission line connected to the driver, and a first terminal formed on the second surface and connected to the driver, an interposer having a third surface facing the second surface and a fourth surface, and including a signal processor and a second terminal provided on the third surface, a third terminal provided on the fourth surface and a second through hole, the third surface facing the second surface except a region where the driver portion is provided. The interposer is arranged so that the first through hole matches with the second through hole, and a movable guide pin is inserted into the first and second through holes to position the interface module and the interposer.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: February 23, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Hamasaki, Hideto Furuyama
  • Publication number: 20100033940
    Abstract: An object of the invention is to provide the effects of suppressing noise radiated from a plurality of coupling terminals for coupling between boards to the peripheral space outside of an inter-board coupling connector. Two boards opposing to each other are electrically coupled by coupling terminals (3a), (3b), (3c) and these coupling terminals are molded by insulative resin to form in a frame shape. When an electric signal passes through the coupling terminals (3a), (3b), (3c), the noise radiated in the peripheral space of the outside can be suppressed by a shield plate (4a), (4b) attached to the outer periphery of the resin.
    Type: Application
    Filed: February 28, 2006
    Publication date: February 11, 2010
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyuki Yamaguchi, Kiyoshi Nakanishi, Ken Muramatsu, Hiroyuki Suzuki
  • Publication number: 20100020515
    Abstract: A method of manufacturing a stacked module is disclosed and in particular a micro solid state device (MSSD).
    Type: Application
    Filed: July 2, 2009
    Publication date: January 28, 2010
    Applicant: Smart Modular Technologies, Inc.
    Inventors: Michael Rubino, Satyanarayan Shivkumar Iyer, Alessandro Fin, Mark E. Allen, Phillip Henry Kaminski
  • Publication number: 20100020516
    Abstract: A terminal is provided with a support portion configured to be mounted on a circuit board and having electrical insulation property, and a bus bar supported on the support portion and having electrically conductive property. The bus bar includes an external connecting portion configured to be electrically connected to external equipment, a first connecting portion configured to be electrically connected to the circuit board, and a second connecting portion configured to be electrically connected to another circuit board spaced from the circuit board, without passing through the circuit board.
    Type: Application
    Filed: July 24, 2009
    Publication date: January 28, 2010
    Applicant: KEIHIN CORPORATION
    Inventors: Noriya Kishino, Jin Kurihara
  • Publication number: 20100020505
    Abstract: A printed circuit board (PCB) assembly is disclosed. The PCB assembly includes a first PCB, a second PCB and a land grid array (LGA). The first PCB includes signal interconnects for transmitting logic signals and power interconnects for transmitting power signals. In contrast, the second PCB includes only power interconnects for transmitting power signals exclusively. The second PCB also has significantly less vias than the first PCB. The second PCB is connected to the first PCB via the LGA.
    Type: Application
    Filed: July 28, 2008
    Publication date: January 28, 2010
    Inventors: William L. Brodsky, Kevin R. Covi
  • Patent number: 7652890
    Abstract: A wired circuit board includes a wiring formation portion, a terminal formation portion, and a middle portion formed therebetween. The wiring formation portion includes a first conductive layer formed on a first insulating layer, and a second conductive layer formed on a second insulating layer so as to overlap the first conductive layer in a thickness direction. The terminal formation portion includes the first and second conductive layers formed in parallel in the same plane. The middle portion includes the first conductive layer formed on the first insulating layer, and the second conductive layer formed on a portion of the second insulating layer extending from the wiring formation portion to a mid-point between the wiring formation portion and the terminal formation portion, and formed on a portion of the first insulating layer extending from the mid-point to the terminal formation portion.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: January 26, 2010
    Assignee: Nitto Denko Corporation
    Inventors: Tetsuya Ohsawa, Katsutoshi Kamei
  • Publication number: 20100014267
    Abstract: Provided is a circuit board device, wherein degrees of freedom are provided for a GND connecting position among plural printed boards, and noise shield and/or heat sink effects are provided. An electronic device provided with the circuit board device and a GND connecting method are also provided. Circuit board device (100) includes a pair of printed boards (110, 120), noise generating component (112) and/or heat generating component (122), and metal plate (140). Printed boards (110, 120) include mounting surfaces and GND connecting terminals (111, 121) arranged on the respective mounting surfaces, and the mounting surfaces are arranged to face each other. Noise generating component (112) and/or heat generating component (122) is mounted on the mounting surface of at least one of a pair of printed boards (110, 120).
    Type: Application
    Filed: July 18, 2007
    Publication date: January 21, 2010
    Inventor: Akihito Kubota
  • Publication number: 20100008058
    Abstract: Traffic between logic LSIs and memory is increasing year by year and there is demand for increase of capacity of communication between them and reduction of power consumption in the communication. Communication distances between LSIs can be reduced by stacking the LSIs. However, in a simple stack of logic LSIs and memory LSIs, it is difficult to ensure heat dissipation to cope with increasing heat densities and ensure transmission characteristics for fast communication with the outside of the stacked package. Also required is a connection topology that improves the performance of communication among the stacked LSIs while ensuring the versatility of the LSIs. An external-communication LSI, a memory LSI, and a logic LSI are stacked in this order in a semiconductor package and are interconnected by through silicon vias.
    Type: Application
    Filed: May 14, 2009
    Publication date: January 14, 2010
    Inventors: Makoto SAEN, Kenichi OSADA
  • Patent number: 7643286
    Abstract: A symmetric multiprocessor computer is provided with a star interconnection architecture and a cooling system. The star interconnection architecture include a middle plane, and plural first processor boards and second processor boards configured vertically onto opposite surfaces of the middle plane. The first processor boards and the second processor boards are crisscross to each other at the opposite surfaces of the middle plane. The cooling system includes a first cooling module and a second cooling system module configured for generating a plurality of first airflows and second airflows for the first processor boards and the second processor boards respectively, wherein the paths of the first airflows and the second airflows are crisscross to each other at the opposite surfaces of the middle plane.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: January 5, 2010
    Assignee: Mitac International Corp.
    Inventors: Tomonori Hirai, Mario J. D. Lee, Jyh-Ming Jong
  • Patent number: 7639903
    Abstract: A daisy-chain optical interconnection technique provides connectivity among a plurality of circuit boards. A plurality of optical cables is connected between pairs of the circuit boards to form a ring. Optical connection matrices disposed on each circuit board accept the ends of the optical cables. The optical connection matrices include optical vias to connect selected ones of the optical paths between ends of the optical cables. Unselected ones of the optical paths are coupled to optical transmitters and optical receivers on each board.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: December 29, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Robert Newton Bicknell, Pavel Kornilovich, Jong-Souk Yeo
  • Publication number: 20090314537
    Abstract: A package substrate including an outermost interlayer resin insulating layer, a pad structure formed on the outermost interlayer resin insulating layer, a conductive connecting pin for establishing an electrical connection with another substrate, the conductive connecting pin being secured to the pad structure via a solder, and via holes formed through the outermost interlayer resin insulating layer and for electrically connecting the pad structure to one or more conductive circuits formed below the outermost interlayer resin insulating layer, the via holes being positioned directly below the pad structure.
    Type: Application
    Filed: August 25, 2009
    Publication date: December 24, 2009
    Applicant: IBIDEN CO., LTD.
    Inventors: Naohiro HIROSE, Hitoshi ITO, Yoshiyuki IWATA, Masanori KAWADE, Hajime YAZU
  • Publication number: 20090309220
    Abstract: The adhesive composition of the invention comprises a radical generator, a thermoplastic resin and a urethane (meth)acrylate having two or more radical-polymerizing groups in the molecule and a weight-average molecular weight of 3000-30,000.
    Type: Application
    Filed: March 15, 2006
    Publication date: December 17, 2009
    Applicant: HITACHI CHEMICAL CO., LTD.
    Inventors: Shigeki Katogi, Hiroyuki Izawa, Houko Sutou, Masami Yusa, Tohru Fujinawa