Abstract: A memory cell that is readable through a bit line and addressable through a word line can be stressed using a method that includes addressing the memory cell, through the word line, for an addressing time. The memory cell can be stressed by applying a stress voltage to the bit line for a stress voltage time that overlaps with the addressing time for a stress time ?t. A method for testing a memory cell can include writing a data value into the memory cell, stressing the memory cell, reading a stored value from the memory cell and determining whether the stored value corresponds to the data value. A testable memory array can include at least one memory cell that is addressable through a word line and readable through a bit line and a stress circuit for applying a stress voltage to the bit line.

Abstract: A semiconductor device may include: a storage unit configured to store program codes provided through control of a processor core; and a control unit configured to perform a control operation on a semiconductor memory device according to the program codes.

Abstract: A method for operating a computing system includes: monitoring a central interface for a power event; accessing a high-speed memory for pre-shutdown data; accessing a non-volatile memory during the power event for the pre-shutdown data previously stored on the high-speed memory; selecting a multiplexer for allowing external access to the high-speed memory; and formatting the pre-shutdown data in the non-volatile memory for access through a non-disruptive interface.

Abstract: A smart memory system preferably includes a memory including one or more memory chips, and a processor including one or more memory processor chips. The system may include a smart memory controller capable of performing a bit error rate built-in self test. The smart memory control may include bit error rate controller logic configured to control the bit error rate built-in self test. A write error rate test pattern generator may generate a write error test pattern for the bit error rate built-in self test. A read error rate test pattern generator may generate a read error test pattern for the built-in self test. The smart memory controller may internally generate an error rate timing pattern, perform built-in self test, measure the resulting error rate, automatically adjust one or more test parameters based on the measured error rate, and repeat the built-in self test using the adjusted parameters.

Abstract: A semiconductor device includes a word line coupled to a mask ROM memory cell, a bit line pair coupled to the memory cell, a differential sense amplifier for amplifying the potential difference of the bit line pair, and a logic circuit for detecting whether the logic states of the bit line pair match or not. In this way, when there is a failure in the memory cell, it is possible to prevent the semiconductor device from passing the test as a result of the determination that the actual value is the same as the expected value in the test even if there is no potential difference in the bit line pair.

Abstract: The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of reading memory cells in a memory array, such as a cross point memory array. In one aspect, the method comprises providing a memory array comprising a memory cell in one of a plurality of states. The method additionally comprises determining whether a threshold voltage (Vth) of the memory cell has a value within a predetermined read voltage window. A test pulse is applied to the memory cell if it is determined that the threshold voltage has a value within the predetermined read voltage window. The state of the memory cell may be determined based on a response of the memory cell to the test pulse, wherein the state corresponds to the one of the pluralities of states of the memory cell prior to receiving the test pulse.

Abstract: A Dual In-Line Memory Module (DIMM) Solid State Drive (SSD) System-on-a-Chip (SoC) (345) is disclosed. The DIMM SSD SoC (345) can interoperate with a host memory controller (335) as though it were a traditional Dynamic Random Access Memory (DRAM) DIMM (105, 130) with system interconnect skew and on-DIMM skew, even though the DIMM SSD SoC (345) does not have on-DIMM skew. The DIMM SSD SoC (345) can include variable delay elements (422, 424, 426, 428, 430, 432, 434, 436, 438) that can replicate the delay a traditional DRAM DIMM (105, 130) experiences and that the host memory controller (335) expects, or a superior delay that minimizes system signal integrity issues, thereby increasing maximum system speed.

Abstract: An example scannable register file includes a plurality of memory cells and, a shift phase of a scan test shifts data bits from a scan input through the plurality of memory cells to a scan output. The shifting can be performed by, on each clock cycle, reading one of the plurality of memory cells to supply the scan out and writing one of the plurality of memory cells with the data bit on a scan input. To perform sequential reads and writes on each clock cycle, the scannable register can generate a write clock that, during the shift phase, is inverted from the clock used for functional operation. The write clock is generated without glitches so that unintended writes do not occur. Scannable register files can be integrated with scan-based testing (e.g., using automatic test pattern generation) of other modules in an integrated circuit.

Abstract: A non-volatile flash memory has bit lines spanning multiple blocks grouped into columns, where each block is connected along multiple regular columns and one or more redundancy columns. When there is a local column defect, so that the defect is not at the level of the whole block or global column, the portions of a column at an individual block can be remapped to a portion of the same block along a redundant column. Sections of multiple columns from different blocks can be remapped to the same redundancy column. Then a memory block includes a number of independently accessible sub-blocks, the process can also be implemented at the sub-block level. A dynamic, system level implementation is presented.

Abstract: A memory-testing device for testing a memory is provided. The memory-testing device includes a testing circuitry and a register. The testing circuitry is coupled to the memory for testing performance of the memory. The register is coupled to the testing circuitry and inputted by a testing clock signal, wherein the testing clock signal is different from an original clock signal of the memory and/or the testing circuitry. The testing clock signal is utilized for adjusting the time when the memory-testing device latches data from the memory to decrease a timing slack of the memory-testing device.

Abstract: A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.

Abstract: Shared built-in self-analysis of memory systems employing a memory array tile architecture is provided. To selectively control which memory tile among a plurality of memory tiles is accessed for a built-in self-analysis (BISA) operation, a shared BISA address issued from a shared BISA circuit includes a memory tile address. Each memory tile includes a unique fixed memory tile address that is compared to the received memory tile address of a received BISA address. If the memory tile address in the received BISA address matches the fixed memory tile address of a memory tile, the memory tile is activated to use the memory address in the BISA address to access addressed memory bit cells for analysis. Thus, if the memory system is redesigned to include additional memory tiles for increased capacity, the memory tile address size in the BISA address can be updated for addressing added memory tiles.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs commands, a test address, addresses and a precharge signal. The second semiconductor device enters an auto-precharge operation according to a combination of the commands after a read operation or a write operation and receives the test address and the precharge signal to perform an auto-precharge operation of one bank selected from a plurality of banks by the addresses.

Abstract: A method of testing a microelectronic package configured to provide memory access can include energizing terminals of the microelectronic package, the terminals including first terminals configured to carry address information and second terminals configured to carry data signals. The method can also include applying read and write test data signals simultaneously to the first and second sets of second terminals, so as to simultaneously test read and write operation in first and second microelectronic elements of the microelectronic package. The first and second microelectronic elements can be configured to provide access to memory storage array locations in the first and second microelectronic elements. The terminals can also include third terminals configured to receive a test mode input that reconfigures the first and second microelectronic elements to permit simultaneous access to memory storage array locations in the first and second microelectronic elements.

Abstract: Commands associated with one or more logical block addresses are received via a host interface of a storage device. Based on a timing and sequence of the commands, an extent of a file that contains the logical block addresses is determined, the file being stored on the storage device. The logical block addresses are managed internally as a unitary data structure based on determining an association between the logical block addresses and the file.

Abstract: Disclosed is a method for reading from a non-volatile memory (NVM) device including: retrieving a set of data from an NVM array according to a read sequence for a requested set of logical memory locations received from a host device, detecting errors in the set of data, preparing an error indicator to be output to a host device substantially upon detection of the errors and outputting the error indication in response to a command being received from the host device.

Abstract: A network equipment test device provides a user interface for user specification of a test traffic source, a test traffic destination, SUT and waypoint topology and one or more test cases. In response to receiving the specified input from the user via the interface, the test traffic source is automatically configured to send the test traffic to the destination via the SUT. The waypoint is automatically configured to measure the test traffic. When the test is initiated, test traffic is sent from the test traffic source to the test traffic destination via the SUT and the at least one waypoint. Test traffic is measured at the waypoint, and traffic measurement results are displayed on a visual map of SUT topology.

Abstract: A semiconductor memory device includes a memory cell array and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The refresh control circuit performs a normal refresh operation on the plurality of memory cell rows and performs a weak refresh operation on a plurality of weak pages of the plurality of memory cell rows. Each of the weak pages includes at least one weak cell whose data retention time is smaller than normal cells. The refresh control circuit transmits a refresh flag signal to a memory controller external to the semiconductor memory device when the refresh control circuit performs the weak refresh operation on the weak pages in a normal access mode.

Abstract: An apparatus includes first and second data pads arranged adjacently to each other in a first direction without an intervention of a pad therebetween, first and second output transistors coupled correspondingly to the first and second data pads and arranged adjacently to each other in the first direction and at least one contact plug through which a voltage is supplied to each of the first and second output transistors. The at least one contact plug is arranged between the first and second output transistors.

Abstract: A semiconductor memory device includes: a word line driving unit suitable for performing activation operations for a plurality of normal word lines and a plurality of redundancy word lines in response to test addresses; and a test control unit suitable for controlling a number of activations of each of the plural normal and redundancy word lines to be equal based on repair information corresponding to a repair target word line among the plural normal word lines during a test operation.

Abstract: In some embodiments, a system includes a memory testing circuit configured to perform a test of an internal comparator of a memory circuit by performing operations. The operations may include causing a first value to be stored at the memory circuit as a current data value. The operations may further include subsequently causing the first value to be sent to the memory circuit as a current comparison data value. The operations may further include causing the internal comparator to compare the current data value to the current comparison data value. The operations may further include receiving a current match value that indicates whether the current data value matches the current comparison data value. In some embodiments, the memory testing circuit may be configured to enable a self-test circuit to detect errors regarding functions of the memory circuit that the self-test circuit is not designed to test.

Abstract: A memory device includes a plurality of channels that respectively include memory cell arrays and local input/output lines electrically coupled to the memory cell arrays and are independently operable, shared global input/output lines electrically coupled to the local input/output lines included in the plurality of channels and having a connection relation controlled through one or more path switch circuits arranged among the plurality of channels, and the path switch circuits that control the connection relation of the shared global input/output lines according to a path control signal.

Abstract: We disclose methods, apparatus, and systems for improving semiconductor device yield and/or reliability through bias temperature instability (BTI). One device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line controls access to each pass gate of a first number of cells; a word line driver electrically connected to each word line; and a control line configured to provide an operational write voltage or a first write voltage to each word line through the word line driver. By virtue of BTI, application of the first write voltage may lead to improved stability of data desired to be read from one or more cells of the device.

Abstract: A memory self-testing device for testing a plurality of memory control units includes: a test control unit, coupled to the memory control units, generating a plurality of access request signals and a plurality of sets of data; a channel control unit, coupled to the test control unit and the memory control units, determining a leading feedback signal among a plurality of feedback signals; and a data control unit, coupled to the test control unit and the memory control units, storing the sets of data, and transmitting the sets of data to the memory control units according to a plurality of read/write signals. The feedback signals and the read/write signals are generated by the memory control units in response to the access request signals. The test control units generate the sets of data according to the leading feedback signal.

Abstract: A semiconductor device may include: a first latch configured to store data outputted from a memory cell during a first operation; and a fail detection circuit configured to detect a fail by comparing the data outputted from the memory cell to the data stored in the first latch through a second operation performed at a predetermined time after the first operation.

Abstract: A semiconductor device may include: a fuse array including a plurality of fuses; a voltage generation unit suitable for generating a first measurement voltage having a preset level; and a measurement unit suitable for supplying the first measurement voltage to a sourcing node of the fuse array and a second measurement voltage, which is provided from an external through a first pad, to a sinking node of the fuse array, and outputting a current, which is caused by voltage difference between the first and second measurement voltages and passes through one or more of the multiple fuses, through the first pad.

Abstract: Provided are nonvolatile memory devices and a driving method of the nonvolatile memory devices. The nonvolatile memory devices may include a plurality of memory banks, a read global bit line shared by the plurality of memory banks, a write global bit line shared by the plurality of memory banks, a read circuit connected with the read global bit line and performing a read operation, and a discharge control circuit connected with the write global bit line and primarily discharging the write global bit line during an initialization interval after a power-up operation.

Abstract: An IO structure, method, and apparatus are disclosed for using an IEEE™ 1149.1 boundary scan latch to reroute a functional path. The method for a chip using IEEE™ 1149.1 boundary scan latches may include using the IEEE™ 1149.1 boundary scan latches for testing IO on the chip in a test mode. The method may also include using information stored in the IEEE™ 1149.1 boundary scan latches to route signals around a failing path in a functional mode.

Abstract: A storage control device that controls a solid state drive group including two or more solid state drives sharing data storage includes a detector that detects a wear state of each of the solid state drives, a separation controller that separates a solid state drive having a wear value, which represents a wear state, exceeding a first threshold among the solid state drives, and an enlargement controller that, when detecting a solid state drive having a wear value, which represents a wear state, exceeding a second threshold less than the first threshold among the solid state drives in the solid state drive group, enlarges a difference in a wear value, which represents a wear state, between the solid state drive having the wear value exceeding the second threshold and a remainder of the solid state drives.

Abstract: For test virtual volume operation testing, an identification module determines if an input/output (I/O) operation for a test virtual volume is directed to volume contents data. A disposition module executes the I/O operation in response to the I/O operation being directed to the volume contents data and declines the I/O operation in response to the I/O operation not being directed to the volume contents data.

Abstract: Memory devices storing particular data, systems containing such memory devices and methods of testing such memory devices. The memory devices include an array of memory cells containing particular data, and control circuitry configured to control operations of the array of memory cells.

Abstract: User data or constantly toggling functional critical path timing sensors measure delays in actual critical paths that include a RAM. Variable resistors or variable capacitors are added to RAM bit lines for redundant cells to delay bit-line sensing by sense amplifiers. The sense amplifiers' delayed data is compared to non-delayed data from normal selected RAM cells to detect timing failures. Variable resistors or capacitors may also be added between the write drivers and bit lines to delay writing data into the redundant cells. A margin delay adjustment controller sweeps margin delays for constantly toggling paths until failures. A margin delay is then adjusted and added to functional critical paths that carry user data. Functional critical path timing sensors test setup time with the added margin delay. Timing failures cause VDD to increase, while a controller reduces VDD when no failures occur. Actual delays through the RAM adjust VDD.

Abstract: A method for electrically testing devices fabricated on successive frames of a web of substrate, each frame including a plurality of fiducial marks. A digital imaging system is used to capture a digital image of a frame, which is analyzed to determine spatial relationships between positions of a set of test pads and positions of the fiducial marks. The frame is advanced to an electrical test fixture which includes a set of test probes adapted to make electrical contact with the test pads. A fiducial sensing system including a plurality of fiducial sensors is used to determine positions of the fiducial marks. The position of the electrical test fixture is adjusted responsive to the determined spatial relationships and the determined fiducial mark positions so that the test probes are aligned with corresponding test pads, and an electrical test of the device is performed.

Abstract: The present disclosure relates to thermal disturb as heater in cross-point memory. An apparatus includes a memory controller. The memory controller is configured to identify a target memory cell in response to at least one of a selection failure and a set fail memory read error associated with the target memory cell. The memory controller is further configured to apply a first sequence of recovery pulses to a first number of selected adjacent memory cells adjacent the target memory cell, the first sequence of recovery pulses configured to induce heating in the target memory cell.

Abstract: Various structures having a fuse and methods for forming those structures are described. An embodiment is a method. The method comprises attaching a first die to a first side of a component using first electrical connectors. After the attaching, at least one of (i) the first die comprises a first fuse, (ii) the first side of the component comprises a second fuse, (iii) a second side of the component comprises a third fuse, the second side being opposite the first side, or (iv) a combination thereof. The method further comprises after the attaching the first die to the first side of the component, blowing the first fuse, the second fuse, the third fuse, or a combination thereof.

Abstract: A semiconductor memory device includes a first global line suitable for inputting/outputting data from/to a first bank, a second global line suitable for inputting/outputting data from/to a second bank, a multi-purpose register (MPR) suitable for loading data having a predetermined value on the first global line in a training mode, a first data input/output (I/O) unit suitable for inputting/outputting data between one of the first and second global lines and a first data pad and selectively transferring data loaded on the first global line to the second global line in response to a bandwidth option in the training mode, and a second data I/O unit enabled in response to the bandwidth option, suitable for inputting/outputting data between the second global line and a second data pad.

Abstract: A first input of a sense amplifier is connected to a first bitline, a second input of the sense amplifier is connected to a second bitline, a third input of the sense amplifier is coupled to a third bitline. The sense amplifier provides at an output an indicator of a storage state of a memory cell connected to the first bitline based upon information provided to the sense amplifier via the first, second, and third bitlines.

Abstract: An electrical testing system is adapted to perform electrical tests on devices fabricated on successive frames of a web of substrate, each frame including a plurality of fiducial marks. A digital imaging system captures a digital image of a frame, which is analyzed to determine spatial relationships between positions of a set of test pads and positions of the fiducial marks. The frame is advanced to an electrical test fixture which includes a set of test probes adapted to make electrical contact with the test pads. A fiducial sensing system including a plurality of fiducial sensors determines positions of the fiducial marks. The position of the electrical test fixture is adjusted responsive to the determined spatial relationships and the determined fiducial mark positions so that the test probes are aligned with corresponding test pads, and an electrical test of the device is performed.

Abstract: A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.

Abstract: A semiconductor device includes a latch circuit suitable for storing a test result; a non-volatile memory circuit suitable for storing information used for an operation of the semiconductor device; a decoding unit suitable for generating one or more internal program commands by using one or more control signals; and a control unit suitable for programming information in the non-volatile memory circuit in response to the test result stored in the latch circuit when the internal program commands are activated.

Abstract: A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.

Abstract: In a system on chip (SOC) device, continuity of a memory repair signature chain, which is accessible by all enabled memory systems, is provided, even when certain memory systems are gated (off) for certain SOC configurations. A mechanism for converting between compressed and uncompressed memory repair data within the repair chain is provided so that memory systems that support either uncompressed memory repair data (such as ternary content addressable memories) or compressed memory repair data can be incorporated in the SOC.

Abstract: An SRAM with buffered-read bit cells is disclosed (FIGS. 1-6). The integrated circuit includes a plurality of memory cells (102). Each memory cell has a plurality of transistors (200,202). A first memory cell (FIG. 2) is arranged to store a data signal in response to an active write word line (WWL) and to produce the data signal in response to an active read word line (RWL). A test circuit (104) formed on the integrated circuit is operable to test current and voltage characteristics of each transistor of the plurality of transistors of the first memory cell (FIGS. 7-10).

Abstract: Systems and methods are provided for testing a non-volatile memory, such as a flash memory. The non-volatile memory may be virtually partitioned into a test region and a general purpose region. A test application may be stored in the general purpose region, and the test application can be executed to run a test of the memory locations in the test region. The results of the test may be stored in the general purpose region. At the completion of the test, the test results may be provided from the general purpose region and displayed to a user. The virtual partitions may be removed prior to shipping the electronic device for distribution.

Abstract: Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller.

Abstract: A failure diagnosis circuit includes a multiplexer and a controller. The multiplexer receives address signals, and selectively outputs one of the address signals to an addressable module in response to a selecting signal. The controller generates a first one of address signals and the selecting signal. A built-in self-test circuit generates the second address signal. The addressable module includes addressable components responsive to the address signal. The controller processes the output of the addressable module responsive to the address signal to make a failure diagnosis. The built-in self-test circuit performs signature analysis on the read out output of the addressable module.

Abstract: A memory device to correct a defect cell generated after packing is performed includes a memory cell array in which a plurality of memory cells are arranged, a repair circuit unit including a first storage unit to store defect cell information in the memory cell array, and a fuse circuit unit including a second storage unit that is programmed according to the defect cell information stored in the first storage unit. The first storage unit includes a volatile memory device, and the second storage unit includes a non-volatile memory device.

Abstract: A resistance variable memory apparatus may include: a memory cell array; and a read circuit unit configured to receive a cell current, generate a digital code by repeating a cyclic analog-to-digital conversion (ADC) process a designated number of times, generate read data from the digital code, and output the generated read data during a normal read mode for the memory cell array, and to generate test data corresponding to the cell current and output the generated test data during a test read mode for the memory cell array.

Abstract: The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP.

Abstract: For performing advanced memory test diagnostics, an apparatus, method, and computer program product are disclosed. The apparatus may include a processor, a memory that stores code executable by the processor, an address space module that identifies an address space having a plurality of blocks of memory addresses, a memory diagnostic module that performs, at least three times, a memory test procedure using a block pattern, wherein a first block pattern is used the first time, a second block pattern is used the second time, and a third block pattern is used the third time, and a memory fault module that determines the presence of a memory fault based on results of the memory test procedures.