Abstract: A method and system for upgrading a programmable battery unit in a mobile information handling system. The method and system make use of unique address words, checks, and comparisons stored in memory in order to allow upgrades in the battery unit. Non-reprogrammable section provides security in calculating checksums of addresses in the non-reprogrammable section and programmable section of memory.

Abstract: A semiconductor memory with a memory core for dynamically holding data in which a data collision at the time of the semiconductor memory making the transition from a standby state to a nonstandby state is prevented. A first buffer circuit inputs an enable signal for controlling a standby state or a nonstandby state. A second buffer circuit outputs a predetermined logic signal or a read/write signal for controlling the reading of data from or the writing of data to the memory core in accordance with the enable signal. A third buffer circuit outputs an inverted signal obtained by inverting the logic signal or the read/write signal in accordance with the enable signal. A control circuit controls the reading or writing of the data by the read/write signal outputted from the second buffer circuit. A data output control circuit controls the inputting of the data from or the outputting of the data to the outside by the inverted signal or the read/write signal outputted from the third buffer circuit.

Abstract: An SRAM device and a method of powering-down an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array, (2) peripheral circuitry coupled to the SRAM array having voltage domains defined by a boundary and (3) a power-down voltage controller coupled to the SRAM array and the peripheral circuitry that separately regulates voltages of the SRAM array and the peripheral circuitry to reduce leakage current of the SRAM array and the peripheral circuitry at the boundary during a sleep mode.

Abstract: A semiconductor device that achieves high speed and low power consumption that can be used in a real-time system by preventing held data from disappearing at the time of power shutdown and sharply rising power while also preventing a through-current at the time of power resumption. During normal operation, the switch is on, and the clock generating circuit and the data holding circuit are operated with the first power supply voltage. When data holding is required at the time of power shutdown, the switch and the first power supply voltage supplied to the logic circuit are turned off, and the clock generating circuit and the data holding circuit are operated with the second power supply voltage.

Abstract: A semiconductor memory device is provided which effectively reduces a consumption of current of a system of circuits associated with refresh operations. A control signal circuit 2 controls n-channel transistors 3C, 4B to be in an OFF-state based on an internal chip select signal SCI in an interval time period between the refresh operations, wherein the n-channel transistors 3C, 4B are connected between the system of circuits associated with refresh operations (an internal voltage-down circuit 3 and a boost circuit 4) and the ground, so as to break down a leak path of the system of circuits associated with refresh operations for reducing the leakage of current. At a timing of starting the refresh operation by triggering a timer, the internal chip select signal SCI is transitioned to a high level for supplying a ground voltage to the internal voltage-down circuit 3 and the boost circuit 4.

Abstract: A method and apparatus of reducing the time for enabling a dynamic random access memory (DRAM) upon initial application of power, comprises generating an internal RAS signal upon initial power up to generate internal voltages. The internal RAS pulse is asserted after a short time delay ends. After the internal RAS pulse is asserted, voltages on a digit line pair are amplified with a sense amplifier. Then, the amplified voltages on the digit line pair are equilibrated with an equilibration circuit. The equilibrated voltage is also coupled through the equilibration circuit to charge a common plate of a memory cell capacitor.

Abstract: An SRAM device and a method of powering-down an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array coupled to an SRAM array low voltage source that provides a low SRAM array supply voltage VSB to the SRAM device and (2) main column peripheral circuitry having main pre-charge circuitry free of an SRAM header, coupled to the SRAM array by bit lines and coupled to a sleep mode controller through an associated main column peripheral driving circuitry that is configured to isolate the bit lines from a power supply during a sleep mode.

Abstract: A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption.

Abstract: When the CPU writes data into a memory, a 0 detection circuit detects the number of bits having the value 0 from the data. When the number of bits with 0 is equal to or larger than the number of bits with 1, the data output from the CPU is provided to the memory under control of a selector. When the number of bits with 0 is fewer than the number of bits with 1, the data output from the CPU is inverted and provided to the memory under control of the selector. Accordingly, the rewriting frequency of each memory cell from 0 to 1 or from 1 to 0 in the memory can be reduced in average. Thus the power consumption of the memory in a data writing mode can be reduced.

Abstract: A power control unit activates a control signal ST for a circuit block to be set to a standby state before turning off power of the circuit block or a whole chip, and saves an operation result of data processing of the circuit block into a memory unit. When the power is again supplied to the circuit block in the standby state, the power control unit activates a control signal RES after the power supply is started and restores the data saved in the memory unit to the circuit block. Flip-flops in the circuit block are connected in series when the saving or restoring of data is performed, and perform a data transfer operation with a path different from that in a normal operation. Therefore, a semiconductor device can be provided which can rapidly transit to a standby mode having reduced current consumption while holding internal information.

Abstract: A circuit to operate a semiconductor integrated circuit memory device having memory cells in a deep power down mode. The power down circuit includes a transistor switch connected between an external voltage source and the device memory cells and peripheral circuits, a generator for providing a control voltage of a first level different from the value of the external voltage, and a multiplexer that receives as one input the control voltage and as a second input the external voltage. The multiplexer has a selected output of one of the control voltage and external voltage that is applied to a control electrode of the transistor switch. When deep power down mode operation is required, the multiplexer responds to a power down control flag signal to apply the external voltage to the transistor control electrode to turn off the transistor and block application of the external voltage to the memory cells and peripheral circuits.

Abstract: One embodiment of the present invention provides a random access memory (RAM) including an array of memory cells arrange in a plurality of rows and columns, wherein access of each row is based on a wordline signal, and a wordline circuit. The wordline circuit includes a voltage node receiving a positive voltage from an external power source, a decoding node receiving a decoding signal having a state representative of an idle mode, and a driver circuit providing to at least one of the rows of memory cells a wordline signal based on the decoding signal and forming a current leakage path from the voltage node to a reference node when the decoding signal state indicates the idle mode.

Abstract: A memory device responsive to standby mode commands for reducing internal operational power on a memory device is disclosed. The memory device includes a circuit for reducing power during a standby mode with the circuit including a reference with at least first and second reference signals. The circuit also includes a switching device for switching between the first and second reference signals in response to the standby mode command and further controls an internal operational power regulator to adjust between normal and low-power outputs for further reducing the power to portions of the memory device.

Abstract: A word line driver includes multiple current paths for driving a word line of a memory device to a negative voltage and a positive voltage. When driving the word line from the negative voltage to the positive voltage, the word line driver uses a first current path to drive the word line to the positive voltage in one stage. When driving the word line from the positive voltage to the negative voltage, the word line driver drives the word line from the positive voltage to ground using the first current path in a first stage. In a second stage, the word driver further drives the word line from ground to the negative voltage in using a second current path.

Abstract: In accordance with the present invention, in order to reduce an averaged consumption current in a stand-by state, there is provided a semiconductor memory device including a memory cell array area which is divided into a plurality of areas, wherein the semiconductor memory device includes: at least one specific area setting unit being electrically coupled to said memory cell array area and adopted to set at least one area defined in said plurality of areas in accordance with an optional criterion; and at least one refresh operation control unit being electrically coupled to said memory cell array area and adopted to perform a refresh operation to the specific area based on at least one kind of specific refresh control signal, which is longer in cycle than a basic refresh control signal at least in a predetermined state of the semiconductor memory device.

Abstract: A semiconductor integrated circuit device includes connected TC unit type ferroelectric memory which includes series connected memory cells each having a cell transistor having a source terminal and a drain terminal and a ferroelectric capacitor inbetween the two terminals, a first power supply circuit which generates a first power supply potential supplied to the gate of the cell transistor when the cell transistor is in a standby state, and a second power supply circuit. The second power supply circuit generates a second power supply potential supplied to the source or drain of the cell transistor and starts operating following the start-up of the first power supply circuit after a power-on.

Abstract: A current drive circuit operates receiving higher voltage than in a waiting mode at source terminal of a P-channel first driver transistor, when supplying a current to a node connected to a load circuit. In accordance with the rising source potential of the first driver transistor, the gate potential output to the first driver transistor by a gate potential control circuit rises. When the first and second driver transistors are off, a precharge circuit configured with a P-channel MOS transistor precharges the node to a prescribed potential. As a result, the current drive circuit is provided with increased reliability of the gate insulating films of the driver transistors without decreasing the driving current.

Abstract: A synchronous semiconductor memory device includes a memory cell array and a command decoder. In the memory cell array, dynamic memory cells are arranged in a matrix form. The command decoder decodes a plurality of commands in synchronism with an external clock signal. The plurality of commands are set by combinations of logical levels of a plurality of control pins at input timing of a first command and at input timing of a second command one cycle after the input timing of the first command. The command decoder includes a first decode section which determines a read operation, a second decode section which determines a write operation, and a third decode section which determines an auto-refresh operation. Setting of an auto-refresh command is determined only by a combination of the logical levels of the plurality of control pins at the input timing of the first command.

Abstract: A word line driver circuit for a semiconductor memory device. One or more transistors in the driver circuit are fabricated such that they are susceptible, under certain conditions, to gate-induced diode leakage (GIDL). One terminal of the transistors are coupled to a local supply node, which during standby conditions when the word line driver circuit is not driving a word line, is maintained at a voltage less than that of a global power supply node. In one embodiment, the local power supply node is coupled to the global power supply node by means of at least one decoupling transistor receiving a control signal at its gate and by a vt-connected transistor, such that the voltage on the local power supply node is maintained at a level not exceeding one transistor threshold voltage less than the global power supply node voltage when the decoupling transistor is off.

Abstract: The present invention relates to a data processing system comprising a processor (100), at least one data memory (132), at least one program memory (134) and a main bus (110), common to the data and program memories and connecting these memories to the processor, characterized in that at least one of the memories has a rapid-access mode and in that the device also comprises a distribution interface (120) between the main bus (110) and the memories in order to alternately put in communication, by means of the main bus, one from among the data memory and the program memory with the processor, in a so-called active-access mode, and to keep the other memory in a so-called passive-access mode allowing subsequent rapid access.

Abstract: A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.

Abstract: A high-speed accessible non-volatile memory device including: a memory cell array which has a plurality of memory cells arranged in a row direction and a column direction, and a precharge voltage supply section. The memory cell has a source region, a drain region, a word gate and a select gate disposed to face a channel region provided between the source region and the drain region, and a non-volatile memory element formed between the word gate and the channel region. The precharge voltage supply section supplies a precharge voltage to all the word gates in the memory cell array during standby mode.

Abstract: A semiconductor integrated circuit is provided including a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The integrated circuit includes an interblock interface circuit provided on a signal path from the elected circuit block to other circuit blocks, wherein a single output of the interblock interface circuit is branched out to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission to other circuit blocks and includes a storage unit for storing a signal right before the power cut.

Abstract: Reducing leakage current when a circuit contains a series of CMOS transistors. The probability that each input signal (connecting to the gate terminal of the corresponding CMOS transistor) will be at a logical value which turns off the corresponding CMOS transistor is determined. A CMOS transistor with a high threshold voltage may be connected to receive an input signal with a high probability to reduce the aggregate leakage current in the circuit. The approach may be used in any environments such as synthesis tools and also manual design methodologies.

Abstract: A semiconductor memory that can make the transition from a power-down state in a synchronous mode to an asynchronous mode without setting by a control register and that needs no extra circuits. A state selection section chooses, by selecting an existing internal signal the level of which changes in the power-down state or an existing internal signal the level of which does not change in the power-down state in accordance with a state selection signal inputted in advance and passing a signal selected to a synchronous/asynchronous mode setting section, whether the semiconductor memory should make the transition from the power-down state to a standby state in the synchronous mode or a standby state in the asynchronous mode. In accordance with the selection by the state selection section, the synchronous/asynchronous mode setting section generates a signal for causing the semiconductor memory to make the transition between the synchronous mode and the asynchronous mode.

Abstract: A zero power standby mode in a memory device used in a system, such as a battery powered hand held device. By disconnecting the internal power supply bus on the memory device from the external power supply during standby mode, the junction leakage and gate induced drain leakage can be eliminated to achieve a true zero-power standby mode. A p-channel field effect transistor (FET) may be used to gate the external power supply such that the internal power supply bus on the memory device may be disconnected from the external power supply.

Abstract: A method for controlling a semiconductor memory in which mode register can be set in burst mode. To set an operation mode in burst mode, the semiconductor memory is changed first from the burst mode, through power-down mode, to standby mode of non-burst mode. Then the semiconductor memory is changed to mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.

Abstract: A method for operating a cache having a sleep mode is provided. The cache is located within a memory hierarchy of a computer system, and the method is comprised of receiving a first cache request, and servicing the first cache request. A sleep mode signal is asserted in response to completion of the servicing of the first cache request. Thereafter, a second cache request is received, and the sleep mode signal is deasserted in response to receiving the second cache request. Thereafter, the second cache request is serviced.

Abstract: A voltage booster device to selectively assume an active status and a stand-by status with a first terminal to assume a respective electric potential and associated to a first capacitor, a second terminal associated to a second capacitor and selectively connectable to the first terminal, and a discharge circuit for discharging the first capacitor thus reducing the electrical potential of the first terminal, the discharge circuit being activated when said device is in the stand-by status and the second terminal is disconnected from said first terminal.

Abstract: A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.

Abstract: A method, system, and apparatus for maintaining the contents of a self-refreshable memory device during periods of data processing system reset is provided. In one embodiment, a refresh controller receives an indication that the data processing system is being reset. If necessary, the refresh controller modifies the signal from a memory controller to the memory device such that the memory device is placed in a self-refresh mode. The refresh controller keeps the memory device in the self-refresh mode until the data processing system re-enables external refresh signals.

Abstract: The invention provides a semiconductor integrated circuit device on which a RAM macro capable of selecting an operation mode adapted to improved ease of use, response, or low power consumption or selecting an input setup value is mounted. In a first operation mode of a RAM macro, a timing of receiving an input signal is set as a first timing. In a second operation mode, a timing of receiving an input signal is set to a second timing later than the first timing. In a semiconductor integrated circuit device including an input circuit for receiving an input signal and a decoder circuit for decoding an output signal of the input circuit, the input circuit is activated on the basis of a first signal and the decoder circuit is activated on the basis of a second signal.

Abstract: A semiconductor integrated circuit device includes a plurality of memory cells, a first voltage generating circuit for generating a first voltage, a second voltage generating circuit for generating a second voltage lower than the first voltage and a switching circuit for changing over the first and second voltages in response to a control signal so as to output the first and second voltages to the memory cells in a normal operation mode and a data retention test mode, respectively.

Abstract: A semiconductor integrated circuit device includes connected TC unit type ferroelectric memory which includes series connected memory cells each having a cell transistor having a source terminal and a drain terminal and a ferroelectric capacitor inbetween the two terminals, a first power supply circuit which generates a first power supply potential supplied to the gate of the cell transistor when the cell transistor is in a standby state, and a second power supply circuit. The second power supply circuit generates a second power supply potential supplied to the source or drain of the cell transistor and starts operating following the start-up of the first power supply circuit after a power-on.

Abstract: A circuit for controlling a reference node in a sense amplifier switchable between an operating mode and a stand-by mode is provided. The reference node provides a reference voltage in the operating mode. The circuit may include circuitry for bringing the reference node to a starting voltage upon entry into the stand-by mode, circuitry for keeping the reference node at a pre-charging voltage in the stand-by mode, and circuitry for providing a comparison voltage closer to the pre-charging voltage than the starting voltage. Pulling circuitry may also be included for pulling the reference node toward a power supply voltage. Further, a controller may activate the pulling circuitry upon entering the stand-by mode, and disable the pulling circuitry when the voltage at the reference node reaches the comparison voltage.

Abstract: A metering data preservation and storage methodology, including steps for protecting data during periods in which power is lost to the meter, is provided. In particular, a methodology for using non-volatile flash memory structures is used in association with various volatile memory structures for the storage and preservation of metering data acquired from a solid-state utility meter. The methodology includes the use of the volatile memory structures for the temporary storage and alteration of the measured and calculated metering data so as to avoid an effective reduction in the lifespan of the non-volatile memory structure which can only be written, erased and rewritten to a finite number of times. Further, such usage reduces costs associated with the maintenance and incorporation of such memory types in the meter. The methodology further includes the use of the non-volatile flash memory as a permanent storage medium for the acquired metering data during power loss to the meter.

Abstract: Ramping voltage circuits are described for augmenting or supplying a higher power-up slope upon initial power-up or a wake-up transition from a period of dormancy to a semiconductor memory device. Such ramping voltage circuits are responsive to a power-up signal, and are capable of increasing by at least two orders of magnitude the power-up slope, thereby enabling far quicker device turn-on. In one embodiment, a level shifter is used to ramp up the power-on voltage. In another embodiment, the internal voltage line is effectively shorted to an external voltage line via a power-up turned-on PMOS or depletion-type NMOS transistor.

Abstract: A method for controlling power for a semiconductor storage device and the semiconductor storage device are provided which enable power consumption to be greatly reduced in a standby state. The power control method uses an ultra-low power consumption mode in which power control can be exerted in the standby state. In the ultra-low power consumption mode, a burst self-refresh state, power-OFF state, and power-ON state are provided. In the burst self-refresh state, memory cells are refreshed in a centralized manner. In the power-OFF state, an internal power source circuit can be partially turned OFF. In the power-ON state, internal power sources having been partially turned OFF are turned ON. Therefore, it is possible to greatly reduce power consumption in the standby state.

Abstract: A power-source controller for reducing current consumption while a DRAM is in standby, includes a mode detection circuit inverting a disable signal having an L-level under the enable state and having an H-level under the disable state; an internal-power-source driver circuit having first and second transistors; and an internal-power-source reference circuit setting first and second driver control signals respectively to L-level and H-level when an L-level disable signal is input to turn on the first transistor and turn off the second transistor, supplying an external-power-source voltage as an internal-power-source voltage, setting the first driver control signal to H-level when an H-level disable signal is input, controlling the level of the second driver control signal to turn off the second transistor and control the first transistor, and supplying an internal power-source voltage lower than the external-power-source voltage.

Abstract: Methods and devices for a memory system are disclosed. A digital memory device can receive power-down commands during the pendency of an active-mode command such as a burst read or write, that is, “early”. The device shuts down some circuitry, such as address and command registers, immediately upon receipt of the early power-down command. Other device components, e.g., those involved in servicing the burst read or write, remain active at least until their portion of the command has been completed. In some embodiments, the early power-down command can be issued concurrently with an active-mode command as an option to that command, freeing a memory controller from having to schedule and issue power-down commands separately. Significant power savings, as compared to those obtained with prior-art memory device power-down modes, are possible.

Abstract: According to one embodiment, a memory cell is disclosed. The memory cell includes a first PMOS transistor, a first NMOS transistor coupled to the first PMOS transistor, a second PMOS transistor and a second NMOS transistor coupled to the first PMOS transistor. The first and second PMOS transistors receiving a bias control signal.

Abstract: A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.

Abstract: A refresh circuit having a variable restore time according to an operating mode of a semiconductor memory device and a refresh method of the same is provided. The refresh circuit includes a refresh pulse generating unit for receiving a clock signal to generate first and second refresh signals, a standby refresh signal generating unit for receiving the second refresh signal and a chip select signal to generate a standby refresh signal, the chip select signal representing an active state and a standby state of the semiconductor memory device, and a word-line pulse generating unit for receiving the first refresh signal and the standby refresh signal to generate a word-line driving signal. A pulse width of the word-line driving signal generated at the standby state is longer than that generated at the active state resulting in a sufficient refresh time at each memory cell.

Abstract: A booster circuit for a non-volatile semiconductor memory device has a drive control circuit. At a power supply ON time or at a reset time, in response to an externally input power supply ON/reset signal ON/RS, the drive control circuit does not drive a weak charge pump but drives a strong charge pump, which has a greater current capacity than that of the weak charge pump, even in a standby mode. This arrangement enables a boosted voltage HV to quickly rise from 0 V to a standby voltage, thus desirably shortening an initial access permission time at the power supply ON time or at the reset time.

Abstract: The present invention achieves technical advantages as embodiments of an SRAM cell (20, 30) having the bit line voltage (BLB/BLB) controlled during standby, such as allowing the bit line to float allowing the bit line voltage to be established by balance of leakage currents to the minimum leakage through the bit line. Advantageously, a controller (22, 32) also controls voltages of supplies Vdd, Vss and the n-well (Vnwell) voltage. The controller reduces a voltage differential between the supply voltage Vdd and voltage Vss in the standby mode. In one embodiment, the bit line may be tied to the reference voltage Vss, and a time delay may be introduced to reduce the possibility of using more charge in switching than that saved.

Abstract: A method and apparatus of reducing the time for enabling a dynamic random access memory (DRAM) upon initial application of power, comprises generating an internal RAS signal upon initial power up to generate internal voltages. The internal RAS pulse is asserted after a short time delay ends. After the internal RAS pulse is asserted, voltages on a digit line pair are amplified with a sense amplifier. Then, the amplified voltages on the digit line pair are equilibrated with an equilibration circuit. The equilibrated voltage is also coupled through the equilibration circuit to charge a common plate of a memory cell capacitor.

Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ss1 of the driver MOS transistors in the memory cells.

Abstract: A word line driver includes multiple current paths for driving a word line of a memory device to a negative voltage and a positive voltage. When driving the word line from the negative voltage to the positive voltage, the word line driver uses a first current path to drive the word line to the positive voltage in one stage. When driving the word line from the positive voltage to the negative voltage, the word line driver drives the word line from the positive voltage to ground using the first current path in a first stage. In a second stage, the word driver further drives the word line from ground to the negative voltage in using a second current path.

Abstract: A semiconductor storage having the same memory cells as a DRAM, operating in SRAM specifications, and having advantages such as a small chop size, a low power consumption, a low manufacturing cost, no access delay due to skew, and no memory cell breakdown. An ATD circuit (3) generates a one-shot pulse added to an address change detection signal (ATD) from a change of the address (Address) supplied from external. By combining one-shot pulse produced for each bit of the address, only one one-shot pulse is generated even if the address includes skew. A memory cell is refreshed by using a refresh address (R_ADD) generated by a refresh control circuit (4) during the time when a one-shot pulse is generated. At the fall of the one-shot pulse, a latch control signal (LC) is generated, and the address is taken in a latch (2) so as to access a memory cell array (6).

Abstract: A memory controller is disclosed, in which upon receipt of an access request from a device, the memory controller activates a page designated by a row address of a first bank at a predetermined memory cycle, based on the access request. After that, before the read access to a page of the first bank, a second bank next to be accessed is precharged. In the case where a page mishit occurs due to the access from the first bank to the second bank by the graphic processing after the access to the first bank by the read operation, the memory controller activates the second bank immediately without precharging.