Abstract: An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.

Abstract: An apparatus comprising a first portion, a second portion and a processor. The first portion is configured to generate a count signal in response to a number of oscillations of a clock signal. The first portion is powered by an unswitched power source. The second portion is configured to generate an interrupt signal in response to the count signal and a predetermined stored value. The second portion is powered by a switched power source. The processor is configured to (i) receive the interrupt signal and (ii) generate the switched power.

Abstract: A memory device includes at least one memory array having a plurality of memory cells addressed by a plurality of word lines and bit lines, and coupled between a power line and a ground line. A word line decoder is coupled to one end of the word line for selecting the word lines in response to input signals. A voltage control circuit is coupled to another end of the word line for connecting the word line to a ground voltage when the memory device is in a sleep mode, wherein the voltage control circuit is supplied by DC power.

Abstract: A memory module includes module-internal command/address bus lines that are terminated on the memory module by terminating resistors and a terminating voltage. The memory module also includes switches to disconnect the terminating resistors during quiescent states of the memory module in which no activity by the memory module is expected. Therefore, power consumption of the memory module is considerably reduced during the quiescent state.

Abstract: A driver circuit for an integrated circuit device includes a transistor that has a gate terminal, a source terminal, and a bulk substrate terminal. The source terminal is connected to the bulk substrate terminal. A pull-up circuit is connected between a power supply node and the source terminal. The pull up circuit is configured to increase a voltage at the source terminal and the bulk substrate terminal of the transistor responsive to a control signal.

Abstract: A semiconductor memory device may include an oscillator circuit for generating an oscillation signal that is varied based on mode of operation, and a word line enable circuit for generating a word line enable signal in response to the oscillation signal. The device may also include a control circuit to control the oscillator circuit and the word line enable circuit, so as to control a pulse width of the word line enable signal and period of the oscillation signal, based on a change in operation mode of the device.

Abstract: An SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode is provided. In one embodiment, the SRAM device includes a hierarchical grouping of memory cells of memory cells and biasing circuitry, coupled to the hierarchical grouping of memory cells, configured to bias a subset of the set based on a memory address associated therewith. In another embodiment, a method includes receiving a memory address associated with the hierarchical grouping of memory cells and biasing a subset of the hierarchical grouping of memory cells based on the memory address.

Abstract: A power (voltage) switching circuit in a semiconductor memory device, capable of reducing leakage current in a standby mode of operation and shortening the wake-up time when a standby mode is switched to an operation mode. The power (voltage) switching circuit comprises a first power switch, a second power switch, and a third power switch operatively connected to at least one bitline in a memory cell array, configured to selectively output, as a cell power voltage, a dynamically selected one of a first power supply voltage, a second power supply voltage, and a third power supply voltage, respectively in response to a first, second or third applied switch control signals. The second power supply voltage being higher than the first power supply voltage and, the third power supply voltage being lower than the first power supply voltage.

Abstract: A device and method for increasing the read stability of a memory device includes sizing a sleep transistor according to a size ratio of the transistor relative to a driver transistor forming part of the memory device based on a static noise margin value. A leakage reduction circuit and method includes reducing a voltage via a current leakage of a transistor to track the leakage of the memory cells and generating a sleep signal if the voltage drops below a predetermined threshold.

Abstract: Method and apparatus for assessing a time interval during which a refresh device can be maintained in a self-refresh mode by an associated energy source. The refresh device is initially operated in a self-refresh mode to maintain the device in a selected state. The time interval during which the refresh device can be subsequently maintained in the refresh mode is next determined in relation to an energy requirement value obtained during the self-refresh mode and an energy capacity value from the associated energy source. The energy capacity value is preferably obtained by fully discharging the associated energy source. Preferably, the refresh device is characterized as a dynamic random access memory (DRAM), and the associated energy source is characterized as a rechargeable backup battery. A selected test pattern is preferably written to the refresh device and maintained thereby during the self-refresh mode.

Abstract: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.

Abstract: A semiconductor device of this invention includes a first circuit for initializing a predetermined circuit in accordance with the level of a power source voltage, a second circuit for controlling the output from the first circuit by activation or deactivation, and an activation control circuit for activating or deactivating the second circuit in accordance with external input.

Abstract: A clock control device includes a set circuit for triggering an input address in response to an internal command signal to output a first address, a shift register including a plurality of flip-flops connected in series wherein some of the flip-flops perform a flip-flop operation of the first address in synchronism with an internal clock to provide a second address and the remaining flip-flops sequentially conduct a flip-flop operation of the second address in synchronism with a synchronous clock to produce an internal address, an active signal generator for outputting an active signal based on state of an active control signal indicating whether or not each bank is activated and a precharge control signal, and a clock generator for generating the synchronous clock depending on the internal clock and the active signal.

Abstract: An SRAM device and a method of operating an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array coupled to row peripheral circuitry by a word line and coupled to column peripheral circuitry by bit lines and (2) a sleep mode voltage controller configured to provide both an array high supply voltage VADD that is lower than a high operating voltage VDD and an array low supply voltage VASS that is higher than a low operating voltage VSS to the SRAM array during a sleep mode.

Abstract: The present invention provides a system for reducing row periphery power consumption in a semiconductor memory device, particularly during sleep mode operation. A memory device (100) according to the present invention has a row (106) of memory cells and driver circuitry (102) preceding the row of memory cells. The present invention provides an intervention circuit (114) instantiated within the driver circuitry proximal to the row of memory cells. The intervention circuit is operated to hold the row of memory cells at a desired state, while the driver circuitry (108, 110) preceding the intervention circuit is powered down.

Abstract: An internal power supply voltage generating circuit of semiconductor memory devices configured such that only a predetermined internal power driver is driven but the remaining internal power drivers are not driven, in a standby mode so that the leakage current in standby mode is reduced and the standby current is thus reduced. Furthermore, the leakage current of an internal power driver that does not operate in the standby mode is reduced using a high voltage as a back bias of the internal power driver.

Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

Abstract: The present invention achieves technical advantages as embodiments of an SRAM cell (20, 30) having the bit line voltage (BLB/BLB) controlled during standby, such as allowing the bit line to float allowing the bit line voltage to be established by balance of leakage currents to the minimum leakage through the bit line. Advantageously, a controller (22, 32) also controls voltages of supplies Vdd, Vss and the n-well (Vnwell) voltage. The controller reduces a voltage differential between the supply voltage Vdd and voltage Vss in the standby mode. In one embodiment, the bit line may be tied to the reference voltage Vss, and a time delay may be introduced to reduce the possibility of using more charge in switching than that saved.

Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

Abstract: An internal voltage generator maintains stable level of an internal voltage without increasing physical area. The internal voltage generator includes an active level detector for detecting a level of an internal voltage by comparing the level of the internal voltage and a level of a reference voltage to thereby output a first active driving signal, a first active driver for providing the internal voltage in response to the first active driving signal, a driving time controller for generating a time driving signal activated for a predetermined time, an active driving controller for activating a second active driving signal while the time driving signal is activated and for outputting the first active driving signal as the second active driving signal while the time driving signal is inactivated, and a second active driver for providing the internal voltage in response to the second active driving signal.

Abstract: A semiconductor storage device according to an embodiment of the present invention includes: a plurality of word lines; a plurality of memory cells corresponding to the plurality of word lines; and a refresh circuit for sequentially driving the plurality of word lines to refresh each of the plurality of memory cells based on a timer period, which sets the timer period in accordance with a disturb amount in an active mode upon shift from the active mode to the standby mode.

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

Abstract: A self-contained backup power source such as a battery is provided for components within an electrically powered device such as a storage controller, photocopier or the like, to maintain diagnostic status data and to power a service indicator aid, or diagnostic indicator, such as an LED. A switch selects the backup power source when a primary power source of the electrically powered device is no longer available to the component, such as when the component is removed from the electrically powered device, the primary power source is disconnected as a safety precaution when servicing or replacing the component, or a higher-level assembly, in which the component is provided, is removed from the electrically powered device. The diagnostic indicator may be powered separately from the data storage device.

Abstract: A semiconductor storage device includes first and second additional FETs disposed in parallel on one of potential lines for supplying first and second drive potentials to each SRAM memory cell. The gate terminal of the first additional FET is supplied with a selection signal through a selection signal supply line to turn on the first additional FET, when the memory cell is selected. The gate terminal of the second additional FET is supplied with a bias potential through a bias supply line, wherein the bias potential has first and second levels respectively corresponding to non-selection and selection of the memory cell.

Abstract: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

Abstract: A semiconductor circuit apparatus comprises a substrate and a circuit block including a memory formed on the substrate. The circuit block performs regular operations at a first power supply voltage in an active mode, and a part of the circuit block is stopped and the memory keeps stored data at a second power supply voltage smaller than the first power supply voltage in a power save mode. The memory holds the stored data during the power save mode, resulting in higher speed return to a regular active mode, as well as power consumption reduction.

Abstract: Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.

Abstract: When an event takes place in a standby mode, data corresponding to the event is set to a shadow register. The shadow register is operated with a low speed local clock. The contents of the shadow register are copied to a bus IF register through a selector. The bus IF register is connected to a main circuit through a system LSI bus. Data is read from/written to the bus IF register in synchronization with a high speed clock. When the status of the bus IF register changes, a CPU is notified of an interrupt. In a normal mode, an event corresponding to a status change is set to the data bus IF register not through the shadow register. In the standby mode, power of the main circuit is turned off. The high speed clock for the bus IF register is stopped. Thus, the power consumption can be reduced.

Abstract: A multi-chip semiconductor device capable of selectively activating and deactivating the individual semiconductor chips of the device and a chip enable method thereof are included. The individual semiconductor chips of the device are activated and deactivated in accordance with internal chip enable signals.

Abstract: A memory device (200) can include a memory cell block (202), a standby current source (206), an active current source (208), and a clamping device (212). In a standby mode, a standby current source (206) can provide constant standby current ISTBY to memory cell block (202) via block supply node (204). In an active mode, active current source (208) can provide current to accommodate current necessary for active operations (e.g., accessing the memory cell block). A clamping circuit (212) can provide additional current in the event a block supply node (204) potential VCCX collapses due to the presence of micro-defects. In addition, compensation for process variation can be achieved by a self regulating well (454) to source (404) back bias that can modulate the threshold voltage of p-channel transistors of memory cells within the well (454), reducing overall leakage.

Abstract: Different stepped-up voltages and different output currents are generated in one charge pump circuit without increasing the chip area of the charge pump circuit and also electric power consumption in the charge pump circuit to be reduced to a very low power consumption level in standby mode and other modes. A semiconductor integrated circuit device comprises one charge pump circuit with an N number of basic pump cell stages connected to step up voltages in the erase and write modes of a non-volatile memory or the like, generates stepped-up voltages lower than in the erase and write modes and different from one another in output current supply capability, by using series- or parallel-connected pump cells not in excess of the N number of pump cell stages mentioned above, and changes a voltage step-up clock to a stepped-up voltage detection signal.

Abstract: A control circuit for a delay-lock loop having a delay line and a phase detector is used in a memory device. In a standby mode, the control circuit isolates a reference clock signal from the delay-lock loop to save power unless a clock signal generated by the loop is needed for a memory operation. However, the reference signal is periodically coupled to the delay line for a sufficient period to achieve a locked condition. As a result, the phase of the output signal from delay-lock loop can be quickly locked to the phase of the reference signal when a memory operation is to occur during a normal operating mode. When transitioning between the standby mode and the normal operating mode, the control circuit couples the reference clock signal to the delay line for at least a predetermined period of time.

Abstract: In one embodiment, an apparatus comprises a plurality of memory cells; first and second bit lines coupled to the plurality of memory cells; a first and second bit line precharge circuits coupled to the first and second bit lines; and a control circuit coupled to the first and second bit line precharge circuits. The first and second bit line precharge circuits are each configured to precharge the first bit line and the second bit line. The control circuit is coupled to receive an indication that one or more clocks are being restarted after a period of stopped clock operation, and is configured to activate both the first and second bit line precharge circuits responsive to the indication and independent of an operation to the memory that was interrupted by the period of stopped clock operation, if any.

Abstract: The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.

Abstract: A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.

Abstract: A method is described that comprises modulating the power consumption of an SRAM as a function of its usage at least by reaching, with help of a transistor, a voltage on a node within an operational amplifier's feedback loop. The voltage is beyond another voltage that the operational amplifier would drive the node to be without the help of the transistor. The voltage helps the feedback loop establish a voltage drop across a cell within the SRAM.

Abstract: A memory device includes: a generator system having a number of generators that supply voltage or current to the memory device, a controller that supplies to the generator system a state control signal that commands the generators to be in an active state or a standby state, and a self-refresh oscillator that generates a self-refresh clock signal having a period suitable to refresh memory cells of the memory device. The controller uses the self-refresh clock signal to delay transitions of the state control signal from the active state to the standby state relative to corresponding state changes of at least one external signal received by the memory device.

Abstract: Disclosed is a semiconductor storage device in which control is performed in such a manner that if the refresh operation is not being performed when a chip-select signal undergoes a transition from an inactive (standby) state to an active state, read or write access is executed immediately and if the refresh operation is in progress when the chip-select signal undergoes a transition from the inactive state to the active state, a wait signal for causing read or write access to wait is generated by a wait generating circuit.

Abstract: An on die termination (ODT) mode transfer circuit, for use in a semiconductor memory device, including: a delay locked loop (DLL) for receiving an external clock signal in order to generate a DLL clock signal according to a power down mode and an active-standby mode; an ODT mode signal generation means for generating an ODT mode signal in response to the DLL clock signal and a clock enable signal; and an ODT control means for generating a termination resistor (RTT) signal in response to an ODT signal and the ODT mode signal.

Abstract: A memory with an internal detection mechanism to detect the presence of either an external component of an external voltage on some no connect pins, allowing a change in the configuration of the internal voltage pumps based on those detections, or which can be used as a standard device as well. The embodiments allow the system to lower its card power consumption depending upon availability of other voltage sources in the system or available components such as inductors to provide internal voltages more efficiently.

Abstract: A wake-up circuit of a memory device employs a cascade chain structure in which bit lines are divided into a plurality of blocks, and if the bit lines of one of the blocks are determined to have undergone a wake-up operation based on a bit line voltage fed back in the block, the wake-up operation is performed on a subsequent block. Accordingly, a wake-up delay can be varied, and therefore peak currents can be controlled, thereby reducing overall system power noise.

Abstract: A memory device capable of reducing power consumption when the operation mode is a deep power down mode, includes an external power source voltage line through which an external power source voltage is supplied; an internal voltage line through which an internal voltage generated in an internal voltage generator is supplied; a ground voltage line through which a ground voltage is supplied; and an internal circuit selectively connected to one of the external power source voltage line, the internal voltage line and the ground line according to the operation modes of the memory device, to use one of the external power source voltage, the internal voltage and the ground voltage as a power source based on the selective connection of the lines.

Abstract: A new method of increasing access cycle time in a memory device is achieved. The memory device has three operating states of standby, read, and write. The data lines in the memory device may be pre-charged. The method comprises, first, during the standby state, the data lines are pre-charge. Second, during the write state, the data lines are not pre-charged. Third, during the read state, the data lines are not pre-charged. During a transition from the write state to the read state, the data lines are pre-charged.

Abstract: An apparatus and associated method for reducing power consumption in an electronic circuit comprising a refresh load device being employed alternatively between an operational mode and a state refresh mode. A supply voltage level to the refresh load device is adjusted in relation to which of the operational and state refresh modes is employed and in relation to which of a primary alternating current derived power source or a backup battery power source is employed.

Abstract: A device and a method for breaking the leakage current path, wherein the leakage current is caused by a defect in a memory cell of a memory array, are provided. The device includes a column selection line, a row selection line, a switch device coupled to the column selection line, the row selection line, a power supply terminal and a memory cell. When a column turn-off signal is coupled to the column selection line and a row turn-off signal is coupled to the row selection line, the switch device is turned off and thus a power from the power supply terminal can not be coupled to the memory cell. When at least one of the column selection line and the row selection line does not receive the turn-off signal, the switch device is not turned off and the power can be coupled to the memory cell.

Abstract: Current consumption in a nonvolatile memory apparatus operable on two or more different power voltages is to be substantially reduced in its standby mode. A stepped-down power supply unit provided in a flash memory to generate an internal power voltage, when supplied from outside with about 3.3 V as a power voltage, causes a first stepped-down power supply circuit to output the internal power voltage to control circuits when in normal operation. In a low power consumption mode, a second stepped-down power supply circuit outputs the internal power voltage to the control circuits, and in a standby mode a third stepped-down power supply circuit outputs to the control circuits an internal power voltage stepped down by an N-channel MOS transistor.

Abstract: A memory circuit comprises an enable circuit and a receiver. The enable circuit is configured to receive an internal clock signal and provide an enable signal having a first logic level and a second logic level. The receiver is configured to be activated in response to the first logic level of the enable signal and deactivated in response to the second logic level of the enable signal.

Abstract: A dynamic semiconductor memory device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs. A mode setting portion receives a mode setting code applied from an external portion to generate a power saving mode control signal for a power saving mode of operation responsive to a mode setting command. An address control portion decodes an address applied from an external portion or a refresh address to select one of the plurality of the word lines during a normal mode operation. The address control portion also selects a predetermined number of bits of the address during a power saving mode of operation. The semiconductor memory device, therefore extends the refresh cycle while reducing the refresh time resulting in a lower power consumption.

Abstract: Disclosed herein are techniques for reducing standby power consumption due to leakage currents in memory array circuits.

Abstract: A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.