Abstract: A precharge voltage supply circuit and a semiconductor memory device using the same are described. The precharge voltage supply circuit includes a first voltage supplier configured to reduce a precharge voltage and supply the reduced precharge voltage in response to a power down mode signal that is activated in a power down mode, a second voltage supplier configured to supply a power voltage in a predetermined section from a point of time when exiting the power down mode, and a third voltage supplier configured to supply the precharge voltage after a lapse of the predetermined section.

Abstract: A circuit for generating a voltage of a semiconductor memory apparatus includes a control unit that outputs a driving control signal in response to an enable signal and a burn-in signal, a first voltage generating unit that generates and outputs a first voltage in response to the enable signal, and a voltage maintaining unit that maintains the first voltage in response to the driving control signal.

Abstract: An internal voltage generator of a semiconductor memory device controls generating an internal voltage according to an increase of the internal voltage during an active mode, to thereby decrease current consumption. The internal voltage generator of a semiconductor memory device includes a voltage sensor, a plurality of first control units, a plurality of second control units, and a plurality of voltage drivers. The voltage sensor detects an internal voltage. The plurality of first control units generate a plurality of internal control signals according to the voltage level of an output of the voltage sensor. The plurality of second control units generate a plurality of driver control signals in response to the plurality of internal control signals. The plurality of voltage drivers are turned on/off in response to the plurality of driver control signals.

Abstract: An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node.

Abstract: In a non-volatile memory (NVM) device having a controller and a non-volatile memory array controlled by the controller a voltage supervisor circuit monitors an output of a voltage supply powering the NVM device. The voltage supervisor circuit may be part of the NVM device or coupled to it. The voltage supervisor circuit is configured to assert a “low-voltage” signal responsive to detecting the output of the voltage supply powering the NVM device dropping below a predetermined value. The controller is configured to write data into the memory array while the “low-voltage” signal is deasserted and to suspend writing data while the “low-voltage” signal is asserted. In response to assertion of the “low-voltage” signal, the controller completes a write cycle/program operation, if pending, and prevents any additional write cycles/program operation(s) during assertion of the “low-voltage” signal.

Abstract: A semiconductor memory device reduces power consumption during a refresh operation. The semiconductor memory device comprises a voltage generator, a sensing controller, an output driver and a data transmitter. The voltage generator is configured to generate an internal power voltage, which is lower during a power saving mode than during a normal mode, for a peripheral area. The sensing controller is configured to generate a control signal corresponding to a level of the internal power voltage. The output driver is configured to drive a transmitting data by using an output voltage. The data transmitter is configured to convert an inputting data into the transmitting data by using the internal power voltage or convert the inputting data into the transmitting data by using the output voltage in response to the control signal.

Abstract: A semiconductor memory device can stably supply a high voltage even if not only the PVT (Process, Voltage, and Temperature) fluctuations but also the level fluctuations of the external voltage are caused by the variation of the external environments. The driving force of a standby VPP generating unit and a plurality of active VPP generating units are changed according to the PVT fluctuations.

Abstract: A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at least a part of the row control circuit block, the column control circuit block, and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to a mode register. According to the present invention, even if it is necessary to turn predetermined circuit blocks into the active state by an operation other than a read or write operation, there is no need to always set these circuit blocks into the active state.

Abstract: A semiconductor memory including a memory cell which is a MOSFET formed on an SOI substrate. The memory cell has a gate electrode connected to a word line, a drain region connected to a bit line, and a grounded source region. An operation of reading out data written in the memory cell is performed under a biasing condition by which a relationship Vd>Vg?Vth0 holds between a gate voltage Vg to be applied to said gate electrode, a drain voltage Vd to be applied to said drain region, a threshold voltage Vth1 of said MOSFET when a predetermined amount of holes are stored in a body region of the memory cell, and a threshold voltage Vth0 of said MOSFET when holes whose amount is smaller than the predetermined amount are stored in the body region.

Abstract: A power saving system and method are provided. In use, at least one of a plurality of memory circuits is identified that is not currently being accessed. In response to the identification of the at least one memory circuit, a power saving operation is initiated in association with the at least one memory circuit.

Abstract: A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a power node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device, a second terminal coupled to a control signal, a third terminal coupled to a first storage node of at least one tracking cell, a fourth terminal coupled to a second storage node of the tracking cell, and a fifth terminal coupled to the power node of the integrated circuit module, for controlling the switch device to pass the supply voltage to the power node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module.

Abstract: In one embodiment, a memory block includes one or more bit lines that each include two or more cells. Each cell in each bit line has a distance from a sense amplifier coupled to the bit line, and each of one or more of the cells in each of one or more of the bit lines has a delay particularly set according to the distance of the cell from the sense amplifier coupled to the bit line.

Abstract: Provided is an internal voltage generation circuit for generating an internal voltage used in a semiconductor device. The internal voltage generation circuit includes a standby internal voltage generator which is driven during a standby operation and an active operation and supplies a voltage to a core voltage end, a first active internal voltage generator for supplying a voltage to the core voltage end in response to an active signal activated during the active operation, and a second active internal voltage generator which is driven only for a predetermined time period in response to the active signal, and supplies a voltage to the core voltage end.

Abstract: A consumption current balance circuit reduces the layout area and suppresses the deterioration of accuracy of a delay time caused by a temperature variation due to a power variation of a delay circuit itself or caused by a load variation of a power supply. The consumption current balance circuit includes a delay circuit for giving a delay time to a timing pulse signal, a compensation circuit for interpolating the consumption current of the delay circuit, a ring oscillator provided in the same power supply area as the delay circuit; an output period counter for measuring the output period of the ring oscillator; and a heater circuit current amount adjusting circuit for adjusting the current amount of the heater circuit to minimize the difference in the output period between the stand-by state and the active state of the ring oscillator.

Abstract: A first signal input circuit outputs a first control signal in response to self-refresh and active signals. A second signal input circuit outputs a second control signal in response to the self-refresh and active signals. The power supply circuit applies a first supply voltage to an output terminal in response to the first control signal. An elevated voltage generator generates a elevated voltage by pumping a second supply voltage, and applies the elevated voltage to the output terminal, in response to the first and second control signals.

Abstract: An energy efficient storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.

Abstract: A semiconductor memory device includes a cell matrix having a number of cells, a multiplicity of column decoders for selectively activating the cells in response to code signals containing column address information for the cells, wherein each column decoder contains a pre-driving unit for providing a state output signal transiting between a power supply voltage and a source voltage in response to the code signals and a driving unit for outputting a column selection signal to activate a corresponding cell in response to the state output signal, wherein the pre-driving unit and the driving unit include at least one PMOS transistor and at least one NMOS transistor receiving a pumping voltage and a back-bias voltage, respectively, through their bulk, the pumping voltage having a voltage level higher than that of the power supply voltage and the back-bias voltage having a voltage level lower than that of a ground voltage.

Abstract: A method adapts circuit components of a memory module to changing operating conditions within a predefined range. According to one embodiment, a memory module provides a sensor arrangement and a communication bus. Sub-ranges are defined for at least one operating condition, in which the circuit components can work with a fixed setup. During operation, the current state of the at least one operating condition is sensed using the sensing arrangement. The sensed state of the operating condition is mapped to one of the predefined ranges and an associated set of control signals is transmitted over the communication bus. The control signals transmitted over the communication bus are used to adapt at least one circuit component to the current operating conditions.

Abstract: A self-contained backup power source such as a battery is provided for components within an electrically powered device such as a storage controller, photocopier or the like, to maintain diagnostic status data and to power a service indicator aid, or diagnostic indicator, such as an LED. A switch selects the backup power source when a primary power source of the electrically powered device is no longer available to the component, such as when the component is removed from the electrically powered device, the primary power source is disconnected as a safety precaution when servicing or replacing the component, or a higher-level assembly, in which the component is provided, is removed from the electrically powered device. The diagnostic indicator may be powered separately from the data storage device.

Abstract: A non-volatile memory array such as a flash memory array may include a power savings circuit to control a stand-by mode of the non-volatile memory array. The power savings circuit may cause a placement of the non-volatile memory array into a stand-by mode in the absence of activity on at least one or more inputs of the non-volatile memory array. Power may be saved automatically without processor intervention by reducing the operating current of the non-volatile memory array. The automatic power savings circuit may provide a chip enable output to an input of stand-by circuitry to control the operation of the standby circuitry without requiring an explicit stand-by command from a processor.

Abstract: A memory device for early stabilization and rapid increase of a power level after deep power down exit includes a deep power down exit pulse generator, a deep power down exit mode signal generator, a current driving unit, a controller and a voltage generator. The deep power down exit pulse generator generates a deep power down exit pulse signal having a predetermined pulse width in response to a deep power down command. The deep power down exit mode signal generator generates a deep power down exit mode bias signal in response to the deep power down exit pulse signal. The current driving unit generates a deep power down exit mode reference voltage in response to the deep power down exit mode bias signal and a reference signal. The controller generates an enable signal in response to the deep power down exit mode bias signal or an active command.

Abstract: A flash memory device includes a memory cell array including a plurality of memory cells. The flash memory device also includes a voltage generating circuit which generates a plurality of constant voltages to be applied to the memory cell array, the voltage generating circuit including a plurality of voltage regulators which generate at least two constant voltages, each having a constant voltage difference.

Abstract: During operation, a control signal attains H level, a conventional type first reference voltage generation circuit is activated, and the first reference voltage generation circuit generates a reference voltage. During stand-by, the control signal attains L level, and the first reference voltage generation circuit is inactivated, whereby a through current does not flow through the first reference voltage generation circuit. Then, during stand-by, an internal voltage generation circuit is supplied with the reference voltage generated by a second reference voltage generation circuit including a resistance division circuit constituted of first to third resistors each having a high resistance value of T (tera) ? order, in which a through current is extremely small.

Abstract: A semiconductor device may include a first logic unit for performing a logic operation with respect to a plurality of first control signals, each of which indicates whether a corresponding one of a plurality of banks of the semiconductor device is in an active state, a refresh detector for outputting a second control signal which is enabled when at least one of the banks performs a self-refresh operation or auto-refresh operation, and a second logic unit for performing a logic operation with respect to an output signal from the first logic unit and the second control signal to generate a third control signal having information about activation of the semiconductor device. The third control signal is enabled when at least one of the banks performs the self-refresh operation or auto-refresh operation even though it is in the active state.

Abstract: Disclosed is a method for refreshing voltages in a non volatile memory during a standby mode. The method comprises generating a first node voltage and a second node voltage through a resistance ladder, storing the voltages in a pair of capacitors, comparing the voltages by a comparator, generating an output electrical signal by the comparator upon comparing the voltages, latching the output electrical signal by a flip flop, generating an electrical refresh pulse by a refresh pulse generator upon receiving the output electrical signal from the flip flop, the electrical refresh pulse being supplied to a refresh node of a plurality of refresh nodes in the non volatile memory and generating an electrical sample pulse by a sample pulse generator, the electrical sample pulse along with the electrical refresh pulse setting the flip flop, thereby causing the flip flop to latch a new output electrical signal.

Abstract: A power-down mode exit control circuit enables a memory device to exit from an initially set power-down mode state using a clock enable signal. Specifically, although a clock enable signal is inputted in an unstable state at an initial operation indicating that a supply of a supply voltage is started, the present invention provides the power-down mode exit control circuit which is capable of escaping from the power-down mode at an internally set correct time. For this, the present invention comprises: a clock enable signal sensor for sensing an activation or deactivation state of a clock enable signal; and a power-down mode exit signal generator for activating and outputting a power-down mode exit signal in accordance with the activation state of the clock enable signal sensed by the sensor, after storing information related to the deactivation state of the clock enable signal sensed by the sensor.

Abstract: An active cycle control circuit includes a refresh active control signal generation unit that generates a refresh active control signal at the same cycle as a refresh request signal at a timing earlier than the refresh request signal, a refresh standby signal output unit that outputs a refresh standby signal according to a refresh active signal and the refresh request signal, and an active control unit that outputs a row active signal for performing a read cycle according to a read command and outputs the refresh active signal according to the refresh active control signal and the refresh standby signal within the read cycle.

Abstract: A memory device includes at least one memory array having a plurality of memory cells addressed by a plurality of word lines and bit lines, and coupled between a power line and a ground line. A word line decoder is coupled to one end of the word line for selecting the word lines in response to input signals. A voltage control circuit is coupled to another end of the word line for connecting the word line to a ground voltage when the memory device is in a sleep mode, wherein the voltage control circuit is supplied by DC power.

Abstract: A PLD (200) includes a power management unit (PMU 210) that selectively implements one or more different power-reduction techniques in response to power configuration signals (PC). By manipulating the PC signals, the PMU can independently enable/disable various supply voltage circuits (110, 120, 130) that power CLBs (101), IOBs (102), and configuration memory cells (106), can generate a capture signal that causes data stored in storage elements of the CLBs to be captured in configuration memory cells, and/or can switch power terminals of configuration memory cells between voltage supply circuits. Also, the PMU can sequentially apply and remove power from a number of configurable PLD portions in response to the PC signals, wherein each configurable portion may include any number of the PLD's resources.

Abstract: A temperature sensor instruction signal generator, which may drive a temperature sensor, and a semiconductor memory device including the same. The temperature sensor instruction signal generator may generate an instruction signal that instruct the operation of the temperature sensor using at least one of a master clock (CLK) signal, a clock enable (CKE) signal, a row address selection (RAS) signal, a column address selection (CAS) signal, a write enable (WE) signal, and a chip selection (CS) signal, wherein the instruction signal may be enabled corresponding to at least one of a self refresh mode, an auto refresh mode, and a long tRAS mode. The semiconductor memory device may include a temperature sensor and the temperature sensor instruction signal generator.

Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

Abstract: Reducing power while in standby mode may comprise monitoring for an occurrence of at least one event requiring a transition out of a standby mode while utilizing a lower frequency, less accurate, and low power standby clock signal while operating in the standby mode. After receiving the occurrence of the event, an identity of the received event may be determined. In response to receiving the event, based on the determined identity of the event, a first and/or a second clock signal may be enabled, which has higher frequency and better accuracy and consumes more power than the standby clock signal. If the first and/or second clock signal is enabled, they may be disabled in order to re-enter the standby mode, which utilizes the standby clock signal while in standby mode.

Abstract: An internal voltage generation device includes a plurality of output nodes; a bit line precharge voltage generation unit for generating a bit line precharge voltage; a first voltage drop unit for transferring the bit line precharge voltage to a first output node after decreasing the bit line precharge voltage by a first voltage drop amount in response to a test mode signal; and a second voltage drop unit for transferring the bit line precharge voltage to a second output node after decreasing the bit line precharge voltage by a second voltage drop amount in response to the test mode signal, wherein the second voltage drop amount is greater than the first voltage drop amount.

Abstract: An internal voltage generator includes an output node, a bit line precharge voltage generating unit for generating a bit line precharge voltage, and a voltage drop block for dropping a voltage level of the bit line precharge voltage according to operating modes.

Abstract: A battery-backed write-caching mass storage controller is disclosed. The controller includes a plurality of volatile memory banks for caching write data prior to being written to disk drives. Critical data is stored into a first subset of the memory banks, leaving a second subset of memory banks storing only non-critical data. Critical data is data that must be retained during a main power loss to avoid loss of write-cached user data. Critical data includes the write-cached user data itself, as well as metadata describing the write-cached user data. When the controller detects a loss of main power, the controller causes the critical memory banks to receive battery power, but disables battery power to the non-critical memory banks in order to extend the length of time the critical memory banks can continue to receive battery power to reduce the likelihood of user data loss.

Abstract: A backup volatile state retention circuit is provided with low leakage current for employment with a volatile memory circuit to store the value of the latter during power down of the volatile circuit or during power-down or inactivation of neighboring or peripheral circuits or due to the loss of power of any of these circuits. An example of such a volatile circuit is a memory circuit having volatile memory cells such as employed in dynamic memory core, in particular, a random access memory (RAM) in CMOS circuitry.

Abstract: A flash memory device may include a memory cell array. The memory cell array may include a plurality of memory cells. The flash memory device may also include a voltage generator which generates a plurality of constant voltages. The voltage generator may comprise of a plurality of voltage regulators, wherein each voltage regulator is configured to divide a high voltage generated from a charge pump to generate at least two constant voltages having a constant voltage difference therebetween. The plurality of voltage regulators may have independent voltage dividing paths, wherein each path is configured to generate a separate constant voltage.

Abstract: A voltage regulator for a static random access memory operating either in a standby mode or a operation mode is provided. The voltage regulator includes a reference voltage generating circuit for generating a reference voltage, a first control circuit connected to the reference voltage generating circuit for providing power supply during the standby mode of the SRAM, and a second control circuit connected to the reference voltage generating circuit for providing power in response to an enabling signal during the operation mode of the SRAM.

Abstract: A DRAM and its application to a mobile telephony circuit with a control circuit including a first refreshment controller controlled by a first clock signal and a second refreshment controller controlled by a second clock signal having a frequency less than that of the first one and used to synchronize events of the GSM network.

Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

Abstract: A memory with an internal detection mechanism to detect the presence of either an external component of an external voltage on some no connect pins, allowing a change in the configuration of the internal voltage pumps based on those detections, or which can be used as a standard device as well. The embodiments allow the system to lower its card power consumption depending upon availability of other voltage sources in the system or available components such as inductors to provide internal voltages more efficiently.

Abstract: A semiconductor integrated circuit is provided including a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The integrated circuit includes an interblock interface circuit provided on a signal path between an elected circuit block and a branch point at which the signal path branches into different branch paths so as to connect to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission from the elected circuit block to the other circuit blocks, and includes a storage unit for storing a signal right before the power cut-off.

Abstract: A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit a relatively slow refresh rate. When transitioning from the full density mode to the half density mode, data are copied from each row of memory cells storing data to an adjacent row of memory cells. The adjacent row of memory cells are made free to store data from an adjacent row by remapping the most significant bit of the row address to the least significant bit of the row address, and then remapping all of the remaining bits of the row address to the next highest order bit.

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

Abstract: Disclosed is a method for refreshing voltages in a non volatile memory during a standby mode. The method comprises generating a first node voltage and a second node voltage through a resistance ladder, storing the voltages in a pair of capacitors, comparing the voltages by a comparator, generating an output electrical signal by the comparator upon comparing the voltages, latching the output electrical signal by a flip flop, generating an electrical refresh pulse by a refresh pulse generator upon receiving the output electrical signal from the flip flop, the electrical refresh pulse being supplied to a refresh node of a plurality of refresh nodes in the non volatile memory and generating an electrical sample pulse by a sample pulse generator, the electrical sample pulse along with the electrical refresh pulse setting the flip flop, thereby causing the flip flop to latch a new output electrical signal.

Abstract: A semiconductor integrated circuit is provided including a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The integrated circuit includes an interblock interface circuit provided on a signal path from the elected circuit block to other circuit blocks, wherein a single output of the interblock interface circuit is branched out to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission to other circuit blocks and includes a storage unit for storing a signal right before the power cut.

Abstract: A semiconductor integrated circuit is provided including a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The integrated circuit includes an interblock interface circuit provided on a signal path from the elected circuit block to other circuit blocks, wherein a single output of the interblock interface circuit is branched out to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission to other circuit blocks and includes a storage unit for storing a signal right before the power cut.

Abstract: Provided is a DRAM having reduced current consumption and a communication terminal including the same. The DRAM includes a plurality of memory banks capable of being independently supplied with power, and a DPD controller for selectively causing some of the plurality of memory banks to enter a DPD mode.

Abstract: A memory device responsive to standby mode commands for reducing internal operational power on a memory device is disclosed. The memory device includes a circuit for reducing power during a standby mode with the circuit including a reference with at least first and second reference signals. The circuit also includes a switching device for switching between the first and second reference signals in response to the standby mode command and further controls an internal operational power regulator to adjust between normal and low-power outputs further reducing the power to portions of the memory device.

Abstract: An Static Random Access Memory (SRAM) device and a method of operating the same. In one embodiment, the SRAM device includes: (1) an SRAM array coupled to row peripheral circuitry by a word line and coupled to column peripheral circuitry by bit lines and (2) an array low voltage control circuitry that provides an enhanced low operating voltage VESS to the SRAM array during at least a portion of an active mode thereof.