Abstract: An apparatus includes a first tier, a second tier and a memory. The second tier is vertically stacked on the first tier. The memory includes a column of memory bit cells. A first portion of the column of memory bit cells is on the first tier. A second portion of the column of memory bit cells is on the second tier.

Abstract: An interconnect layout structure having air gaps includes a plurality of air gaps extended along a direction, and at least a first interconnect unit disposed in between the air gaps. The first interconnect unit includes a first conductive line, a first landing mark situated on the first conductive line and a first via structure situated on the first landing mark. The first via structure penetrates the first landing mark and is electrically connected to the first conductive line. And the first landing mark physically separates the air gaps arranged in a straight line.

Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.

Abstract: A semiconductor memory device includes a memory structure including a first integrated circuit chip and a plurality of second integrated circuit chips stacked on each other, the first integrated circuit chip is interposed between a pair of the plurality of second integrated circuit chips, an interface unit disposed on the first integrated circuit chip, the memory structure is connected to a third circuit through the interface unit, and the interface unit transfers operation signals to the first integrated circuit chip and the plurality of second integrated circuit chips, at least one inter-chip interconnector connected with the interface unit and the first integrated circuit chip and the plurality of second integrated circuit chips, and an external interconnector connected with the interface unit and the third circuit.

Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

Abstract: There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

Abstract: A memory circuit includes a first memory cell and a second memory adjacent to the first memory cell. The first memory cell includes a first word line strapping line segment electrically coupled with a pass device of the first memory cell; and a second word line strapping line segment. The second memory cell includes a first word line strapping line segment; and a second word line strapping line segment electrically coupled with a pass device of the second memory cell. The first word line strapping line segment of the first memory cell and the first word line strapping line segment of the second memory cell are connected with each other at a first interconnection layer. The second word line strapping line segment of the first memory cell and the second word line strapping line segment of the second memory cell are connected with each other at the first interconnection layer.

Abstract: A semiconductor apparatus includes a plurality of stacked chips. Each of the plurality of stacked chips includes a delay chain. Each of the plurality of stacked chips comprises a plurality of Through-Vias, wherein one of the plurality of Through-Vias formed in a first one of the plurality of stacked chips and electrically coupled to a predetermined location of a first delay chain on the first one of the plurality of stacked chips and one of the plurality of Through-Vias formed in a neighboring one of the plurality of stacked chips and electrically coupled to a predetermined location of a delay chain on the neighboring one of the plurality of stacked chips are configured to electrically couple the first one of the plurality of stacked chips to the neighboring one of the plurality of stacked chips. A signal transmitted from a first one of the plurality of stacked chips generates a feedback signal to the first one of the plurality of stacked chips through one or more of the plurality of Through-Vias.

Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

Abstract: A storage apparatus includes a printed circuit board (PCB) and multiple memory chips symmetrically arranged on two sides of the PCB, where multiple memory chips on one side of the PCB form a rank, and multiple memory chips on the other side of the PCB form a rank; a memory chip includes multiple pins; multiple cables are disposed in the PCB; and one cable of the multiple cables is connected to two pins in a same position on the two sides of the PCB.

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a first stacked body, a columnar part, a second insulating film, and a second stacked body. The first stacked body is provided in a first region on the substrate. The second insulating film is provided in a second region on the substrate, and has a first thickness in a stacking direction of the first stacked body. The second stacked body is provided on the second insulating film. The second stacked body includes a first film and a third insulating film stacked alternately on one another. The uppermost first film in the first films of the second stacked body is located at a first distance in the stacking direction from the upper surface of the substrate. The first thickness is a thickness not less than 30 percent of the first distance.

Abstract: A stackable layer is provided for 3-Dimensional multi-layered modular computers. The stackable layer comprises at least one encapsulated chip die. Sets of electrical contacts are provided on each one of the large surfaces of the layer. The encapsulated chip die and the two large opposite surfaces of the layer are substantially parallel.

Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.

Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.

Abstract: A backplane system, which includes a backplane board and a backplane controller module having a backplane controller. The backplane controller module is configured to be detachably connected to the backplane board via a small outline dual in-line memory module (SODIMM) connector interface to enable communications between the backplane controller and the backplane board via the SODIMM connector interface, such that the backplane controller is configured to control a plurality of components on the backplane board. Specifically, the SODIMM connector interface may include a SODIMM connector socket disposed on the backplane board, and a SODIMM connector pin set provided on the backplane controller module to be detachably inserted into the SODIMM connector socket. The SODIMM connector pin set may be a 144-pin SODIMM connector having 144 contact pins.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one metal layer interconnecting the first transistors, a portion of the first transistors forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; at least one connection from the plurality of first transistors to a plurality of through silicon vias (TSVs); a plurality of third transistors overlaying the plurality of second transistors, where the plurality of second transistors are self-aligned to the plurality of third transistors having been processed following the same lithography step; and a first memory array and a second memory array, where the first memory array includes the plurality of second transistors and the second memory array includes the plurality of third transistors.

Abstract: A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks.

Abstract: A layout arrangement for a resistive random access memory cell includes an active area, a polysilicon row address line over the active region, a metal column address line running orthogonal to the row address line and having an active region contact portion extending over the active region and having a contact to the active region. A metal output line runs parallel to the column address line over the active region. A first cell contact region intersects with the output line and has a contact to the active region. A first metal cell contact region forms an intersection with the first cell contact region. A first resistive random access memory device is formed at the intersection of the first cell contact region and the output line. A second resistive random access memory device is formed at the intersection of the first cell contact region and the first cell contact region.

Abstract: A system includes a memory device and a memory controller. The memory device has a data pin and a first available pin. The memory controller has a data pin coupled to the data pin of the memory device, and has a first available pin coupled to the first available pin of the memory device. The memory controller transfers memory data on the first available pin of the memory controller, and the memory device receives memory data on the first available pin of the memory device.

Abstract: An apparatus includes a motherboard, a storage module, a first socket arranged on the motherboard, a second socket also arranged on the motherboard, and an interface. A processor is arranged within the first socket and a storage module is arranged within the second socket. The interface is configured to provide intercommunication between the processor and the storage module. The storage module contains a plurality of nonvolatile memory cards.

Abstract: A wafer-level package has a first input/output (I/O) port, a second I/O port, a first semiconductor die, and a second semiconductor die. The first I/O port and the second I/O port of the wafer-level package are arranged to connect at least one management bus. The first semiconductor die and the second semiconductor die assembled in the wafer-level package are arranged to receive commands from the first I/O port and the second I/O port, respectively.

Abstract: Systems and methods for reducing the area and improving the performance of a non-volatile memory array are described. The non-volatile memory array may comprise a 3D NAND memory array that includes vertical NAND strings that are arranged orthogonal to a substrate. A vertical NAND string may include floating gate memory cell transistors or charge trap memory cell transistors. Sensing circuitry for sensing the programmed data states of memory cell transistors within the vertical NAND strings may be positioned underneath the 3D NAND memory array and connections from bit lines positioned above the 3D NAND memory array may be made using vertical connections extending though the 3D NAND memory array or through memory breaks within the 3D NAND memory array.

Abstract: According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)th second sidewall film matching a pattern of a nth (where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2n)×(?/NA) or less when an exposure wavelength of an exposure device is ?, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.

Abstract: A first photo-alignment film (12) of a liquid crystal display device (100) includes a first and a second pre-tilt region (12a, 12b) defining pre-tilt directions (PD1, PD2) that are anti-parallel to each other, and a second photo-alignment film (22) thereof includes a third and a fourth pre-tilt region (22a, 22b) defining pre-tilt directions (PD3, PD4) that are anti-parallel to each other. The entire boundary (BD1) between the first and second pre-tilt regions and the entire boundary (BD2) between the third and fourth pre-tilt regions are aligned with each other, as seen from the display plane normal direction. A pixel electrode (11) includes a first and a second cut-off portion (11a1, 11a2) provided by cutting off at least a part of a particular edge portion (11e1, 11e2) of the outer perimeter thereof.

Abstract: Pixel compensation circuit, method and flat display device. The circuit includes a control terminal of a first controllable switch connected with a first scanning line, first terminal connected with data line; second terminal connected with control terminal of the driving switch through a storage capacitor, a first terminal of the driving switch connected with a voltage terminal; a control terminal of the second controllable switch connected with a second scanning line, a first terminal connected with the control terminal of the driving switch, the second terminal connected with second terminal of the driving switch; control terminal of the third controllable switch connected with a third scanning line, first terminal connected with the second terminal of the driving switch; anode of an OLED connected with the second terminal of the third controllable switch, cathode is grounded to avoid unstable current of the OLED by drift of threshold voltage of driving transistor.

Abstract: A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration.

Abstract: Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip.

Abstract: A system and a method for temperature sensing of three-dimensional integrated circuits are revealed. The three-dimensional integrated circuit is formed by stacking of a plurality of chip layers that execute specific functions. The chip layer includes a master layer and at least one slave layer. The master layer is disposed with a master temperature sensor while a first thermal conductive part is arranged at the slave layer where heat is detected. The first thermal conductive part and the master temperature sensor are connected by a thermal conductive structure. Thereby temperature of various points at different chip layers is conducted to the same chip layer by Through Silicon Vias to be measured and calibrated. The design complexity and the implementation cost of the temperature sensing system are significantly reduced.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of pillar portions, and an interconnection portion. The stacked body is provided on the substrate. The stacked body includes a plurality of electrode layers stacked separately from each other. The plurality of pillar portions are provided in the stacked body. The plurality of pillar portions extend in a stacking direction of the stacked body. The interconnection portion is provided in the stacked body. The interconnection portion extends in a first direction. The neighboring pillar portions are not arranged along the first direction.

Abstract: An integrated circuit die may include bottom-gate thin-body transistors. The bottom-gate thin-body transistors may be formed in a thinned-down substrate having a thickness that is defined by shallow trench isolation structures that provide complete well isolation for the transistors. The transistors may include gate terminal contacts formed through the shallow trench isolation structures, bulk terminal contacts that are formed through the thinned substrate and that overlap with the gate contacts, and source-drain terminal contacts with in-situ salicide. Additional metallization layers may be formed over the gate/bulk/source-drain contacts after bonding.

Abstract: A three-dimensional (3D) non-volatile semiconductor memory device is disclosed. The three-dimensional (3D) non-volatile semiconductor memory device includes: a cell region having a plurality of memory cells; a page buffer formed to store data of the cell region in units of a page; a decoder formed below the cell region, configured to provide a word line voltage to word lines of the cell region; a first upper line formed above the cell region, configured to transfer the word line voltage; a lower interconnection structure formed below the cell region, configured to transfer the word line voltage to the decoder; and a first via disposed between the cell region and the page buffer, configured to couple the first upper line to the lower interconnection structure.

Abstract: Methods, systems, and apparatus that increase available memory or storage using active boundary areas in quilt architecture are described. A memory array may include memory cells overlying each portion of a substrate layer that includes certain types of support circuitry, such as decoders and sense amplifiers. Active boundary portions, which may be elements of the memory array having a different configuration from other portions of the memory array, may be positioned on two sides of the memory array and may increase available data in a quilt architecture memory. The active boundary portions may include support components to access both memory cells of neighboring memory portions and memory cells overlying the active boundary portions. Address scrambling may produce a uniform increase in number of available data in conjunction with the active boundary portions.

Abstract: A semiconductor memory device may include: a first group of pillars having diameters which are gradually increased toward the a first side; and interlayer insulating layers and conductive patterns surrounding the pillars of the first group, the interlayer insulating layers and conductive patterns being alternately stacked.

Abstract: According to one embodiment, electrodes are provided in stacked M (M is an integer of 2 or more) semiconductor chips, a transmission units are provided for the semiconductor chips and, based on a chip identification information on a semiconductor chip in the present stage, transmits the chip identification information on a semiconductor chip in the next stage via the electrodes, or transmit a data for setting the chip identification information, and the direction in which an external signal is sent via the electrodes is opposite to the direction in which the chip identification information is transmitted via the electrodes.

Abstract: An improved architecture is provided which enables significant convergence of the components of a system to implement virtualization. The infrastructure is VM-aware, and permits scaled out converged storage provisioning to allow storage on a per-VM basis, while identifying I/O coming from each VM. The current approach can scale out from a few nodes to a large number of nodes. In addition, the inventive approach has ground-up integration with all types of storage, including solid-state drives. The architecture of the invention provides high availability against any type of failure, including disk or node failures. In addition, the invention provides high performance by making I/O access local, leveraging solid-state drives and employing a series of patent-pending performance optimizations.

Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.

Abstract: A chip includes a dielectric layer having a top surface and a bottom surface, a first semiconductor layer overlying and bonded to the top surface of the dielectric layer, and a first Metal Oxide-Semiconductor (MOS) transistor of a first conductivity type. The first MOS transistor includes a first gate dielectric overlying and contacting the first semiconductor layer, and a first gate electrode overlying the first gate dielectric. A second semiconductor layer is underlying and bonded to the bottom surface of the dielectric layer. A second MOS transistor of a second conductivity type opposite to the first conductivity type includes a second gate dielectric underlying and contacting the second semiconductor layer, and a second gate electrode underlying the second gate dielectric.

Abstract: A serial peripheral interface of an integrated circuit includes: a first transfer pin for receiving an instruction and an address; and a clock pin for inputting a plurality of timing pulses each having a rising edge and a falling edge. After the first transfer pin receives the instruction, the integrated circuit receives the address through the first transfer pin in continuity with the receipt of the instruction. The first transfer pin receives the instruction at either of the rising edges and the falling edges of the timing pulses and receives the address at both of the rising edges and falling edges of the timing pulses.

Abstract: A device includes a first data terminal, a second data terminal, a first switching buffer coupled between a data node and the first data terminal and a second switching buffer coupled between the data node and the second data terminal. The first switching buffer and the second switching buffer are arranged such that a distance between the first switching buffer and the second data terminal is shorter than a distance between the second switching buffer and the second data terminal and that a distance between the first switching buffer and the first data terminal is shorter than a distance between the second switching buffer and the first data terminal.

Abstract: A storage module may include a controller configured to communicate with a memory having a plurality of memory dies. The controller may include a plurality of bond pads, where each bond pad is configured to communicate a same type of memory signal, and where each bond pad is electrically connected to at least one but less than all of the plurality of memory dies. A core of the controller may identify a memory die that it wants to communicate a memory signal and an associated bond pad with which to communicate the memory signal.

Abstract: The present disclosure outlines front-end-of-line (FEOL) processing, middle-end-of-line (MEOL) processing, and back-end-of-line (BEOL) processing for fabricating a memory cell that can be implemented within a data storage device. The memory cell of the present disclosure represents a multiple port memory cell having at least three ports, such as a write-port, a first read-port, and a second read-port. The disclose FEOL processing is used to form semiconductor devices of the memory cell onto diffusion layers and polysilicon layers of a semiconductor layer stack. The disclosed MEOL processing is used to form interconnections, such as one or more vias and/or one or more contacts to provide some examples, between the semiconductor devices and metallization layers of the semiconductor layer stack. The disclosure BEOL processing is used to form the least three ports onto the metallization layers of the semiconductor layer stack.

Abstract: A semiconductor package may include a first die, a second die disposed adjacent to the first die, and configured to share an address with the first die. The semiconductor package may include a first address pin included with the first die, and configured for receiving the address. The semiconductor package may include a second address pin included with the second die, and configured for receiving the address. The first die and the second die may output data corresponding to the address. Timings of the address in the first die and the second die may be aligned according to delay signals applied from a controller.

Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

Abstract: A memory array including: a first volatile memory cell including first and second cross-coupled inverters between first and second storage nodes; a first non-volatile memory cell including at least one resistive element that can be programmed to take one of at least two resistive states; and a control circuit adapted to couple the first non-volatile memory cell to the first and second storage nodes in order to generate a current for programming the resistive state of the at least one resistive element.

Abstract: A semiconductor device is provided. The semiconductor device includes: a plurality of fin-type active patterns which extend along a first direction, and are arranged with respect to each other along a second direction different from the first direction; a contact which is electrically connected to the plurality of fin-type active patterns; a first gate electrode which extends along the second direction and is formed on at least two of the plurality of fin-type active patterns; and a second gate electrode which extends along the second direction and is formed on at least one of the plurality of fin-type active patterns. The first gate electrode is disposed between the contact and the second gate electrode, and the number of fin-type active patterns intersected by the first gate electrode is greater than the number of fin-type active patterns intersected by the second gate electrode.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells arranged on a substrate. The semiconductor memory device includes an interconnect layer including a first interconnect and a second interconnect, the first interconnect extending in a first direction, the second interconnect extending in a second direction, the first direction being tilted with respect to an arrangement direction of the memory cells, the second direction being different from the first direction and tilted with respect to the arrangement direction of the memory cells.

Abstract: A semiconductor memory including a memory cell array having a plurality of memory cells, a plurality of bit line pairs which are disposed corresponding to respective columns of the memory cell array, and sense amplifiers which are disposed in plurality corresponding to the plurality of bit line pairs for amplifying a potential difference between the bit line pair in which the sense amplifier includes; precharging transistors each having a diffusion layer and precharging the bit line pair, and switching transistors each having a diffusion layer formed integrally with the diffusion layer of the precharging transistor for selectively connecting the plurality of the bit line pairs to a common bus line.

Abstract: A method of training a command signal for a memory module. The method includes programming a memory controller into a mode where a single bit of an address signal is active for a single clock cycle. The method then programs a programmable delay line of the address signal with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode. A write leveling procedure is then performed and a response to the write leveling procedure is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.