Abstract: A memory module is provided including a plurality of semiconductor memory devices mounted on a circuit board. A control device is mounted on the circuit board and configured to receive a command signal, an address signal, and a clock signal and to provide the command signal, the address signal, and the clock signal to the plurality of semiconductor memory devices. A first group of the semiconductor memory devices is disposed between the control device and a first edge portion of the circuit board, and a second group of the semiconductor memory devices is disposed between the control device and a second edge portion of the circuit board. The control device is configured to transmit the address signal to the first group of the semiconductor memory devices and the second group of the semiconductor memory devices through a first transmission line and a second transmission line, respectively.

Abstract: An image sensor comprising a BJT pixel circuit, a biasing circuit and a comparator. The BJT pixel circuit comprises a BJT; a charging selection circuit, configured to control a first storage capacitor to be charged in a first reset time and to control a second storage capacitor to be charged to a second reset time; a discharging selection circuit, configured to control the first storage capacitor to be discharged by the BJT in a first exposure time to generate a first output voltage, and to control the second storage capacitor to be discharged by the BJT in a second exposure time to generate a second output voltage; a biasing circuit, configured to provide voltage decreasing and voltage increasing to the second output voltage to generated adjusted images; and a comparator, configured to compare the first output voltage and the adjusted voltages.

Abstract: Multiple independent point-to-point memory channels are operated, by at least one controller, in parallel to form a wider memory channel. The memory components on these point-to-point channels include the ability to connect to multiple (e.g., 2) instances of these independent memory channels. The controller operates multiple instances of the wider channels with the memory components configured in a clamshell mode. A single memory component is also operated in clamshell mode to provide error correction code information, independently of the other wider channels, to multiple instances of the wider memory channel.

Abstract: A semiconductor storage device includes a logic circuit formed on a substrate, a first area formed on the logic circuit and has a plurality of first insulating layers and a plurality of conductive layers alternately stacked in a first direction, a plurality of memory pillars MP which extend in the first area in the first direction, a second area which is formed on the logic circuit and has the plurality of first insulating layers 33 and a plurality of second insulating layers alternately stacked in the first direction, and a contact plug CP1 which extends in the second area in the first direction and is connected to the logic circuit.

Abstract: A three dimensional (3D) array of magnetic random access memory (MRAM) bit-cells is described, wherein the array includes a mesh of: a first interconnect extending along a first axis; a second interconnect extending along a second axis; and a third interconnect extending along a third axis, wherein the first, second and third axes are orthogonal to one another, and wherein a bit-cell of the MRAM bit-cells includes: a magnetic junction device including a first electrode coupled to the first interconnect; a piezoelectric (PZe) layer adjacent to a second electrode, wherein the second electrode is coupled to the second interconnect; and a first layer adjacent to the PZe layer and the magnetic junction, wherein the first layer is coupled the third interconnect.

Abstract: Apparatus, systems, or methods for a memory array having a plurality of word lines. A word line includes at least one word line plate, and the word line plate comprises a first material with a first resistivity. An edge of the word line plate is recessed and filled with a second material having a second resistivity that is lower than the first resistivity. As a result, the total resistance of the word line may be reduced compared to a word line using only the first material with the first resistivity. Other embodiments may also be described and claimed.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes a plurality of first lines extending in a first direction; a plurality of second lines over the first lines, the second lines extending in a second direction crossing the first direction; a plurality of memory cells disposed at intersection regions of the first lines and the second lines between the first lines and the second lines in a third direction perpendicular to the first and second directions; and a heat sink positioned between two memory cells adjacent to each other in a diagonal direction with respect to the first and second directions.

Abstract: An edge memory array mat with access lines that are split, and a bank of sense amplifiers formed under the edge memory array may in a region that separates the access line segment halves. The sense amplifiers of the bank of sense amplifiers are coupled to opposing ends of a first subset of the half access lines pairs. The edge memory array mat further includes access line connectors configured to connect a second subset of the half access line pairs across the region occupied by the bank of sense amplifiers to form combined or extended access lines that extend to a bank of sense amplifiers coupled between the edge memory array mat and an inner memory array mat.

Abstract: A semiconductor device of an embodiment includes: a wiring board having a first surface and a second surface on a side opposite to the first surface; a first semiconductor element on the first surface of the wiring board; a second semiconductor element on the first surface of the wiring board; and a first sealing material that seals at least the second semiconductor element. A slit is formed in the first sealing material between the first semiconductor element and the second semiconductor element. When a thickness of the first sealing material on the first semiconductor element is t1 and a thickness of the first sealing material on the second semiconductor element is t2, the t1 and the t2 satisfy a relationship of 0?t1<t2.

Abstract: A system for clock management in an m columns×n rows array-based accelerators. Each row of the array may include a clock domain that clocks runtime clock cycles for the m processing elements. The clock domain includes a data detection and timing control circuit which is coupled to a common clock phase bus which provides a local clock source in multiple selectable phases, wherein the data detection and timing control circuit is configured to select a clock phase to clock a next clock cycle for a next concurrent data processing by the m processing elements. Each of m processing elements is coupled to access data from a first memory and a second memory and to generate respective outputs from each of the m processing elements to a corresponding m processing element of a same column in a subsequent neighboring row for the next processing in the next clock cycle.

Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).

Abstract: A semiconductor device including a substrate having isolation films and active regions that are defined by the isolation films. The active regions extend in a first direction. A first trench is disposed on the substrate. Second trenches are disposed in the active regions. A filling film is disposed in the first trench. First gate patterns are disposed on the filling film in the first trench. Second gate patterns are disposed in the second trenches. The second gate patterns extend in a second direction that is different from the first direction. The filling film includes at least one material selected from a semiconductor material film and a metal.

Abstract: Detection accuracy of a collector sense in detecting a voltage is improved. A power module 300 has a first conductor 410 and a second conductor 411 to which a plurality of active elements 317 and 315 configuring upper and lower arm circuits are connected. In addition, the power module 300 has an AC side terminal 320B protruding from one side 301a, a positive electrode side terminal 315B and a negative electrode side terminal 319B which protrude from the other side 301b, an intermediate electrode portion 414 that connects the first conductor 410 and the second conductor 411 to each other, and a collector sense wiring 452a in which a collector electrode of an active element 157 and the first conductor 410 are connected to each other via a sense connection portion 415.

Abstract: A representative system, apparatus, method and protocol are disclosed for data communication between chiplets or SOCs on a common interposer. A representative system comprises: an interposer; a first integrated circuit arranged on the interposer, the first integrated circuit comprising a first common protocol interface circuit; a communication link coupled to the first common protocol interface circuit; and a second integrated circuit arranged on the interposer, the second integrated circuit comprising a second common protocol interface circuit coupled to the communication link to form a serial protocol interface between the first common protocol interface circuit and the second common protocol interface circuit. Serial data and control packets and parallel data and control packets having specified, ordered fields are also disclosed.

Abstract: The present disclosure generally relates to semiconductor devices, and more particularly, to semiconductor devices having memory cells for multi-bit programming and methods of forming the same. The present disclosure also relates to a method of forming such semiconductor devices. The disclosed semiconductor devices may achieve a smaller cell size as compared to conventional devices, and therefore increases the packing density of the disclosed devices.

Abstract: Provided are embodiments for a computer-implemented method, a system, and a computer program product for updating an analog crossbar array. Embodiment include receiving a number used in matrix multiplication to represent using pulse generation for a crossbar array, and receiving a bit-length to represent the number. Embodiments also include selecting pulse positions in a pulse sequence having the bit length to represent the number, performing a computation using the selected pulse positions in the pulse sequence, and updating the crossbar array using the computation.

Abstract: Some embodiments include an integrated assembly having first conductive lines which extend along a first direction, and having second conductive lines over the first conductive lines and which extend along a second direction that crosses the first direction. Capacitors are over the second conductive lines. The second conductive lines are operatively proximate active structures to gatedly couple a first set of the capacitors to the first conductive lines through the active structures. Shield structures are between the first conductive lines and extend along the first direction. A voltage source is electrically coupled to the shield structures through a second set of the capacitors. Some embodiments include assemblies having two or more decks stacked one atop another.

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

Abstract: A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting transistors laterally displaced from one another. A memory device, a thin film transistor control logic assembly, an electronic system, and a method of operating a semiconductor device are also described.

Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material. Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.

Abstract: A light emitting diode package structure and a manufacturing method thereof and a display device are provided. The light emitting diode package structure includes a blue light emitting diode and a phosphor layer. The phosphor layer is disposed on the blue light emitting diode package structure, and the phosphor layer includes an encapsulation layer and a plurality of phosphor powders. The phosphor powders are disposed in the encapsulation layer and consist of green phosphor powders, red phosphor powders, and yellow phosphor powders, in which a weight percentage of the yellow phosphor powders ranges from 1% to 10%.

Abstract: A memory test method and apparatus, an electronic device, and a computer-readable storage medium are provided. The method includes: obtaining a test instruction; generating, in response to the test instruction, a test clock signal, a to-be-tested address and to-be-tested data; determining a to-be-tested memory from memories of a storage device, the storage device including a self-test circuit; writing the to-be-tested data into a storage unit corresponding to the to-be-tested address of the to-be-tested memory; reading output data from the storage unit corresponding to the to-be-tested address of the to-be-tested memory; and comparing the to-be-tested data and the output data to obtain a test result of the to-be-tested memory. The self-test circuit disposed in the storage device is used to implement a memory test process. Thus, the dependency on automatic test equipment is reduced, thereby improving test speed and reducing test cost.

Abstract: A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.

Abstract: An example apparatus includes a three-dimensional (3D) memory array including a sense line and a plurality of vertical stacks. Each respective on of the vertical stacks includes a different respective portion of the sense line, a first memory cell coupled to that portion of the sense line, a second memory cell coupled to that portion of the sense line, a first access line coupled to the first memory cell and a second access line coupled to the second memory cell. The first and second access lines are perpendicular to the sense line.

Abstract: A non-volatile memory device includes a memory cell array, a word line driver, a bit line driver, a read circuit, and control logic. The memory cell array includes a plurality of banks. Each bank includes a plurality of tiles. Each tile includes a plurality of resistive memory cells connected to a plurality of bit lines and a plurality of word lines. The word line driver selects one of the word lines in response to an input address. The bit line driver selects one of the bit lines in response to the input address. The read circuit reads a code word from the memory cell array in a read operation. The control logic is configured to control the word line driver, the bit line driver, the read circuit in the read operation. The control logic performs an address scramble on the input address, and provides the scrambled address to the read circuit to access the plurality of tiles in the read operation.

Abstract: A display apparatus includes a base substrate, a polysilicon active pattern disposed on the base substrate, including polycrystalline silicon, including a source region and a drain region each doped with impurities and a channel region between the source region and the drain region, and including indium, a first gate electrode overlapping the channel region, and a source electrode electrically connected to the source region and a drain electrode electrically connected to the drain region.

Abstract: A magnetic memory and its programming control method and reading method, and a magnetic storage device of the magnetic memory are provided in the present disclosure. The magnetic memory includes a first magnetic tunnel junction memory cell, including a first terminal coupled to a first bit line, and further includes a switch device, including a first terminal coupled to a second terminal of the first magnetic tunnel junction memory cell, and a control terminal connected to a switch control signal. The magnetic memory further includes a second magnetic tunnel junction memory cell, including a first terminal coupled to a second bit line, and a second terminal coupled to a second terminal of the switch device. The magnetic memory further includes a first transistor, a second transistor, and a sensing amplifier.

Abstract: Combinations of resistive change elements and resistive change element arrays thereof are described. Combinational resistive change elements and combinational resistive change element arrays thereof are described. Devices and methods for programming and accessing combinations of resistive change elements are described. Devices and methods for programming and accessing combinational resistive change elements are described.

Abstract: A memory device includes a control logic circuit, a write data strobe signal divider, a data transceiver, and a memory cell array. The control logic circuit generates a reset signal before a write data strobe signal provided from a memory controller starts to toggle. The write data strobe signal divider generates internal write data strobe signals that toggle depending on toggling of the write data strobe signal, the internal write data strobe signals toggling with different phases, respectively. The control logic circuit initializes the internal write data strobe signals to given values in response to the reset signal. The data transceiver receives write data provided from the memory controller based on the internal write data strobe signals. The memory cell array stores the received write data.

Abstract: Described herein are apparatuses, methods, and systems associated with a memory circuit in a three-dimensional (3D) integrated circuit (IC). A control circuit of the memory circuit may include logic transistors in a logic layer of the 3D IC. The control circuit may further include one or more interconnects (e.g., local or global interconnects) and/or other devices in one or more front-side metal layers of the 3D IC. The memory circuit may further include a memory array in back-side metal layers of the 3D IC. The memory array may be formed in the back-side metal layers that are closest to the logic layer. Other embodiments may be described and claimed.

Abstract: A flash memory device includes: first pads; second pads; third pads; a memory cell region including first metal pads and a memory cell array; and a peripheral circuit region including a second metal pads and vertically connected to the memory cell region by the first metal pads and the second metal pads directly. The peripheral circuit region includes a row decoder block; a buffer block storing a command and an address received from an external semiconductor chip through the first pads; a page buffer block connected to the memory cell array through bit lines, connected to the third pads through data lines, and exchanging data signals with the external semiconductor chip through the data lines and the third pads; and a control logic block receiving control signals from the external semiconductor chip through the second pads, and controlling the row decoder block and the page buffer block.

Abstract: A flash memory device includes: first pads; second pads; third pads; a memory cell array; a row decoder block; a buffer block that stores a command and an address received from an external semiconductor chip through the first pads and provides the address to the row decoder block; a page buffer block that is connected to the memory cell array through bit lines, is connected to the third pads through data lines, and exchanges data signals with the external semiconductor chip through the data lines and the third pads; and a control logic block that receives the command from the buffer block, receives control signals from the external semiconductor chip through the second pads, and controls the row decoder block and the page buffer block based on the received command and the received control signals.

Abstract: Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the first portions of the plurality of sense lines and further includes a second array region including second portions of the plurality of sense lines and memory cells coupled to the second portions of the plurality of sense lines. An array gap is disposed between the first and second array regions and includes third portions of the plurality of sense lines and does not include any memory cells. Each third portion of the plurality of sense lines includes conductive structures having vertical components configured to couple the first portions and second portions of the plurality of sense lines to provide an electrically continuous sense lines through the first and second array regions and the array gap.

Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

Abstract: Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

Abstract: A device includes a first reference storage unit, a second reference storage unit, a first reference switch, and a second reference switch. The first reference switch includes a first terminal coupled to a first reference bit line, a second terminal coupled to the first reference storage unit, and a control terminal coupled a reference word line. The second reference switch includes a first terminal coupled to a second reference bit line, a second terminal coupled to the second reference storage unit, and a control terminal coupled the reference word line. The first reference storage unit is configured to receive a bit data through the first reference switch, and to generate a first signal having a first logic state.

Abstract: A memory device and an electronic device including the same are provided. The memory device includes a first memory cell disposed at an intersection of first and second conductive lines that extend in first and second directions, respectively, a second memory cell spaced apart from the first memory cell by a first distance in the first direction, a third memory cell spaced apart from the first memory cell by a second distance in the second direction, a first insulating pattern disposed between the first memory cell and the second memory cell, and a second insulating pattern disposed between the first memory cell and the third memory cell. The second insulating pattern has a lower thermal conductivity than the first insulating pattern.

Abstract: Semiconductor devices and systems are disclosed. A semiconductor device includes a redistribution layer including a first polygonal structure for conveying a first power signal and including a first cutout region. The semiconductor device further includes a second polygonal structure for conveying a second power signal. Further, the semiconductor device includes an island polygon for conveying a third power signal and positioned within the first cutout region, wherein the island polygon does not touch the first polygonal structure.

Abstract: There are provided a data buffer and a memory system having the same. The data buffer includes first and second amplifiers configured to output output data by inverting input data, the first and second amplifiers having coupled output nodes to which the output data is output, wherein both of the first and second amplifiers are activated to output the output data when the input data has a first swing level, and wherein one of the first and second amplifiers is activated to output the output data when the input data has a second swing level narrower than the first swing level.

Abstract: Embodiments provide a chip assembly and a chip. The chip assembly includes a substrate, a first chip and a second chip stacked on an upper surface of the substrate, and the first chip is arranged above the second chip. At edges of first sides of the first chip and the second chip there is provided with a first pad pair, and at edges of second sides of the first chip and the second chip there is provided with a second pad pair. The second pad pair is arranged between two adjacent functional units at an outermost side of the edge of the second side of the first chip or the second chip, and a lower edge of the second pad pair is not lower than lower edges of the two adjacent functional units.

Abstract: A host device and memory device function together to perform internal write leveling of a data strobe with a write command within the memory device. The memory device includes a command interface configured to receive write commands from the host device. The memory device also includes an input-output interface configured to receive the data strobe from the host device. The memory device also includes internal write circuitry configured to launch an internal write signal based at least in part on the write commands. The launch of the internal write signal is based at least in part on an indication from the host device that indicates when to launch the internal write signal relative to a cas write latency (CWL) for the memory device.

Abstract: An integrated circuit structure includes an SRAM array including a first sub-array having a first plurality of rows and a plurality of columns of SRAM cells, and a second sub-array having a second plurality of rows and the plurality of columns of SRAM cells. A first bit-line and a first complementary bit-line are connected to the first and the second pass-gate MOS devices of SRAM cells in a column in the first sub-array. A second bit-line and a second complementary bit-line are connected to the first and the second pass-gate MOS devices of SRAM cells in the column in the second sub-array. The first bit-line and the first complementary bit-line are disconnected from the second bit-line and the second complementary bit-line. A sense amplifier circuit is electrically coupled to, and configured to sense, the first bit-line, the first complementary bit-line, the second bit-line, and the second complementary bit-line.

Abstract: A Read Only Memory (ROM) cell array includes: a first transistor coupled to a first word line; a second transistor coupled to a second word line; and a third transistor disposed between the first transistor and the second transistor, the third transistor having a first gate terminal permanently coupled to a power rail.

Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.

Abstract: A semiconductor memory device includes a plurality of page buffers defined in active regions of a substrate; and a plurality of wiring lines disposed over the page buffers, and coupled to the page buffers through contacts. The plurality of wiring lines may include contact portions which are coupled with the contacts, respectively. The plurality of wiring lines may be configured into a bent shape such that the contact portions are offset toward center lines of the active regions.

Abstract: Examples may include techniques to improve a read operation to a memory array. Examples include identifying characteristics of memory cells in the memory array such as relative positions of memory cells within the memory array and then set multiple read reference voltages or currents to detect a memory state of memory cells based on identified characteristics.

Abstract: A memory device comprising: a plurality of memories, a plurality of access units and a controller configured to control data from an access unit according to operation cycle different to another access unit whose form factor is different to that of the access unit.

Abstract: A memory system may include a controller; and a plurality of memory modules, wherein a data input and output of the plurality of memory modules is performed with a single channel manner according to an address signal provided from the controller in common, wherein each of the plurality of memory modules includes a buffer chip and a plurality of memory chips coupled to the buffer chip, wherein all the buffer chips of the plurality of memory modules are directly coupled to the controller through independent input and output bus.

Abstract: A a semiconductor storage device includes a logic circuit formed on a substrate, a first area formed on the logic circuit and has a plurality of first insulating layers and a plurality of conductive layers alternatively stacked in a first direction, a plurality of memory pillars MP which extend in the first area in the first direction, a second area which is formed on the logic circuit and has the plurality of first insulating layers 33 and a plurality of second insulating layers alternately stacked in the first direction, and a contact ping CP1 which extends in the second area in the first direction and is connected to the logic circuit.