Particular Current Control Structure Patents (Class 372/46.01)
  • Patent number: 11824322
    Abstract: A laser device with one or more active regions, such as quantum wells, gain/lighting media, or other devices, and one or more non-absorbing regions, may be formed by a first growth run (growing a first semiconductor layer), then performing selective, shallow-depth etching, and then a second growth run (growing a second semiconductor layer). The laser device may include a first portion, one or more active regions located on the first portion, and a second portion located on the active region(s). A third portion may be located on one or more ends of the first portion and on the second portion. The third portion may be formed during the second growth run, after the etching step. The non-absorbing region(s) may be formed by the third portion and the end(s) of the first portion. If desired, the non-absorbing region(s) may be produced without annealing or locally-induced quantum well intermixing.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: November 21, 2023
    Assignee: II-VI DELAWARE, INC.
    Inventors: René Todt, Markus Rösch, Evgeny Zibik, Susanne Pawlik, Gustavo F. Villares
  • Patent number: 11817674
    Abstract: A semiconductor optical device may include a semiconductor substrate; a compound semiconductor layer on the semiconductor substrate; an additional insulating film on the pedestal portion of the compound semiconductor layer, the additional insulating film having an upper surface and a side surface at an inner obtuse angle between them; a passivation film covering the compound semiconductor layer and the additional insulating film except at least part of the mesa portion, the passivation film having a protrusion raised by overlapping with the additional insulating film; a mesa electrode on the at least part of the mesa portion; a pad electrode on the passivation film within the protrusion; and an extraction electrode on the passivation film, the extraction electrode being continuous within and outside the protrusion, the extraction electrode connecting the pad electrode and the mesa electrode, the extraction electrode being narrower in width than the pad electrode.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: November 14, 2023
    Assignee: Lumentum Japan, Inc.
    Inventors: Ryosuke Nakajima, Yasushi Sakuma, Shigetaka Hamada
  • Patent number: 11735888
    Abstract: A method for producing a semiconductor optical device includes the steps of bonding a semiconductor chip to an SOI substrate having a waveguide, the semiconductor chip having an optical gain and including a first cladding layer, a core layer, and a second cladding layer that contain III-V group compound semiconductors and are sequentially stacked in this order, forming a covered portion with a first insulating layer on the second cladding layer, etching partway in the thickness direction the second cladding layer exposed from the first insulating film, forming a second insulating film covering from the covered portion to a part of a remaining portion of the second cladding layer, and forming a first tapered portion that is disposed on the waveguide and tapered along the extending direction of the waveguide by etching the core layer and the second cladding layer exposed from the second insulating film.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: August 22, 2023
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Naoki Fujiwara, Hideki Yagi, Takuo Hiratani, Takehiko Kikuchi, Toshiyuki Nitta
  • Patent number: 11714230
    Abstract: An environmentally protected PIC, including an InP-based substrate having a first surface that is at least partially provided with an InP-based optical waveguide, and a dielectric protective layer arranged to cover at least the first surface of the InP-based substrate and the InP-based optical waveguide. The dielectric protective layer is configured to protect said PIC from environmental contaminants, to enable confinement of optical radiation in the dielectric protective layer in at least one direction that is transverse to a direction of propagation of the optical radiation, and to allow exchange of the optical radiation between the InP-based optical waveguide and the dielectric protective layer. An opto-electronic system including PIC.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: August 1, 2023
    Assignee: EFFECT PHOTONICS B.V.
    Inventor: Tsjerk Hans Hoekstra
  • Patent number: 11703453
    Abstract: Building blocks are provided for on-chip chemical sensors and other highly-compact photonic integrated circuits combining interband or quantum cascade lasers and detectors with passive waveguides and other components integrated on a III-V or silicon. A MWIR or LWIR laser source is evanescently coupled into a passive extended or resonant-cavity waveguide that provides evanescent coupling to a sample gas (or liquid) for spectroscopic chemical sensing. In the case of an ICL, the uppermost layer of this passive waveguide has a relatively high index of refraction that enables it to form the core of the waveguide, while the ambient air, consisting of the sample gas, functions as the top cladding layer. A fraction of the propagating light beam is absorbed by the sample gas if it contains a chemical species having a fingerprint absorption feature within the spectral linewidth of the laser emission.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: July 18, 2023
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Jerry R. Meyer, Igor Vurgaftman, Chadwick Lawrence Canedy, William W. Bewley, Chul Soo Kim, Charles D. Merritt, Michael V. Warren, R. Joseph Weiblen, Mijin Kim
  • Patent number: 11664641
    Abstract: A light source device includes: a plurality of laser sources; a plurality of collimating parts, each configured to collimate the light beam emitted from a corresponding one of the laser sources; a combining grating configured to diffract, at an identical diffraction angle, light beams that have passed through the collimating parts and are incident on the combining grating at different incident angles to combine the diffracted light beams; and a plurality of volume holographic gratings, wherein each of the volume holographic gratings is disposed in an optical path between a corresponding one of the laser sources and the combining grating, wherein each of the volume holographic gratings determines a wavelength of the light beam incident on the combining grating, and wherein each of the volume holographic gratings is configured to diffract a portion of the light beam emitted from a corresponding laser source back to the laser source.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: May 30, 2023
    Assignee: NICHIA CORPORATION
    Inventors: Norihiro Dejima, Masaki Omori
  • Patent number: 11616341
    Abstract: Exemplary embodiments of the present disclosure include chip-scale laser sources, such as semiconductor laser sources, that produce directional beams with low spatial coherence. The lasing modes are based on the axial orbit in a stable cavity and have good directionality. To reduce the spatial coherence of emission, the number of transverse lasing modes can be increased by fine-tuning the cavity geometry. Decoherence is reached in as little as several nanoseconds. Such rapid decoherence facilitates applications in ultrafast speckle-free full-field imaging.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: March 28, 2023
    Assignee: Yale University
    Inventors: Hui Cao, Stefan Wolfgang Bittner, Kyungduk Kim
  • Patent number: 11616343
    Abstract: A VCSEL may include an n-type substrate layer and an n-type bottom mirror on a surface of the n-type substrate layer. The VCSEL may include an active region on the n-type bottom mirror and a p-type layer on the active region. The VCSEL may include an oxidation layer over the active region to provide optical and electrical confinement of the VCSEL. The VCSEL may include a tunnel junction over the p-type layer to reverse a carrier type of an n-type top mirror. Either the oxidation layer is on or in the p-type layer and the tunnel junction is on the oxidation layer, or the tunnel junction is on the p-type layer and the oxidation layer is on the tunnel junction. The VCSEL may include the n-type top mirror over the tunnel junction, a top contact layer over the n-type top mirror, and a top metal on the top contact layer.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: March 28, 2023
    Assignee: Lumentum Operations LLC
    Inventors: Jun Yang, Guowei Zhao, Matthew Glenn Peters, Eric R. Hegblom, Ajit Vijay Barve, Benjamin Kesler
  • Patent number: 11594859
    Abstract: A light emitting element includes: a laminated structure 20 obtained by laminating a first compound semiconductor layer 21, an active layer 23, and a second compound semiconductor layer 22; a first light reflecting layer 41 disposed on a first surface side of the first compound semiconductor layer 21; a second light reflecting layer 42 disposed on a second surface side of the second compound semiconductor layer 22; and light convergence/divergence changing means 50. The first light reflecting layer 41 is formed on a concave mirror portion 43. The second light reflecting layer 42 has a flat shape. When light generated in the active layer 23 is emitted to the outside, a light convergence/divergence state before the light is incident on the light convergence/divergence changing means 50 is different from a light convergence/divergence state after the light passes through the light convergence/divergence changing means 50.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: February 28, 2023
    Assignee: Sony Corporation
    Inventors: Jugo Mitomo, Tatsushi Hamaguchi, Hiroshi Nakajima, Masamichi Ito, Susumu Sato
  • Patent number: 11495942
    Abstract: A laser diode, comprising a transverse waveguide that is orthogonal to the lateral waveguide comprising an active layer between an n-type waveguide layer and a p-type waveguide layer, wherein the transverse waveguide is bounded by an n-type cladding layer on an n-side and p-type cladding layer on a p-side and a lateral waveguide bounded in a longitudinal direction at a first end by a high reflector (HR) coated facet and at a second end by a partial reflector (PR) coated facet, the lateral waveguide further comprising a buried higher order mode suppression layer (HOMSL) disposed beneath the p-cladding within the lateral waveguide or on one or both sides of the lateral waveguide or a combination thereof, wherein the HOMSL extends in a longitudinal direction from the HR facet a length less than the distance between the HR facet and the PR facet.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: November 8, 2022
    Assignee: NLIGHT, INC.
    Inventors: Manoj Kanskar, Zhigang Chen, Nicolas Biekert
  • Patent number: 11466384
    Abstract: A method for forming a laterally-grown group III metal nitride crystal includes providing a substrate, the substrate including one of sapphire, silicon carbide, gallium arsenide, silicon, germanium, a silicon-germanium alloy, MgAl2O4 spinel, ZnO, ZrB2, BP, InP, AlON, ScAlMgO4, YFeZnO4, MgO, Fe2NiO4, LiGa5O8, Na2MoO4, Na2WO4, In2CdO4, lithium aluminate (LiAlO2), LiGaO2, Ca8La2(PO4)6O2, gallium nitride, or aluminum nitride (AlN), forming a pattern on the substrate, the pattern comprising growth centers having a minimum dimension between 1 micrometer and 100 micrometers, and being characterized by at least one pitch dimension between 20 micrometers and 5 millimeters, growing a group III metal nitride from the pattern of growth centers vertically and laterally, and removing the laterally-grown group III metal nitride layer from the substrate.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: October 11, 2022
    Assignee: SLT Technologies, Inc.
    Inventors: Mark P. D'Evelyn, Derrick S. Kamber
  • Patent number: 11456363
    Abstract: An indium phosphide crystal substrate has a diameter of 100-205 mm and a thickness of 300-800 ?m and includes any of a flat portion and a notch portion. In any of a first flat region and a first notch region, when an atomic concentration of sulfur is from 2.0×1018 to 8.0×1018 cm?3, the indium phosphide crystal substrate has an average dislocation density of 10-500 cm?2, and when am atomic concentration of tin is from 1.0×1018 to 4.0×1018 cm?3 or an atomic concentration of iron is from 5.0×1015 to 1.0×1017 cm?3, the indium phosphide crystal substrate has an average dislocation density of 500-5000 cm?2.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: September 27, 2022
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Muneyuki Nishioka, Kazuaki Konoike, Takuya Yanagisawa, Yasuaki Higuchi, Yoshiaki Hagi
  • Patent number: 11451009
    Abstract: A vertical cavity surface emitting laser (VCSEL) may include a top contact, wherein the top contact is associated with a particular shape, and wherein the particular shape is a toothed shape with a particular quantity of teeth. The VCSEL may include at least one implanted region. The VCSEL may include at least one top contact segment.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: September 20, 2022
    Assignee: Lumentum Operations LLC
    Inventors: Pengfei Qiao, Chien-Yao Lu, Albert Yuen
  • Patent number: 11424388
    Abstract: Provided is a light-emitting device including a substrate, a light-emitting pattern provided on the substrate, a first reflection film provided between the light-emitting pattern and the substrate, a second reflection film provided on a side surface of the light-emitting pattern, and a passivation film provided between the light-emitting pattern and the second reflection film, wherein the second reflection film is electrically connected to the light-emitting pattern, and a portion of light generated from the light-emitting pattern is emitted through an upper surface of the light-emitting pattern after being reflected by at least one of the first reflection film and the second reflection film.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: August 23, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junhee Choi, Kiho Kong, Jinjoo Park, Joohun Han, Kyungwook Hwang, Sungjin Kang, Junghun Park
  • Patent number: 11404269
    Abstract: A single crystal substrate is provided and is characterized in that the single crystal substrate has a foundation substrate provided with a plurality of first grooves, which include a first crystal face and a second crystal face opposed to the first crystal face in an inner face thereof, and the extending direction of which is a<110> direction, and a plurality of second grooves, the extending direction of which intersects with the first grooves, and in which the first grooves are formed in a displaced manner in a depth direction, and a transverse cross-sectional shape of the second groove is a shape in which straight lines are open at an opening angle less than 180°. Further, it is preferred that an angle formed by the first crystal face and the second crystal face is more than 70.6°.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: August 2, 2022
    Inventors: Yukimune Watanabe, Noriyasu Kawana
  • Patent number: 11355899
    Abstract: An optical device includes a light-emitting device integrated with a memory device. The memory device include a first electrode and a second electrode, and the light-emitting device includes a third electrode and the second electrode. In such configuration, a first voltage between the second electrode and the third electrode causes the light-emitting device to emit light of a first wavelength, and a second voltage between the first electrode and the second electrode while the memory device is at OFF state causes the light-emitting device to emit light of a second wavelength shorter than the first wavelength or while the memory device is at ON state causes the light-emitting device to emit light of a third wavelength longer than the first wavelength.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: June 7, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Bassem Tossoun, Di Liang, John Paul Strachan
  • Patent number: 11322909
    Abstract: A semiconductor laser device includes: a first semiconductor layer of a first conductivity type; a light emitting layer formed above the first semiconductor layer; a second semiconductor layer of a second conductivity type formed above the light emitting layer; and an electrode formed above a ridge portion formed in the second semiconductor layer. The electrode is divided at positions at which an integrated value of light intensities of higher-order mode oscillation has a local maximum.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: May 3, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masao Kawaguchi, Shinichi Takigawa, Nozomi Naka
  • Patent number: 11196230
    Abstract: An emitter array may comprise a plurality of emitters and a metallization layer to electrically connect the plurality of emitters. The metallization layer may have a first end and a second end. The plurality of emitters may include a first emitter and a second emitter. The first emitter may be located closer to the first end than the second emitter. The first emitter and the second emitter have differently sized structures to compensate for a first impedance of the metallization layer between the first end and the first emitter and a second impedance between the first end and the second emitter.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: December 7, 2021
    Assignee: Lumentum Operations LLC
    Inventors: Ajit Vijay Barve, Benjamin Kesler, Matthew Glenn Peters
  • Patent number: 11196228
    Abstract: A pixel structure for a vertical cavity surface emitting laser has an emission window. The pixel structure includes a plurality of sub-pixels in the emission window. Bright-area sub-pixels emit light and dark-area sub-pixels having no light emission. The bright-area sub-pixels and the dark-area sub-pixels are arranged in a pattern in the emission window. Various patterns are possible. Different structures for implementing the sub-pixels are described.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: December 7, 2021
    Assignee: Vertilite Co., Ltd.
    Inventors: Dong Liang, Yijie Huo, Song Liu
  • Patent number: 11189991
    Abstract: A semiconductor optical element is configured to emit or absorb light and includes a lower structure that includes a multiple quantum well layer; an upper mesa structure that is disposed on the lower structure; a current injection structure that is disposed on the upper mesa structure, when seen from an optical axis of the emitted or absorbed light, a width of a portion of the current injection structure in contact with the upper mesa structure is smaller than a width of the upper mesa structure, the portion of the current injection structure in contact with the upper mesa structure consisting of InP, and an average refractive index of the upper mesa structure is higher than a refractive index of the InP forming the current injection structure; and an insulating film covering both side surfaces of the upper mesa structure and a part of an upper surface of the upper mesa structure.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: November 30, 2021
    Assignee: Lumentum Japan, Inc.
    Inventors: Kouji Nakahara, Kazuki Suga
  • Patent number: 11171125
    Abstract: A display device including a pixel circuit, an insulation layer covering the pixel circuit, an etching prevention layer disposed on the insulation layer, a first guide layer, a second guide layer, a first electrode, a second electrode, and a light emitting element. The first guide layer and the second guide layer may be disposed on the etching prevention layer and spaced apart from each other. The first electrode may be disposed on the first guide layer and electrically connected to the pixel circuit. The second electrode may be disposed on the first guide layer and insulated from the first electrode. The light emitting element may be in contact with the top surface of the etching prevention layer, disposed between the first guide layer and the second guide layer on a plane, and electrically connected to the first electrode and the second electrode.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: November 9, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Euikang Heo, Cha-Dong Kim, Hyunae Kim, Chongsup Chang
  • Patent number: 11152762
    Abstract: A semiconductor laser device of an edge emission type, where a waveguide mode is multi-mode, is provided. The semiconductor laser device includes a first facet of the waveguide on an emission direction front side, the first facet having a first width in a horizontal direction perpendicular to a longitudinal direction of the waveguide; and a second facet of the waveguide on an emission direction rear side, the second facet having the first width, wherein a width of the waveguide, in the horizontal direction, is at least partially narrower than the first width, between the first facet and the second facet.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: October 19, 2021
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Eisaku Kaji, Yutaka Ohki
  • Patent number: 11088503
    Abstract: One illustrative laser disclosed herein includes a gain medium layer having a first width in a transverse direction that is orthogonal to a laser emitting direction of the laser, and an upper light-confining structure positioned above an upper surface of the gain medium layer, wherein the upper light-confining structure has a second width in the transverse direction that is equal to or less than the first width and comprises at least one material having an index of refraction that is at least 2.0. The laser also includes a lower light-confining structure positioned below a lower surface of the gain medium layer, wherein the lower light-confining structure has a third width in the transverse direction that is equal to or less than the first width and comprises at least one material having an index of refraction that is at least 2.0.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: August 10, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Yusheng Bian, Ajey Poovannummoottil Jacob
  • Patent number: 11061186
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to rib waveguide structures and methods of manufacture. The structure includes: a waveguide structure comprising one or more bends, an input end and an output end; and grating structures which are positioned adjacent to the one or more bends of the waveguide structure.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: July 13, 2021
    Assignees: GLOBALFOUNDRIES U.S. INC., KHALIFA UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Ajey Poovannummoottil Jacob, Marcus V. S. Dahlem, Humaira Zafar, Anatol Khilo, Sujith Chandran
  • Patent number: 11011663
    Abstract: A semiconductor element which oscillates or detects a terahertz wave, the semiconductor element comprising: a first electrode; a semiconductor layer having a gain of the terahertz wave; a second electrode which forms a mesa structure together with the semiconductor layer; a third electrode; a fourth electrode; a first dielectric layer which is in contact with the third electrode and which surrounds the mesa structure; and a second dielectric layer which is arranged between the first electrode and the fourth electrode, which surrounds the third electrode, and which is made of a different material from the first dielectric layer, wherein the first electrode, the semiconductor layer, the second electrode, the third electrode, and the fourth electrode are stacked in this order from a side of the substrate in a direction perpendicular to the substrate, and a predetermined mathematical expression is satisfied.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: May 18, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasushi Koyama, Jun Iba
  • Patent number: 10985533
    Abstract: A semiconductor laser device includes: a first semiconductor layer on a first conductivity side; a second semiconductor layer on the first conductivity side; an active layer; a third semiconductor layer on a second conductivity side different from the first conductivity side; and a fourth semiconductor layer on the second conductivity side. Eg2<Eg3 is satisfied, where Eg2 and Eg3 denote maximum values of band gap energy of the second semiconductor layer and the third semiconductor layer, respectively. The third semiconductor layer includes a first region layer in which band gap energy monotonically decreases toward the fourth semiconductor layer. N2>N3 is satisfied, where N2 denotes an impurity concentration of the second semiconductor layer, and N3 denotes an impurity concentration of the third semiconductor layer.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 20, 2021
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Tougo Nakatani, Takahiro Okaguchi, Norio Ikedo, Takeshi Yokoyama, Tomohito Yabushita, Toru Takayama, Shoichi Takasuka
  • Patent number: 10938179
    Abstract: Provided are an addressable laser array device and an electronic apparatus including the addressable laser array device. The addressable laser array device includes a plurality of VCSELs, each including a distributed Bragg reflector (DBR), a nanostructure reflector including a plurality of nanostructures having a sub-wavelength dimension, and a gain layer disposed between the DBR and the nanostructure reflector; a plurality of first wiring patterns extending in a first direction and being electrically connected to the plurality of VCSELs, respectively; and a plurality of second wiring patterns extending in a second direction intersecting the first direction and being electrically connected to the plurality of VCSELs, respectively, wherein the plurality of VCSELs are disposed at intersections of the plurality of first wiring patterns and the plurality of second wiring patterns, and the addressable VCSEL array device is configured to selectively drive at least some of the plurality of VCSELs.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: March 2, 2021
    Assignees: SAMSUNG ELECTRONICS CO., LTD., UNIVERSITY OF MASSACHUSETTS
    Inventors: Byunghoon Na, Mahdad Mansouree, Seunghoon Han, Amir Arbabi
  • Patent number: 10938180
    Abstract: An optoelectronic component includes a layer structure including an active zone that generates electromagnetic radiation, wherein the active zone is arranged in a plane, the layer structure includes a top side and four side faces, the first and third side faces are arranged opposite one another, the second and fourth side faces are arranged opposite one another, a strip-type ridge structure is arranged on the top side of the layer structure, the ridge structure extends between the first side face and the third side face, the first side face constitutes an emission face for electromagnetic radiation, a first recess is introduced into the top side of the layer structure laterally alongside the ridge structure, a second recess is introduced into the first recess, and the second recess extends as far as the second side face.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: March 2, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Sven Gerhard, Alfred Lell, Clemens Vierheilig, Andreas Löffler
  • Patent number: 10916917
    Abstract: A method of manufacturing a surface emitting laser includes: forming a mesa by performing etching on a lower reflector layer, an active layer, and an upper reflector layer; forming a current narrowing layer by oxidizing a part of the upper reflector layer; exposing a substrate by performing etching on the lower reflector layer, the active layer, and the upper reflector layer, using a chlorine-containing gas; cleaning the substrate; performing heat treatment on the substrate; forming an insulating film covering a surface of the substrate; forming an electrode on the lower reflector layer and the upper reflector layer; and performing heat treatment on the substrate, wherein a temperature in the first heat treatment is lower than a temperature in the forming the current narrowing layer.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: February 9, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Yukihiro Tsuji
  • Patent number: 10903624
    Abstract: A semiconductor laser element includes a first nitride semiconductor layer of a first conductivity-type; a second nitride semiconductor layer of a second conductivity-type; and an active region disposed between the first nitride semiconductor layer and the second nitride semiconductor layer. The active region includes a first barrier layer, an intermediate layer, a well layer and a second barrier layer. A lattice constant of the intermediate layer is greater than a lattice constant of each of the first barrier layer and the second barrier layer, and smaller than a lattice constant of the well layer. A thickness of the intermediate layer is greater than a thickness of the well layer. The well layer and the second barrier layer are in contact with each other, or a distance between the well layer and the second barrier layer is smaller than a distance between the first barrier layer and the well layer.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: January 26, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Yoji Nagao
  • Patent number: 10896969
    Abstract: A manufacturing method of an HEMT includes: forming a heterostructure; forming a first gate layer of intrinsic semiconductor material on the heterostructure; forming a second gate layer, containing dopant impurities of a P type, on the first gate layer; removing first portions of the second gate layer so that second portions, not removed, of the second gate layer form a doped gate region; and carrying out a thermal annealing of the doped gate region so as to cause a diffusion of said dopant impurities of the P type in the first gate layer and in the heterostructure, with a concentration, in the heterostructure, that decreases as the lateral distance from the doped gate region increases.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: January 19, 2021
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Ferdinando Iucolano
  • Patent number: 10892597
    Abstract: A nitride semiconductor laser includes: a first nitride semiconductor layer; a light-emitting layer formed on the first nitride semiconductor layer and including a nitride semiconductor; a second nitride semiconductor layer formed on the light-emitting layer and having a ridge portion; an electrode component formed on the second nitride semiconductor layer, and which is wider than the ridge portion; and a dielectric layer formed on side surfaces of the ridge portion and including SiO2. A space is present between the electrode component and the dielectric layer, and the electrode component is prevented from being in contact with the dielectric layer by the space, and is in contact with the upper surface of the ridge portion.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: January 12, 2021
    Assignee: PANASONIC CORPORATION
    Inventors: Hiroyuki Hagino, Osamu Imafuji, Shinichiro Nozaki
  • Patent number: 10847950
    Abstract: A vertical cavity surface emitting laser includes: a supporting base; and a post including an upper distributed Bragg reflecting region, an active layer, and a lower distributed Bragg reflecting region. The upper distributed Bragg reflecting region, the active layer, and the lower distributed Bragg reflecting region are arranged on the supporting base. The lower distributed Bragg reflecting region includes first semiconductor layers and second semiconductor layers alternately with each of the first semiconductor layers having a refractive index lower than that of each of the second semiconductor layers. The upper distributed Bragg reflecting region includes first layers and second layers alternately with each of the first layers having a group III-V compound semiconductor portion and a group III oxide portion. The group III-V compound semiconductor portion contains aluminum as a group III constituent element, and the group III oxide portion surrounds the group III-V compound semiconductor portion.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 24, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Yutaka Onishi
  • Patent number: 10843381
    Abstract: An LED wafer processing method includes a dividing step of rotatably mounting a first cutting blade having a first width in a first cutting unit, holding an LED wafer on a holding table, and then relatively moving the first cutting unit and the holding table to cut the wafer along each division line formed on the wafer, thereby forming a full-cut groove along each division line to thereby divide the wafer into individual chips. The method further includes rotatably mounting a second cutting blade having a second width larger than the first width in a second cutting unit after performing the dividing step, and then relatively moving the second cutting unit and the holding table to thereby polish the opposed side surfaces of the full-cut groove formed along each division line, whereby a polished groove larger in width than the full-cut groove is formed along each full-cut groove.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: November 24, 2020
    Assignee: DISCO CORPORATION
    Inventor: Makiko Ohmae
  • Patent number: 10840419
    Abstract: The present application discloses a nitride semiconductor light-emitting device and a manufacture method thereof. The nitride semiconductor light-emitting device includes an epitaxial structure, wherein the epitaxial structure has a first face and a second face opposite to the first face, the first face is a (0001) nitrogen face and located at the n type side of the epitaxial structure, the second face is located at the p type side of the epitaxial structure, the n type side of the epitaxial structure is electrically contacted with an n type electrode, the p type side is electrically contacted with a p type electrode, and a ridge waveguide structure is formed on the first face.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: November 17, 2020
    Assignee: Suzhou Institute of Nano-Tech and Nano-Bionics (Sinano), Chinese Academy of Sciences
    Inventors: Qian Sun, Meixin Feng, Yu Zhou, Hongwei Gao, Hui Yang
  • Patent number: 10833476
    Abstract: A surface-mountable semiconductor laser and an arrangement with such a semiconductor laser are disclosed. In one embodiment, the semiconductor laser is includes a semiconductor layer sequence having at least one generation region between a p-side and an n-side, at least two contact surfaces for external electrical contacting of the p-side and the n-side, wherein the contact surfaces are located on the same side of the semiconductor layer sequence in a common plane so that the semiconductor laser are contactable without bonding wires, at least one of a plurality of conductor rails extending from a side with the contact surfaces across the semiconductor layer sequence and a plurality of through-connections running at least through the generation region, wherein the generation region is configured to be pulse operated with time-wise current densities of at least 30 A/mm2.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: November 10, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Martin Müller, Hubert Halbritter
  • Patent number: 10825734
    Abstract: A method and stacked semiconductor device having a top surface, a bottom surface, and at least one side surface that connects the top surface with the bottom surface. The bottom surface is formed of a substrate layer or a rear side contact layer arranged below the substrate layer. On the substrate layer, a first semiconductor layer of a first conductivity type is arranged and on the first semiconductor layer at least one second semiconductor layer of a second conductivity type is arranged. The first and second semiconductor layers are formed of a III-V material or consist of a III-V material. The first and second conductivity types are different. The top surface is at least partially formed by a passivation layer. Along the side surface, an amorphized and/or insulating region extending to a depth is formed, and the depth is perpendicular or substantially perpendicular to the layer stack.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: November 3, 2020
    Assignee: 3-5 Power Electronics GmbH
    Inventor: Volker Dudek
  • Patent number: 10811843
    Abstract: The disclosure relates to a semiconductor laser includes a semiconductor layer sequence with an-n-type n-region, a p-type p-region and an active zone lying between the two for the purpose of generating laser radiation. A p-contact layer that is permeable to the laser radiation and consists of a transparent conductive oxide is located directly on the p-region for the purpose of current input. An electrically-conductive metallic p-contact structure is applied directly to the p-contact layer. The p-contact layer is one part of a cover layer, and therefore the laser radiation penetrates as intended into the p-contact layer during operation of the semiconductor laser. Two facets of the semiconductor layer sequence form resonator end surfaces for the laser radiation.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: October 20, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Sven Gerhard, Alfred Lell, Clemens Vierheilig, Andreas Loeffler, Christoph Eichler
  • Patent number: 10784649
    Abstract: A semiconductor laser (2) includes an n-type semiconductor substrate (1), a stack of an n-type cladding layer (4), an active layer (5), and a p-type cladding layer (6) successively stacked on the n-type semiconductor substrate (1). An optical waveguide (3) includes a non-impurity-doped core layer (9) provided on a light output side of the semiconductor laser (2) on the n-type semiconductor substrate (1) and having a larger forbidden band width than the active layer (5), and a cladding layer (10) provided on the core layer (9) and having a lower carrier concentration than the p-type cladding layer (6). The semiconductor laser (2) includes a carrier injection region (X1), and a non-carrier-injection region (X2) provided between the carrier injection region (X1) and the optical waveguide (3).
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: September 22, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Go Sakaino, Naoki Nakamura, Yuichiro Okunuki
  • Patent number: 10770864
    Abstract: A surface emitting laser includes a conductive substrate, a metal bonding layer, a laser structure layer, an epitaxial semiconductor reflection layer, and an electrode layer. The laser structure layer has an epitaxial current-blocking layer having a current opening. Currents are transmitting through the current opening. The epitaxial current-blocking layer is grown by a semiconductor epitaxy process to confine the range of the currents to form electric fields.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: September 8, 2020
    Assignee: TREND LIGHTING CORP.
    Inventors: Jonathan Wang, Pei-Chin Hsieh, Pei-Jih Wang, Shih-Chieh Cheng
  • Patent number: 10714901
    Abstract: In an embodiment a laser include a semiconductor layer sequence having an active zone for generating radiation and an electrical contact web arranged on a top side of the semiconductor layer sequence, wherein the contact web is located on the top side only in an electrical contact region or is in electrical contact with the top side only in the contact region so that the active zone is supplied with current only in places during operation, wherein the contact web comprises a plurality of metal layers at least partially stacked one above the other, wherein at least one of the metal layers comprises a structuring so that the at least one metal layer only partially covers the contact region and has at least one opening or interruption, and wherein the structuring reduces stresses of the semiconductor layer sequence on account of different thermal expansion coefficients of the metal layers.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: July 14, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Bernhard Stojetz, Georg Brüderl
  • Patent number: 10693277
    Abstract: A non-planarized VCSEL can include: a blocking region over or under an active region, the blocking region having a first thickness; one or more conductive channel cores in the blocking region, the one or more conductive channel cores having a second thickness that is larger than the first thickness, wherein the blocking region is defined by having an implant and the one or more conductive channel cores are devoid of the implant, wherein the blocking region is lateral the one or more conductive channel cores, the blocking region and one or more conductive channel cores being an isolation region; and a non-planarized semiconductor region of one or more non-planarized semiconductor layers over the isolation region. The VCSEL can include a planarized bottom mirror region below the active region and a non-planarized top mirror region above the isolation region, or a non-planarized bottom mirror region below the active region.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: June 23, 2020
    Assignee: II-VI Delaware Inc.
    Inventors: Luke A. Graham, Sonia Quadery, Deepa Gazula, Haiquan Yang
  • Patent number: 10673207
    Abstract: The invention relates to, inter alia, a light-emitting semiconductor component comprising the following: —a first mirror (102, 202, 302, 402, 502), —a first conductive layer (103, 203, 303, 403, 503), —a light-emitting layer sequence (104, 204, 304, 404, 504) on a first conductive layer face facing away from the first mirror, and—a second conductive layer (105, 205, 305, 405, 505) on a light-emitting layer sequence face facing away from the first conductive layer, wherein—the first mirror, the first conductive layer, the light-emitting layer sequence, and the second conductive layer are based on a III-nitride compound semiconductor material, —the first mirror is electrically conductive, and—the first mirror is a periodic sequence of homoepitaxial materials with varying refractive indices.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: June 2, 2020
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Armin Dadgar, André Strittmatter, Christoph Berger
  • Patent number: 10658531
    Abstract: A photodiode fabricated using spalling techniques, and method for making the same. The photodiode including a substrate, an optical device semiconductor material layer disposed over the substrate, a p-type contact disposed over the optical device semiconductor material layer, an n-type contact disposed over the substrate, and an adhesion layer for rear illumination adhered to the bottom of the substrate. Both the substrate and the optical device semiconductor material layer comprise at least one of GaN, AlGaN or AlN.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, James R. Kozloski, Devendra K. Sadana
  • Patent number: 10658816
    Abstract: The invention relates to a distributed feedback laser diode (10) comprising a waveguide with a gain medium assisted by a network formed by a distribution of elements (22) including a sub-set comprising localised resonators (24) distributed along the axis of the waveguide, characterised in that the frequency characteristic of the feedback induced on the wave of the guide by the spatial distribution of said elements differs by less than 50% of the resonance frequency of said localised resonators.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: May 19, 2020
    Assignees: UNIVERSITE PARIS SUD, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Anatole Lupu, Natalia Dubrovina, Abderrahim Ramdane, Henri Benisty
  • Patent number: 10636724
    Abstract: A mount structure having a joining capable of withstanding development of cracks generated by thermal stress due to repeated temperature changes in a mount structure having the joining of a large area is formed by joining a ceramic substrate electrode of a ceramic substrate and a metal substrate electrode of a metal substrate by a laminate, in which the laminate is formed by stacking a first interface layer, a first solder joining portion, a second interface layer, a first buffer material electrode, a buffer material, a second buffer material electrode, a third interface layer, a second solder joining portion and a fourth interface layer in this order from the ceramic substrate electrode toward the metal substrate electrode, a thickness of the laminate is 30 ?m or more and 100 ?m or less, a difference between a thickness of the first solder joining portion and a thickness of the second solder joining portion is within 25%, and differences in elastic moduli and in linear expansion coefficients between the firs
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: April 28, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTTD.
    Inventors: Kiyohiro Hine, Akio Furusawa, Hidetoshi Kitaura, Kazuki Sakai
  • Patent number: 10627055
    Abstract: A method and device for emitting electromagnetic radiation at high power using a gallium containing substrates such as GaN, AlN, InN, InGaN, AlGaN, and AlInGaN, is provided.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: April 21, 2020
    Assignee: Soraa Laser Diode, Inc.
    Inventor: Eric Goutain
  • Patent number: 10630057
    Abstract: In an embodiment a laser include a semiconductor layer sequence having an active zone for generating radiation and an electrical contact web arranged on a top side of the semiconductor layer sequence, wherein the contact web is located on the top side only in an electrical contact region or is in electrical contact with the top side only in the contact region so that the active zone is supplied with current only in places during operation, wherein the contact web comprises a plurality of metal layers at least partially stacked one above the other, wherein at least one of the metal layers comprises a structuring so that the at least one metal layer only partially covers the contact region and has at least one opening or interruption, and wherein the structuring reduces stresses of the semiconductor layer sequence on account of different thermal expansion coefficients of the metal layers.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: April 21, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Bernhard Stojetz, Georg Brüderl
  • Patent number: 10593838
    Abstract: The embodiment discloses a semiconductor device which includes: a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer; a first electrode electrically connected to the first conductive semiconductor layer; a second electrode electrically connected to the second conductive semiconductor layer; a first cover electrode disposed on the first electrode; and an insulation layer disposed between the first electrode and the second electrode, wherein the insulation layer comprises a first insulation portion disposed between the first conductive semiconductor layer and the first cover electrode, and a second insulation portion disposed on the first cover electrode, wherein the first cover electrode comprises a first protrusion portion disposed between an upper surface of the first insulation portion and a lower surface of the second insulation portion.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: March 17, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Youn Joon Sung, Jin Soo Park, Rak Jun Choi
  • Patent number: RE48774
    Abstract: Disclosed is a semiconductor light emitting device. The semiconductor light emitting device includes a plurality of compound semiconductor layers including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer; a pad on the plurality of compound semiconductor layers; an electrode layer under the plurality of compound semiconductor layers; and a supporting member disposed under the plurality of compound semiconductor layers and corresponding to the pad.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: October 12, 2021
    Assignee: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
    Inventor: Hwan Hee Jeong