Condenser Or Capacitor Patents (Class 427/79)
  • Patent number: 7281305
    Abstract: A method for attaching a capacitor to the feedthrough assembly of a medical device having a terminal pin comprises threading a first washer over the terminal pin, and placing a body of epoxy in contact with the first washer. The capacitor is positioned over the terminal pin such that the first washer and the body of epoxy are between the lower surface of the capacitor and a support surface. The body of epoxy is cured to couple the capacitor to the insulating structure. During curing, the body of epoxy is substantially confined between the upper surface and the lower surface by the ferrule, the insulating structure, the capacitor, and the first washer.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: October 16, 2007
    Assignee: Medtronic, Inc.
    Inventors: Rajesh V. Iyer, Susan A. Tettemer, John P Tardiff, Shawn D. Knowles
  • Patent number: 7275298
    Abstract: There is provided methods for producing an ultrasonic transducer assembly. The methods generally comprise the steps of creating a multi-layered rigid or flexible printed circuit board, having a top surface and bottom surface; creating a patterned conducting layer upon each of the top and bottom surface; creating at least one patterned backplate electrode on the board or as part of a discreet component which is then attached to the board; creating at least one conductive through-hole via integral with the board; roughening at least a portion of each of the at least one backplate to introduce gas pockets in that portion of a surface of the backplate; and attaching thin insulating or dielectric single or multi-layer film on a portion of the board in which the film has an integral conducting surface and in which the conducting surface is configured so as to form a capacitive structure with the at least one backplate.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: October 2, 2007
    Inventor: David W. Schindel
  • Patent number: 7237316
    Abstract: According to the present invention, a method for fabricating a three-dimensional acceleration sensor, comprising: providing a semiconductor substrate having first and second surfaces; forming an insulating layer on the first surface of the semiconductor substrate; forming an active layer on the insulating layer; forming a plurality of openings on the active layer at a first region, which is to be located above a movable mass with a predetermined space; selectively removing the insulating layer located under the first region in a wet-etching process through the plurality of openings; and selectively removing the active layer to form a groove separating the first region from a movable mass.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: July 3, 2007
    Assignee: Oki Electronics Industry Co., Ltd.
    Inventor: Akihiro Sakamoto
  • Patent number: 7226640
    Abstract: A method of forming an iridium-containing film on a substrate, from an iridium-containing precursor thereof which is decomposable to deposit iridium on the substrate, by decomposing the precursor and depositing iridium on the substrate in an oxidizing ambient environment which may for example contain an oxidizing gas such as oxygen, ozone, air, and nitrogen oxide. Useful precursors include Lewis base stabilized Ir(I)?-diketonates and Lewis base stabilized Ir(I) ?-ketoiminates. The iridium deposited on the substrate may then be etched for patterning an electrode, followed by depositing on the electrode a dielectric or ferroelectric material, for fabrication of thin film capacitor semiconductor devices such as DRAMs, FRAMs, hybrid systems, smart cards and communication systems.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: June 5, 2007
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Thomas H. Baum, Chongying Xu
  • Patent number: 7216417
    Abstract: Method for manufacturing an electromechanical sensor element for converting mechanical forces produced by the movements and vital functions or a person into electric signals, in which method a sensor film (11) is provided with metallic electrodes (15,16) placed on either side of it, at least one of said electrodes being a signal electrode, in which method is produced by cutting off a larger amount of sensor element material, in which method in the manufacture of sensor element material the electrodes are created in a continuous roll-to-roll process, and in which method the sensor element material is produced by laminating as a continuous roll-to-roll process. At least the sensor element material consists of repeated electrode patterns and a sensor element of a desired size and/or shape is formed by cutting the material between the patterns.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: May 15, 2007
    Assignee: Emfitech Oy
    Inventor: Heikki Raisanen
  • Patent number: 7201943
    Abstract: A thin film is formed using an atomic layer deposition process, by introducing a first reacting material including tantalum precursors and titanium precursors onto a substrate. A portion of the first reacting material is chemisorbed onto the substrate. Then, a second reacting material including oxygen is introduced onto the substrate. A portion of the second reacting material is also chemisorbed onto the substrate, to form an atomic layer of a solid material on the substrate. The solid material may be used as a dielectric layer of the capacitor and/or a gate dielectric layer of the transistor.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: April 10, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-Sung Park, Jeong-Hee Chung, Jae-Hyun Yeo
  • Patent number: 7168150
    Abstract: A method of making a resonant frequency tag which resonates at a predetermined frequency. The method involves providing a first conductive pattern having an inductive element and a first land and a second conductive pattern having a second land and a third land which are joined together by a link. The second conductive pattern is overlaid the first conductive pattern such that the second land is positioned over the first land. The third land is in electrical communication with the inductive element of the first conductive pattern. The formed resonant frequency tag is energized to determine if the tag resonates at the predetermined frequency. If the tag resonates properly, the third land is electrically coupled to the inductive element. If it does not, the second conductive pattern is adjusted so that overlapping portions of the first and second lands are changed, altering the capacitance to adjust the resonant tag frequency.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: January 30, 2007
    Assignee: Checkpoint Systems, Inc.
    Inventors: Eric Eckstein, Gary Mazoki, Peter Lendering, Luis Francisco Soler Bonnin, Takeshi Matsumoto, Lawrence Appalucci
  • Patent number: 7152291
    Abstract: Improved method steps for terminating multilayer electronic components are disclosed. Monolithic components are formed with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. Electrode and dielectric layers are provided in an interleaved arrangement and selected portions of the electrode layers are exposed. Electrically isolated anchor tabs may optionally be provided and exposed in some embodiments. Termination material is then plated to the exposed portions of the electrode layers until exposed portions of selected such portions thereof are connected. A variety of different plating techniques and termination materials may be employed in the formation of the subject self-determining plated terminations.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: December 26, 2006
    Assignee: AVX Corporation
    Inventors: Andrew P. Ritter, Robert Heistand, II, John L. Galvagni, Sriram Dattaguru
  • Patent number: 7144432
    Abstract: A method of making a capacitor element used for a solid electrolyte capacitor is provided. The method includes steps of forming a dielectric layer, a solid electrolyte layer of manganese dioxide, a graphite layer and a metal layer in this order on an anode chip of valve metal. The method further includes a step of forming an intermediate layer between the electrolyte layer and the graphite layer. The intermediate layer is made by application of manganese nitrate solution containing 0.5–2.0 wt % of graphite powder or by application of a graphite material containing manganese dioxide powder.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: December 5, 2006
    Assignee: Rohm Co., Ltd.
    Inventor: Takahiro Nakamura
  • Patent number: 7115302
    Abstract: A ceramic capacitor having a ceramic body and terminal electrodes, the ceramic body being substantially a rectangular parallelopiped in shape, the terminal electrodes being provided at the two ends of the ceramic body in the length direction, each terminal electrode being provided to cover one end face of the ceramic body in the length direction, part of the two surfaces in the width direction, and part of the two surfaces in the thickness direction, wherein, when the length of the ceramic body is L1 and the maximum lengths of the terminal electrodes at the two surfaces of the ceramic body in the width direction are L3 and L4, 0?|(L4?L3|/L1?0.0227 is satisfied. One surface among the two surfaces of the ceramic body in the width direction is the paste introduction side in the roller coating, while the other surface is the paste escape side in the roller coating.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: October 3, 2006
    Assignee: TDK Corporation
    Inventors: Hideki Yokoyama, Atsushi Takeda
  • Patent number: 7087535
    Abstract: A deposition method includes contacting a substrate with a first initiation precursor and forming a first portion of an initiation layer on the substrate. At least a part of the substrate is contacted with a second initiation precursor different from the first initiation precursor and a second portion of the initiation layer is formed on the substrate. The substrate may be simultaneously contacted with a plurality of initiation precursors, forming on the substrate and initiation layer comprising components derived from each of the plurality of initiation precursors. An initiation layer may be contacted with a deposition precursor, forming a deposition layer on the initiation layer. The deposition layer may be contacted with a second initiation precursor different from the first initiation precursor forming a second initiation layer over the substrate.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: August 8, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 7081141
    Abstract: An electrolytic capacitor comprising an anode, cathode and an electrolyte. The electrolyte comprises an aqueous solution comprising a compound of formula 1: CH3—(OCH2CH2)m—OCH3Formula 1 wherein m is an integer from 3 to 10. The electrolyte also comprises an ionogen.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: July 25, 2006
    Assignee: Medtronic, Inc.
    Inventors: Joachim Hossick-Schott, Brian John Melody, John Tony Kinard
  • Patent number: 7067172
    Abstract: Improved terminations, interconnection techniques, and inductive element features for multilayer electronic components are formed in accordance with disclosed plating techniques. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such plated termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed varying width internal electrode tabs and additional anchor tab portions. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. The combination of electrode tabs and anchor tabs may be exposed in respective arrangements to form generally discoidal portions of plated material.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: June 27, 2006
    Assignee: AVX Corporation
    Inventors: Andrew P. Ritter, John L. Galvagni, Jason MacNeal, Robert Heistand, II, Sriram Dattaguru
  • Patent number: 7067173
    Abstract: Provided is a Ag-based conductive paste for a terminal electrode which suppresses oxidation of the Ni surface of an internal conductor and therefore brings about excellent joining with Ni even when baking is performed in the atmosphere in the case where Ni is used as the internal conductor of a laminated ceramic electronic component. The conductive paste includes at least one of an Ag powder and an Ag alloy powder, a nickel boride powder, an inorganic binder and an organic vehicle, wherein the quantity of the nickel boride powder is within the range of about 5% by weight or more, but less than about 60% by weight of the total paste.
    Type: Grant
    Filed: May 19, 2004
    Date of Patent: June 27, 2006
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Takeshi Miki, Satoru Noda
  • Patent number: 7056357
    Abstract: A method for making a solid electrolytic capacitor including a flat porous body is provided. This method utilizes a mold which includes a horizontal surface and four vertical side surfaces. The horizontal surface and the side surfaces define a cavity into which powder made of valve metal is loaded. By compacting the powder in the cavity, a flat porous body having a predetermined thickness is formed. In the compacting, the powder is compressed vertically with the four side surfaces fixed in position.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: June 6, 2006
    Assignee: Rohm Co., Ltd
    Inventor: Chojiro Kuriyama
  • Patent number: 7011726
    Abstract: A method of fabricating a thin dielectric film, a thin dielectric film formed according to the method, and a system including the thin dielectric film. The method includes: depositing a ceramic precursor material on a metal sheet, the ceramic precursor material including a mixture comprising ceramic particles and an organic carrier medium; heat treating the ceramic precursor material such that the organic carrier medium is substantially burnt off, and further such that a dielectric layer is formed including ceramic grains formed from the ceramic particles, and having grain sizes between about 100 nm and about 500 nm; depositing a CSD precursor material onto the dielectric layer; and heat treating the CSD precursor material such that organics in the CSD precursor material are substantially burnt off, and further such that a CSD medium is formed from the CSD precursor material including CSD grains substantially filling the voids between the ceramic grains.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: March 14, 2006
    Assignee: Intel Corporation
    Inventor: Cengiz A. Palanduz
  • Patent number: 7008669
    Abstract: A method of manufacturing a ceramic includes forming a film which includes a complex oxide material having an oxygen octahedral structure and a paraelectric material having a catalytic effect for the complex oxide material in a mixed state, and performing a heat treatment to the film, wherein the paraelectric material is one of a layered catalytic substance which includes Si in the constituent elements and a layered catalytic substance which includes Si and Ge in the constituent elements. The heat treatment includes sintering and post-annealing. At least the post-annealing is performed in a pressurized atmosphere including at least one of oxygen and ozone. A ceramic is a complex oxide having an oxygen octahedral structure, and has Si and Ge in the oxygen octahedral structure.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: March 7, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Eiji Natori, Takeshi Kijima, Koichi Furuyama, Yuzo Tasaki
  • Patent number: 7004994
    Abstract: Provided are silver-containing powders and a method and apparatus for manufacturing the silver-containing particles of high quality, of a small size and narrow size distribution. An aerosol is generated from liquid feed and sent to a furnace, where liquid in droplets in the aerosol is vaporized to permit formation of the desired particles, which are then collected in a particle collector. The aerosol generation involves preparation of a high quality aerosol, with a narrow droplet size distribution, with close control over droplet size and with a high droplet loading suitable for commercial applications.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: February 28, 2006
    Assignee: Cabot Corporation
    Inventors: Mark J. Hampden-Smith, Toivo T. Kodas, Quint H. Powell, Daniel J. Skamser, James Caruso, Clive D. Chandler
  • Patent number: 7004983
    Abstract: The polymer electrolyte composite, for driving an electrolytic capacitor, according to the present invention is a composite body comprising an electrolyte and an acrylic polymer containing a copolymer of acrylic derivative. The electrolyte comprises a polar solvent and a solute comprising at least one of inorganic acids, organic acids and salts of such acids. The copolymer of acrylic derivative is a polymer of: a first monomer of at least one of a group of monofunctional monomers of acrylic derivatives each having at least one hydroxyl group at a terminal thereof and a polymerizable unsaturated double bond; and a second monomer of at least one of a group of multifunctional monomers of acrylic derivatives each having plural polymerizable unsaturated double bonds.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: February 28, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazumitsu Honda, Nario Niibo, Yuichiro Tsubaki, Junji Ozaki
  • Patent number: 6996891
    Abstract: The invention relates to a method for the manufacture of a sensor element and to a sensor element. In the method, both surfaces of a sensor film are provided with metallic electrodes. The sensor element is produced by cutting it from a larger amount of sensor element material. In the manufacture of the sensor element material, the electrodes are produced as a continuous process from roll to roll and the sensor element material is formed by laminating as a continuous process from roll to roll. At least the signal electrode consists of repeated electrode patterns which are at least partially connected to each other via one or more narrow connecting strips, and a sensor element of a desired length and/or shape is produced by cutting the material across the region of the connecting strips.
    Type: Grant
    Filed: July 3, 2000
    Date of Patent: February 14, 2006
    Assignee: Emfitech Oy
    Inventor: Heikki Räisänen
  • Patent number: 6973706
    Abstract: A process for the manufacture of small sensors with reproducible surfaces, including electrochemical sensors. One process includes fanning channels in the surface of a substrate and disposing a conductive material in the channels to form an electrode. The conductive material can also be formed on the substrate by other impact and non-impact methods. In a preferred embodiment, the method includes cutting the substrate to form a sensor having a connector portion and a transcutaneous portion, the two portions having edges that define one continuous straight line.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: December 13, 2005
    Assignee: TheraSense, Inc.
    Inventors: James Say, Michael F. Tomasco, Adam Heller, Yoram Gal, Behrad Aria, Ephraim Heller, Phillip John Plante, Mark S. Vreeke
  • Patent number: 6962612
    Abstract: A electrolytic capacitor includes (a) a capacitor element having a positive electrode, a negative electrode, and a solid organic conductive material disposed between the positive electrode and the negative electrode, (b) an electrolyte, (c) a case for accommodating the capacitor element and the electrolyte, and (d) a sealing member disposed to cover the opening of the case. The solid organic conductive material has at least one of organic semiconductor and conductive polymer. In this constitution, an electrolytic capacitor having excellent impedance characteristic, small current leak, excellent reliability, and high dielectric strength is obtained.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: November 8, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuyo Saito, Yukihiro Nitta, Hiroshi Tada, Shigeyoshi Iwamoto
  • Patent number: 6960365
    Abstract: A method of manufacturing a vertical metal-insulator-metal capacitor (MIMCap) (10) in regions (19) of an insulating layer (14). Trenches for both conductive lines and vertical MIMCap's are formed in the insulating layer (14), and regions (19) are covered by resist (20) while the conductive lines (24) are deposited on the wafer. The resist (20) is removed, and the MIMCap dielectric and top plate conductive material (28) is deposited, forming a vertical MIMCap in regions (19).
    Type: Grant
    Filed: January 25, 2002
    Date of Patent: November 1, 2005
    Assignee: Infineon Technologies AG
    Inventor: Xian J. Ning
  • Patent number: 6960366
    Abstract: Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on one or both of top and bottom surfaces of a monolithic structure can facilitate the formation of selective wrap-around plated terminations.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: November 1, 2005
    Assignee: AVX Corporation
    Inventors: Andrew P. Ritter, Robert Heistand, II, John L. Galvagni, Sriram Dattaguru
  • Patent number: 6936301
    Abstract: Oxygen partial pressure may be controlled during annealing of a perovskite dielectric layer by providing an oxygen-absorbing layer adjacent the perovskite dielectric layer, and annealing the perovskite dielectric layer in an ambient that includes an ambient oxygen partial pressure, such that the oxygen-absorbing layer locally reduces the oxygen partial pressure adjacent the perovskite dielectric layer to below the ambient oxygen partial pressure. Thus, a perovskite dielectric layer can be annealed without the need to provide ultra-high vacuum and/or ultra-high purity ambient environments.
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: August 30, 2005
    Assignee: North Carolina State University
    Inventors: Jon-Paul Maria, Angus Ian Kingon
  • Patent number: 6925701
    Abstract: A method of making a resonant frequency tag which resonates at a predetermined frequency. The method involves providing a first conductive pattern having an inductive element and a first land and a second conductive pattern having a second land and a third land which are joined together by a link. The second conductive pattern is overlaid the first conductive pattern such that the second land is positioned over the first land. The third land is in electrical communication with the inductive element of the first conductive pattern. The formed resonant frequency tag is energized to determine if the tag resonates at the predetermined frequency. If the tag resonates properly, the third land is electrically coupled to the inductive element. If it does not, the second conductive pattern is adjusted so that overlapping portions of the first and second lands are changed, altering the capacitance to adjust the resonant tag frequency.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: August 9, 2005
    Assignee: Checkpoint Systems, Inc.
    Inventors: Eric Eckstein, Gary Mazoki, Peter Lendering, Luis Francisco Soler Bonnin, Takeshi Matsumoto, Lawrence Appalucci
  • Patent number: 6908639
    Abstract: An interface forming method includes forming a first layer containing a first chemical element and chemisorbing on the first layer an interface layer containing at least one monolayer of the first chemical element intermixed with a second chemical element different from the first chemical element. A second layer comprising the second chemical element can be formed on the interface layer. The first layer might not substantially contain the second chemical element, the second layer might not substantially contain the first chemical element, or both. An apparatus can include a first layer containing a first chemical element, an interface layer chemisorbed on the first layer, and a second layer containing a second element on the interface layer. The interface layer can contain at least one monolayer of the first chemical element intermixed with a second chemical element different from the first chemical element.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: June 21, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Gurtej S. Sandhu
  • Patent number: 6899919
    Abstract: A high surface area electrode is made by retaining an electrode blank with one surface thereof horizontal and facing upward. The surface is then submerged in a liquid having particles of conductive material suspended therein. The particles in suspension are then allowed to precipitate out and onto the surface of the electrode. This process is repeated until a porous layer of particles of the desired thickness has formed on the surface. As a final step the particles are bonded to the surface using an appropriate bonding method such as a heat treatment.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: May 31, 2005
    Inventor: Jack Chen
  • Patent number: 6857172
    Abstract: According to the present invention, a method of manufacturing a ferroelectric capacitor using a ferroelectric thin film, includes steps of: forming a lower conductive layer on a semiconductor substrate; coating solution of ferroelectric coking including organic solvent and organometallic complex on the lower conductive layer; performing a heating process for coated solution at temperature, to decompose said organometallic complex in solution of ferroelectric coking, or more and ferroelectric crystallization temperature or below to form said metal compound thin film; forming an upper conductive layer on said metal compound thin film; and performing a heating process for said metal compound thin film at ferroelectric crystallization temperature or more to form said ferroelectric thin film.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: February 22, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Daisuke Inomata
  • Patent number: 6849292
    Abstract: The present invention concerns the field of solid state capacitors and relates particularly to massed production methods for manufacturing solid state capacitors.
    Type: Grant
    Filed: August 9, 2000
    Date of Patent: February 1, 2005
    Assignee: AVX Limited
    Inventor: David Huntington
  • Patent number: 6845551
    Abstract: There is disclosed herein a high voltage and high temperature power electronics capacitor which comprises one or more insulator layers of mica paper, and one or more metal conductor layers, all dispersed in a pressurized environment of a nonreactive and high voltage strength gas maintained at near ambient to about 405.2 kPa of pressure. The insulator and conductor layers are isolated and separated from one another by the alternating placement of conductor layers between said insulator layers. These capacitors are readily packaged for commercial use in containers or housings of almost any geometric form and any material of construction. Moreover, low inductance ceramic bushings can be employed on these containers for establishing external electrical contacts. These capacitors can be economically manufactured and used in large commercial volumes with currently available materials and production methods.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: January 25, 2005
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Lyon Mandelcorn, John Bowers, Eugene R. Danielson, Stephen R. Gurkovich, Kenneth C. Radford
  • Patent number: 6842965
    Abstract: A strain detector where water does not reach a strain-resistance element and which supplies stable output at all times is provided. In the strain detector, a first protective layer made of glass is disposed to cover an insulating substrate and the strain-resistance element. A second protective layer made of resins or glass for covering the first protective layer, and a thermistor for compensating the resistance of the strain-resistance element are disposed.
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: January 18, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshirou Otobe, Takashi Kawai, Yukio Mizukami
  • Patent number: 6843810
    Abstract: An electric double layer capacitor is disclosed which is capable of preventing transmission of an electrolytic solution vaporized in a basic cell through current collectors and capable of improving a yield. A method for preparing the electric double layer capacitor is also disclosed.
    Type: Grant
    Filed: January 2, 2004
    Date of Patent: January 18, 2005
    Assignee: NEC Tokin Corporation
    Inventors: Yutaka Nakazawa, Ryuichi Kasahara, Koji Sakata
  • Patent number: 6841191
    Abstract: A fabricating method and apparatus of an zinc phosphate coating for a varistor has a insulation formed on a surface of a body which does not include two opposite ends of the body formed two outer terminals. The insulation has anti-etch feature for the electrolyte, so that the exposed surface of the body prevents to be etched and to be electroplated a metal material on it. Therefore the varistor has a great fabricating yield and the great shape after electroplating the two outer terminals step.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: January 11, 2005
    Assignee: Thinking Electronic Industrial Co., Ltd.
    Inventor: Chien-Liang Wu
  • Patent number: 6832420
    Abstract: An electronic device has a plurality of capacitors in an ultra-small integrated package. The device has a plurality of terminal structures on one terminal side of the package to permit inverted mounting to a printed circuit board. The terminals are widely spaced, with the individual capacitors being located entirely in between. The device is produced on a suitable substrate using thin film manufacturing techniques. A lead-based dielectric having a high dielectric constant is preferably utilized for each capacitor to provide a relatively high-capacitance value in a relatively small plate area.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: December 21, 2004
    Assignee: AVX Corporation
    Inventor: Donghang Liu
  • Patent number: 6824814
    Abstract: A method of forming a perovskite thin film includes preparing a perovskite precursor solution; preparing a silicon substrate for deposition of a perovskite thin film, including forming a bottom electrode on the substrate; securing the substrate in a spin-coating apparatus and spinning the substrate at a predetermined spin rate; injecting a perovskite precursor solution into the spin-coating apparatus thereby coating the substrate with the perovskite precursor solution to form a coated substrate; baking the coated substrate at temperatures which increase incrementally from about 90° C. to 300° C.; and annealing the coated substrate at a temperature of between about 500° C. to 800° C. for between five minutes to fifteen minutes.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: November 30, 2004
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Wei-Wei Zhuang, Sheng Teng Hsu, Wei Pan, Masayuki Tajiri
  • Patent number: 6824603
    Abstract: A composition of matter comprising a mixture of an oxide powder or powders and a Reactive Organic Medium (ROM) which can be used to create electronic components on a suitable. The materials are applied to conventional polymer-based circuit substrates by any convenient printing process and thermally cured to well-consolidated oxide components at a temperature, which the substrate can withstand. Mixtures for various components, including resistors, capacitor dielectrics and magnetic cores and processes to apply them are disclosed.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: November 30, 2004
    Assignee: Parelec, Inc.
    Inventor: Paul H. Kydd
  • Patent number: 6817086
    Abstract: A bilayer mask employed for lift off has a top strip which bridges between first and second bilayer portions and is completely undercut so that when one or more materials is sputter deposited the materials do not form fences abutting recessed edges of a bottom layer in undercuts below a top layer. Sacrificial protective layers are formed on a sensor and lead layers for protecting these components while overlapping portions of these materials on the top of the sensor formed during deposition can be removed by ion beam sputtering, after which the sacrificial protective layers can be removed by ion milling or reactive ion etching.
    Type: Grant
    Filed: August 12, 2002
    Date of Patent: November 16, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jennifer Qing Lu, Scott Arthur MacDonald, Hugo Alberto Emilio Santini
  • Publication number: 20040213901
    Abstract: Provided is a Ag-based conductive paste for a terminal electrode which suppresses oxidation of the Ni surface of an internal conductor and therefore brings about excellent joining with Ni even when baking is performed in the atmosphere in the case where Ni is used as the internal conductor of a laminated ceramic electronic component. The conductive paste includes at least one of an Ag powder and an Ag alloy powder, a nickel boride powder, an inorganic binder and an organic vehicle, wherein the quantity of the nickel boride powder is within the range of about 5% by weight or more, but less than about 60% by weight of the total paste.
    Type: Application
    Filed: May 19, 2004
    Publication date: October 28, 2004
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Takeshi Miki, Satoru Noda
  • Patent number: 6794098
    Abstract: A capacitor is formed utilizing a plasma deposited capacitor dielectric wherein the plasma deposition is a two-component reaction comprising a silicon donor, which is non-carbon containing and non-oxygenated, and an organic precursor, which is non-silicon containing and non-oxygenated. The plasma deposition produces a capacitor dielectric that can exhibit a low dielectric constant and, in selected depositions, a response to photo-oxidation induced by exposure to radiated electromagnetic energy in the presence of oxygen. Photo-oxidation of selected depositions can be used to alter the dielectric constant of the capacitor dielectric after the capacitor has been fabricated. The capacitor may be used in precision filter applications.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: September 21, 2004
    Inventor: Ronald M. Kubacki
  • Publication number: 20040175561
    Abstract: The present invention relates generally to an electrical charge storage device (ECSD) with enhanced power characteristics. More particularly, the present invention relates to enhancing the current density, voltage rating, power transfer characteristics, frequency response and charge storage density of various devices, such as capacitors, batteries, fuel cells and other electrical charge storage devices. For example, one aspect of the present invention is solid state and electrolytic capacitors where the conductor surface area is increased with smooth structures, thereby reducing the distance separating the conductors, and improving the effective dielectric characteristics by employing construction techniques on atomic, molecular, and macroscopic levels.
    Type: Application
    Filed: March 4, 2004
    Publication date: September 9, 2004
    Inventor: William B. Duff
  • Publication number: 20040146655
    Abstract: A method is taught for fabricating patterned silicon dioxide layers on process areas disposed perpendicularly or at an inclination to a substrate surface. Firstly, a starter layer having leaving groups is produced by non-conformal deposition of a reactive component. Tris(tert-butoxy)silanol is subsequently added. The addition of the tris(tert-butoxy)silanol leads to the formation of a silicon dioxide layer selectively only on the starter layer.
    Type: Application
    Filed: October 21, 2003
    Publication date: July 29, 2004
    Inventors: Harald Seidl, Martin Gutsche
  • Publication number: 20040131762
    Abstract: A method for manufacturing a capacitor on a single-crystal silicon substrate, comprising the steps of:
    Type: Application
    Filed: December 18, 2003
    Publication date: July 8, 2004
    Inventors: Philippe Vigie, Guillaume Guegan
  • Publication number: 20040131763
    Abstract: In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b) flowing an oxidizing gas into the reaction chamber; c) flowing a platinum precursor into the reaction chamber and depositing platinum from the platinum precursor over the substrate in the presence of the oxidizing gas; and d) maintaining a temperature within the reaction chamber at from about 0° C. to less than 300° C. during the depositing. In another aspect, the invention includes a platinum-containing material, comprising: a) a substrate; and b) a roughened platinum layer over the substrate, the roughened platinum layer having a continuous surface characterized by columnar pedestals having heights greater than or equal to about one-third of a total thickness of the platinum layer.
    Type: Application
    Filed: December 17, 2003
    Publication date: July 8, 2004
    Inventor: Eugene P. Marsh
  • Publication number: 20040126484
    Abstract: Thin film ceramic foil capacitors are mass-produced using inline reel-to-reel processing techniques by starting (100) with a length of copper foil which serves as one plate of the capacitor, then depositing (120) a layer of a ceramic precursor on a portion of one side of the copper foil at a first station. The foil is advanced (117, 127, 137, 147) to the next station where the ceramic precursor and the copper foil are heated (130) to remove any carrier solvents or vehicles, then pyrolyzed (140) to remove any residual organic materials. It is then sintered (150) at high temperatures to convert the ceramic to polycrystalline ceramic. A final top metal layer is then deposited (160) on the polycrystalline ceramic to form the other plate of the capacitor.
    Type: Application
    Filed: December 30, 2002
    Publication date: July 1, 2004
    Inventors: Robert Croswell, Jovica Savic, Aroon Tungare, Taeyun Kim, Angus Ian Kingon, Jon-Paul Maria
  • Patent number: 6749890
    Abstract: The invention provides an electrode forming method with steps of arraying chip-style electronic components on an arraying flat bed thereby positioning and aligning the components, lowering a film coated with an adhesive in relative manner together with an adhering top plate parallel to the arraying flat bed thereby adhering ends of the positioned and aligned chip-style electronic components to the adhesive, then lowering the first film to which the chip-style electronic components are adhered in relative manner together with a coating top plate parallel to a coating flat bed provided with a conductive paste layer of a constant thickness thereby pressing the other ends of the chip-style electronic components to the coating flat bed and coating the ends of the electronic components with the conductive paste.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: June 15, 2004
    Assignee: TDK Corporation
    Inventors: Ko Onodera, Satoshi Kurimoto
  • Publication number: 20040110357
    Abstract: A method for manufacturing a multilayer ceramic capacitor includes the steps of forming a ceramic slurry, forming ceramic green sheets from the ceramic slurry, printing internal electrode patterns on the ceramic green sheets, generating a laminated body by stacking the ceramic green sheets provided with the internal electrode patterns printed thereon, dicing the laminated body to thereby form chip-shaped ceramic bodies and sintering the chip-shaped ceramic bodies. The ceramic slurry includes a glass component containing one or more additive elements selected from the group consisting of Mn, V, Cr, Mo, Fe, Ni, Cu and Co.
    Type: Application
    Filed: November 6, 2003
    Publication date: June 10, 2004
    Inventors: Hirokazu Chazono, Hisamitsu Shizuno, Hiroshi Kishi
  • Patent number: 6740351
    Abstract: For manufacturing a multi-layer structure with repeating layer sequences, a band-shaped carrier material is first partially separated into individual sections of a same size with connections capable of bearing remaining between the individual sections. After continuously applying at least one further material layer on the surface of the carrier material, the individual sections are completely separated by cutting or punching. The multi-layer structure is obtained by stacking the individual sections obtained in this way on top of one another, whereby intermediate layers can also be potentially inserted between two individual sections.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: May 25, 2004
    Assignee: Epcos AG
    Inventors: Klaus Schoch, Werner Erhardt, Hartmut Michel
  • Publication number: 20040081811
    Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).
    Type: Application
    Filed: October 15, 2003
    Publication date: April 29, 2004
    Inventors: Michael D. Casper, William B. Mraz
  • Publication number: 20040071879
    Abstract: A method of fabricating aluminum oxide films utilizing aluminum alkoxide precursors is described. The aluminum oxide film is formed by (a) providing an aluminum alkoxide precursor that is dissolved, emulsified or suspended in a liquid; (b) providing a vapor generated from the aluminum alkoxide precursor; and (c) depositing an aluminum oxide film on the substrate at a temperature greater than 500° C.
    Type: Application
    Filed: September 30, 2003
    Publication date: April 15, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alessandro C. Callegari, Deborah Ann Neumayer