Abstract: A semiconductor chip (3) to be positioned with a front face thereof downward for formation of a chip-on-chip structure has electrode marks (35) provided on a back face (34) thereof. The electrode marks (35) are respectively provided in association with a plurality of electrodes (33) provided on the front face (31) of the semiconductor chip in the same arrangement as the arrangement of the electrodes (33). The arrangement of the electrode marks (35) represents the arrangement of the electrodes (33) on the front face (31) when viewed from the side of the back face (34) of the semiconductor chip 3. Therefore, the semiconductor chip (3) can easily be positioned with the front face downward on the basis of the electrode marks (35).

Abstract: This is a semiconductor device made by using a film carrier tape and method of making the same, wherein the package size is close to the chip size and connection portions for electrodes of a semiconductor chip are not exposed. Electroplating is performed in a state where connection leads 24, plating leads 26 and plating electrodes 28 are all conductive, the connection leads being are formed within a region to be filled with a molding material 36 and being connected to electrodes 42 of a semiconductor chip 40 and pad portions 22, the plating leads 26 being connected to the connection leads 24, and plating electrodes 28 being connected to the plating leads 26. The connection portions 29 are punched out into the region to be filled with the molding material, the connection leads 24 and the electrodes 42 are connected, and the molding material 36 is poured in. The end surfaces of the connection leads 24 that are exposed from the holes 32 are also covered by the molding material 36 so as not to be exposed.

Abstract: A plurality of lead frames is supplied in lead frame by lead frame sequence. A curable adhesive, preferably a 505 Epoxy, is applied to one surface of each lead frame as it indexes through an application device. An attaching device attaches a device to each lead frame with the adhesive by holding the device in place to cure for a preselected period of time of about one second. Later, the lead frames have their edges trimmed and then are separated into separate lead frames.

Abstract: A method for fabricating semiconductor packages provides a leadframe for packages that are to be singulated with respective predetermined package body sizes. Individual mold caps are formed on the leadframe with mold cap dimensions that are larger than the respective predetermined package body sizes. The mold caps and leadframe are sawed to singulate packages therefrom. The sawing reduces the dimensions of the mold caps to the respective predetermined package body sizes.

Abstract: A conductive plastic lead frame and method of manufacturing the same, suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment, the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Abstract: A leadframe (20) for a semiconductor device includes a paddle ring (22) having an inner perimeter (24), an outer perimeter (26), and a cavity (28) located within the inner perimeter (24) for receiving an integrated circuit die (30). A first row of terminals (32) surrounds the outer perimeter (26) and a second row of terminals (34) surrounds the first row of terminals (32). Each of the terminals of the first row of terminals (32) is individually connected to the paddle ring (22) and each of the terminals of the second row of terminals (34) is connected to one side of a connection bar (78, 79), which is connected to one of the terminals of the first row (32) or to the paddle ring (22).

Abstract: A semiconductor device having a plurality of semiconductor chips respectively joined to predetermined positions on a surface of a solid, and a frame holding the plurality of semiconductor chips in a relative positional relationship corresponding to joint positions on the surface of the solid. The solid may be another semiconductor chip or a wiring board. The plurality of semiconductor chips may be bonded to a surface, opposite to the surface, of the solid, of the frame. The plurality of semiconductor chips may be respectively fitted in through holes formed in the frame.

Abstract: A semiconductor package includes a semiconductor die having a circuit side and a back side, a multi layered leadframe attached to the die, a dense array of terminal contacts in electrical communication with the die, and a plastic body encapsulating the die and the leadframe. The leadframe includes circuit side leads attached to the circuit side of the die, and back side leads located proximate to the back side of the die. Both the circuit side leads and the back side leads are wire bonded to bond pads on the die. In addition, the back side leads provide electrical paths between the bond pads and selected terminal contacts that would otherwise be inaccessible due to line/space design rules. A method for fabricating the package includes the steps of: attaching the die to the circuit side leads, attaching the back side leads to the circuit side leads, wire bonding the die to the leads, encapsulating the die, and then forming the terminal contacts.

Abstract: A method for forming a direct chip attach (DCA) device (1) includes attaching a chip (3) to a lead frame (2). Conductive studs (22) are attached to bonding pads (13) on the chip (3) and a flag (18) on lead frame (2). The chip (3) and flag (18) are enclosed with an encapsulating layer (4), and openings (6) are formed in an upper surface (7) to expose conductive studs (22). In one embodiment, a masking layer (51) is applied to the lead frame (2), and the structure is then placed in an electroless plating apparatus (61). While in the plating apparatus (61), an injection device (66) injects plating solution (71) towards the upper surface (7) and openings (6) to enhance the formation of barrier layers (24) on the conductive studs (22). Solder bumps (9) are then attached to barrier layers (24) through the openings (6).

Abstract: A lead frame includes: an outer frame section; a plurality of chip mounting sections which are supported by the outer frame section and on which a plurality of semiconductor chips are mounted; lead sections surrounding the chip mounting sections; connecting sections for connecting and supporting the lead sections and the outer frame section with each other; and an encapsulation region in which the chip mounting sections are encapsulated together in an encapsulation resin. An opening is provided in a plurality of regions of the outer frame section that are each located outside the encapsulation region and along the extension of one of the connecting sections.

Abstract: The invention relates to a method for improving the mechanical properties of BOC module arrangements in which chips have 3D structures, solder balls, &mgr; springs or soft bumps which are mechanically and electrically connected by means of solder connections to terminal contacts on a printed circuit board or leadframe. Advantages are achieved by providing a casting compound for the wafer or the chips after they have been individually separated and before they are mounted on the printed circuit board in such a way that the tips of the 3D structures protrude from this compound. The casting compound preferably has elastic and mechanical properties comparable to those of silicon.

Abstract: Two different switches with two different signal input schemes are fabricated by mounting the same semiconductor chip on the same lead pattern. Two of the leads of the lead pattern provides space enough for wire-bonding connection to corresponding electrode pads on the semiconductor chip at both ends of the semiconductor chip. Because each of electrode pads can be connected to the corresponding lead at either end of the semiconductor chip, two sets of bonding wire connection between the leads and the electrode pads provides two different switches with two different signal inputs scheme.

Abstract: A semiconductor including a leadframe having a die attach paddle and a number of leads is provided. The die attach paddle has a recess to provide a number of mold dams around the periphery of the die attach paddle. An integrated circuit is positioned in the recess. Electrical connections between the integrated circuit and the number of leads are made, and an encapsulant is formed over the integrated circuit and around the number of mold dams.

Abstract: A method of fabricating a semiconductor package includes: forming a circuit pattern on a frame; attaching a semiconductor chip onto the circuit pattern; connecting the semiconductor chip and the circuit pattern electrically; forming a molding wrapping the semiconductor chip and the circuit pattern; removing the frame; forming a photoresist film having a through hole on the circuit pattern, the through hole exposing a portion of the circuit pattern; and forming a solder ball on the photoresist film, the solder ball being connected to the portion of the circuit pattern through the through hole.

Abstract: A transfer molding apparatus, wherein said top-half mold and said bottom-half mold form a plurality of cavities interconnected, and wherein said pressure adjusting means reduces the pressure of the cavities every time a specified amount of resin is supplied into any one of a plurality of cavities.

Abstract: A method for applying a viscous material to a lead frame element. A method of the invention includes positioning the lead frame facing downward and bringing the lead fingers into contact with a pool of adhesive material. The contact of the lead fingers to the adhesive material results in a portion of the lead fingers receiving a portion of the adhesive material from the pool of adhesive material. The gravitational forces on the adhesive material on the downward facing lead frame maintain the shape and boundary definition of the adhesive material.

Abstract: A semiconductor package and a fabricating method thereof are proposed. The semiconductor package includes a semiconductor chip; a plurality of leads surrounding the chip and formed with a plurality of connecting mechanisms and strengthening structures; and an encapsulant for encapsulating the chip and the leads. The foregoing semiconductor package eliminates the use of a die pad, allowing the thickness of the package to be reduced and a surface of the chip to be exposed to the outside of the encapsulant for improving the heat dissipating efficiency thereof. The leads have the same height as the semiconductor package, allowing upper and lower surfaces of the leads to be exposed to the outside of the encapsulant, which further enhance the dissipation of heat generated by the chip in operation.

Abstract: A dual gauge lead frame 36 is provided, including at least one mating surface 14 and a plurality of terminal arms 16 formed into a flat circuit surface 12 having a first gauge 32. Each of the plurality of terminal arms 16 includes a fold over terminal arm portion 28 folded over and coined into a base terminal arm portion 26 to form a plurality of end posts 30. The plurality of end posts 30 form a second gauge 34.

Abstract: A semiconductor device includes: a semiconductor element 2 bonded on a first metallic layer; a wire 4 for electrically connecting an electrode pad of the semiconductor element to a second metallic layer; and a resin package 7 for sealing said semiconductor element. Rear surfaces of the first metallic layer 8a and the second metallic layer 8b are flush with a bottom of said resin package.

Abstract: A natural-resource-conservative, environmentally-friendly, cost-effective, leadless semiconductor packaging apparatus, having superior mechanical and electrical properties, and having an optional windowed housing which uniquely seals and provides a mechanism for viewing the internally packaged integrated semiconductor circuits (chips/die). A uniquely stamped and/or bent lead-frame is packaged by a polymeric material during a unique compression-molding process using a mold, specially contoured to avoid the common “over-packaging” problem in related art techniques. The specially contoured mold facilitates delineation of the internal portions from the external portions of the lead-frame, as the external portions are the effective solderable areas that contact pads on a printed circuit board, thereby avoiding a laborious environmentally-unfriendly masking step and de-flashing step, streamlining the device packaging process.

Abstract: Methods of fabricating leadless packages are described that facilitate increased contact density. Each device area in a lead frame panel has a die attach pad and a multiplicity of conductive contacts. The contacts are carried by tie bars and the die attach pad is carried by support bars that extend from the contacts. During assembly, the lead frame panel is held in position while the die attach pad support bars are severed. Once the die attach pad support bars are severed, an adhesive tape is adhered to the bottom surface of the lead frame panel so that the die attach pad may be held in position relative to its associated contacts. After the adhesive tape has been applied, the leadless packages may be assembled in a conventional manner.

Abstract: A method for forming semiconductor device packages that include one or more semiconductor dice, leads in communication with bond pads of each die, and a protective layer, or package, over at least portions of the active surface of each die, and includes electrically exposing the leads through the protective layer so as to facilitate connection thereof to external circuitry. For example, external conductive structures may be secured to the leads through openings in the package. The package may also include protective layers over the back sides or the edges of each semiconductor die. The completed CSP device is precisely encapsulated with minimal lateral dimensions, and has an array of precisely positioned external connectors. A stereolithographic process is used for precisely forming the protective layers of the package. A machine vision system may be used in connection with stereolithographic equipment to locate individual dice, features thereof, or leads.

Abstract: A process for continuous manufacture of electronic modules (6) including the steps of providing a microcircuit and antenna receiving side on a continuous strip (8) and module surface areas; arranging, e.g., by printing, on the module surface area, a plane spiral antenna (2) wholly arranged to this area; fixing on said strip (8) a microcircuit (7) provided with contact pads (13, 14) after placing an insulator between the microcircuit the strip (8); making an electric connection between the antenna (2) and of the microcircuit.

Abstract: A method of manufacturing an integrated circuit package such as a BGA package for use with an integrated circuit chip. The integrated circuit package has a substrate formed with a cavity that exposes a lower conductive level in the package so that connections between the integrated circuit chip and the lower conductive level may be formed to reduce the through holes formed in the substrate. As a result, additional signal line interconnections may be included in the substrate circuit package and/or the size of the integrated circuit chip may be decreased. Each of these may be implemented for enhanced electrical performance. The multiple wire bonding tiers in the substrate may also provide greater wire separation that eases wire bonding and subsequent encapsulation processes.

Abstract: In a packaged integrated circuit, electrostatic discharge protection is provided by portions of a lead frame on which the integrated circuit is mounted. The lead frame includes a die paddle on which an integrated circuit die is mounted, with plastic or epoxy material encapsulating exposed surfaces of the integrated circuit die except for a sensing surface, and supporting pins or leads formed from the lead frame. Portions of the lead frame extending from the die paddle are folded around sides of the encapsulated integrated circuit die and over, or adjacent to and level with, a peripheral upper surface of the encapsulated integrated circuit die to form an electrostatic discharge ring. The lead frame portions folded around the integrated circuit package are connected to ground through a ground pin, so that charge on a human finger touching the electrostatic discharge ring is dissipated to ground before the finger contacts a sensing surface of the integrated circuit.

Abstract: Provide a discrete semiconductor device, particularly a discrete semiconductor device for small signal operation with a smaller packaging area and has excellent high frequency characteristics and good heat dissipation performance, and a method for producing the same. The discrete semiconductor elements are mounted on die bond pads and wire bond pads with the packaging surface being sealed with a resin, and connecting the back faces of the die bond pads and the wire bond pads directly to a mother board.

Abstract: A semiconductor package including a double-faced semiconductor chip having integrated circuitry on both sides thereof, and a method of fabricating the same is provided, wherein the semiconductor package includes the semiconductor chip; a lead-on-chip (LOC)-type substrate, having metal patterns on both sides, bonded with the first side of the semiconductor chip; first wires for connecting the first side of the semiconductor chip to the second side of the LOC-type substrate; second wires for connecting the second side of the semiconductor chip to the first side of the LOC-type substrate; a first sealing material for covering the semiconductor chip, the first wires, and the second side of the LOC-type substrate; a second sealing material for covering the semiconductor chip, the second wires, and the first side of the LOC-type substrate; and solder balls attached to the second side of the LOC-type substrate.

Abstract: A leadframe is plated with palladium only to a surface of a metal plate on which semiconductors elements are to be mounted and a surface of the metal plate to be placed on a substrate, and is not plated with palladium to lead portions, pad portions, other portions except for the surfaces to be plated and the side surface, of the leadframe, thereby, the amount of use of palladium is reduced to minimum and a cheap leadframe can be provided.

Abstract: The present invention relates to a method for fabricating a wiring substrate by forming an insulating film on a metal base having openings on the metal base at positions corresponding to metal bumps to be formed later; forming at least one layer of wiring on the base made of a metal through the insulating film, the layer of wiring having a wring film formed thereon by electroplating; and selectively etching the base. The insulating film can be a liquid photosensitive polyamide, the wiring layer can be copper and the wiring film can be a conductive layer selected from the group consisting of Ni-P and Ni. In the present invention, the wiring layer can be formed through the insulating film in contact with the metal base at the openings in the insulating film and in contact with the insulating film where there are no openings in the insulating film.

Abstract: A method of producing semiconductor devices including the steps of providing a semiconductor wafer of substantially uniform thickness 22, providing a heat-radiating plate 22, and attaching the heat-radiating plate 20 to the semiconductor wafer. The assembled wafer and heat-radiating plate are diced into individual semiconductor integrated circuits having individual heat radiating plates attached thereto.

Abstract: Semiconductor components in a wafer assembly, in which the components are connected to a frame by means of in each case one holder and are formed from the same silicon wafer. The holder connects the respective component to the frame on one side and has a desired breaking point. The desired breaking point is designed as a V-shaped groove, the surfaces of which form crystal planes. According to the method, the patterning for production of the holder takes place on the wafer back surface, with subsequent wet chemical anisotropic etching of the V-groove. In this way, the holder is produced independently of the processing of the wafer front surface, and when the semiconductor component is removed a defined broken edge is formed without there being any risk of the semiconductor component being damaged.

Abstract: In order to suppress defective lead forming and defective mounting, a semiconductor device comprises a sealing body which has a square planar shape, a semiconductor chip which lies within the sealing body, and a plurality of leads which are electrically connected with electrodes of the semiconductor chip, which extend inside and outside the sealing body and which are arrayed along latera of the sealing body, wherein an outer lead portion of each of the leads is such that a root part which protrudes out of the sealing body is formed at a lead width being equal to or greater than a lead thickness, and that a mounting part which joins to the root part through an intermediate part is formed at a lead width being less than the lead thickness.

Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on one side, so that the web-like lead frame, which is solid and flat on the other side is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation without having to cut into any additional metal.

Abstract: A solder metal made of a eutectic or stoichiometric composition including at least two metallic or semiconducting elements is applied to a contact (of the semiconductor component, brought into contact with the metal layer of a metallized film and alloyed by heating into the metal layer of the film, thereby producing an electrically conductive connection having a higher melting point. A solder metal that is particularly suitable for such a purpose is the Bi22In78 (melting point 73° C.), Bi43Sn57, or In52Sn48, or BiIn, or BiIn2.

Abstract: A singulation method used in leadless packaging process is disclosed. An array of molded products on an upper surface of a lead frame is utilized in the singulation method. The lead frame has a plurality of dambars between the molded products. The lower surface of the lead frame is attached with a tape. Each of the molded products includes a semiconductor chip encapsulated in a package body and electrically coupled to the upper surface of the lead frame. The singulation method is accomplished by etching the upper surface of the lead frame with the package bodies as mask until each dambar is etched away.

Abstract: Insulative spacers to be disposed on a surface of a semiconductor device component and methods of fabricating and placing the insulative spacers on semiconductor device components. Upon assembly of the semiconductor device component face-down upon a higher level substrate and establishing electrical communication between the semiconductor device component and the higher level substrate, the insulative spacers define a minimum, substantially uniform distance between the semiconductor device component and the higher level substrate. The insulative spacers also prevent tilting or tipping of the semiconductor device component relative to the higher level substrate. The insulative spacers may be preformed or fabricated on a surface of the semiconductor device component.

Abstract: A thermally conductive substrate includes a thermally conductive resin sheet member attached to a lead frame. The lead frame comprises a thermally conductive resin sheet member and it is integrated with the thermally conductive resin sheet member on the lead frame. The thermally conductive resin sheet member is formed from a thermosetting resin mixture which comprises 70 to 90 parts by weight of an inorganic filler and 5 to 30 parts by weight of a thermosetting resin composition including a thermosetting resin, and the thermosetting resin is in a semi-cured state.

Abstract: A semiconductor card includes a printed circuit substrate upon which is mounted a card circuit including one or more semiconductor components such as dice or packages. External contacts link the card circuit to the circuit of another apparatus by removable insertion therein. The substrate is defined by a peripheral opening in a surrounding frame, which may be part of a multiframe strip. The substrate is connected to the frame by connecting segments. The card includes a first plastic casting molded to the substrate and encapsulating the semiconductor components while leaving a peripheral portion of the substrate uncovered. A second plastic casting is molded to the peripheral portion to abut the first plastic casting and form the card periphery. A method for fabricating the semiconductor card is also included.

Abstract: A method for creating electrical interconnects between a semiconductor die and package. In the preferred embodiment, an insulating material is applied over the die and extends to the substrate contact pads, leaving a portion of each contact pad exposed. Holes are then trimmed through the insulating material, exposing at least a portion of each die bond pad. A conductive material is then applied over the die, flowing into the holes, contacting the die bond pads, and extending out to contact at least a portion of each substrate contact pad. In another preferred embodiment, an electrically conductive bump may be formed on each die bond pad, protruding through said non-conductive material and at least partially through said conductive material. The conductive layer is then laser trimmed, forming conductive patches that serve as electrical interconnects between the die and package substrate.

Abstract: A method and a circuit arrangement for protecting integrated circuits against electrostatic discharge (ESD) during and after packaging. An electrical connection between two integrated circuits is made by producing a low-impedance connection in the first integrated circuit, between a signal pad and a pad for a supply potential. The connection has a portion of reduced cross section, which is preferably severed by a current pulse applied after the arrangement has been assembled in a package and the connection has been electrically bonded to the second integrated circuit. The ESD protection during assembly requires no additional chip surface area.

Abstract: A stacked semiconductor package including: a first chip; a plurality of first leads of which one side of each of the first leads is attached to the first chip by an insulating adhesive member and electrically connected to the first chip; a first molding compound for sealing the first chip and the first leads, including holes for exposing a predetermined portion of each of the plurality of the first leads, and the first molding compound does not cover a side of the first leads opposite the holes; a first conductive portion formed within the holes included in the first molding compound; an external terminal electrically connected to the first conductive portion; a second chip; a plurality of second leads attached on the second chip by the insulating adhesive member, and being electrically connected to the second chip; a second molding compound for sealing the second chip and the second leads, and exposing a predetermined portion of the second leads; a plurality of conductive connection units for electrically co

Abstract: Two semiconductor chips are bonded to each other with the rear surfaces of the respective semiconductor chips faced to each other, so that two longer sides of the semiconductor chips may confront the side of leads, and supporting leads are bonded and fixed onto the circuit forming surface of one of the semiconductor chips. The semiconductor chips are further bonded to each other in a state where the positions of the respective semiconductor chips are staggered relative to each other so that electrodes of one semiconductor chip may lie outside the other longer side of the other semiconductor chip, and that electrodes of the second semiconductor chip may lie outside the other longer side of the first semiconductor chip.

Abstract: The present invention provides an apparatus for bonding a semiconductor chip to substrate using a non-conductive adhesive tape. The non-conductive adhesive tape may be a polyimide tape. The apparatus may include a tape provider having a reel on which the non-adhesive tape may be spooled, rollers, and a tape cutter which cuts the tape to a suitable size. A tape holder and a tape presser may also be provided to hold the tape in place while the tape cutter cuts the tape. A tape pick-up tool may be provided to transfer the cut tape to a die bonding area on the substrate. The tape holder and the tape pick-up tool may include a suction opening for providing a suction force. The apparatus may further include a die pick up tool for transferring a semiconductor chip from a semiconductor chip provider to the adhesive tape affixed to the substrate.

Abstract: A thermally conductive adhesive tape and method for its use in packaging integrated circuits fabricated on semiconductor material. The thermally conductive adhesive tape includes a thermally conductive base upon which an adhesive layer is laminated or coated onto at least one side of the thermally conductive base. Thermal energy generated by operating the integrated circuit may be transferred from the integrated circuit via the thermally conductive adhesive tape to a medium to which the semiconductor material is attached. As a result, any excessive heat that may negatively affect the performance of the integrated circuit is dissipated through the medium.

Abstract: In a method of transferring semiconductor chips from a substantially flat wafer having an active side with a plurality of individual semiconductor chips formed thereon and a support side opposite the active side to a receiver, and the wafer is attached with its support side by way of an adhesive sheet to a support structure and is cut into segments corresponding to the individual semiconductor chips so that the semiconductor chips are individually supported on the adhesive sheet with their active sides exposed and facing away from the adhesive sheet, the support structure is moved with the individual semiconductor chips into a position wherein a particular semiconductor chip to be removed is positioned in a removal location above a receiver and the adhesive sheet is pushed downwardly at the particular semiconductor chip location so as to release the particular semiconductor chip and transfer it with the active side thereof onto the receiver.

Abstract: A fabrication method for an electronic device includes four steps. The first step is for preparing a leadframe with first and second conductive members. The second step is for connecting a first and a second electronic chips to the first and the second conductive members, respectively. For the third step, the first chip is enclosed by a first resin package allowing partial exposure of the first conductive member, while the second chip by a second resin package spaced from the first package. For the fourth step, the exposed part of the first conductive member is cut. The cutting is performed using first and second tools, where the first tool makes an indentation in the exposed part on a first side. On another side opposite to the first side, the second tool makes a full cut to be linked with the indentation.

Abstract: A method of curing adhesives of a die attach material to reduce the formation of voids at the resulting bondline, defined by the interface between the adhesive and the surface of a die being attached. The method includes applying a relatively high pressure, in addition to a relatively high temperature, to cure the adhesive material.

Abstract: The semiconductor integrated circuit device comprises a planar leadframe having lead segments arranged in alternating order into first and second pluralities, the segments having their inner tips near the chip mount pad and their outer tips remote from the mount pad. The outer tips have a solderable surface. All outer tips are bent away from the leadframe plane into the direction towards the intended attachment locations on an outside substrate such that the first segment plurality forms an angle of about 70±1° from the plane and the second segment plurality forms an angle of about 75±1° (see FIG. 4). Consequently, the outer tips create a staggered lead pattern suitable for solder attachment to an outside substrate.

Abstract: A method for fabricating a leadframe structure comprising a chip mount pad and a plurality of lead segments, each having a first end near the mount pad and a second end remote from said mount pad. The structure is formed from a sheet-like starting material. In a first plating system, the leadframe is plated with a layer of nickel. Next, the second segment ends are selectively masked and a layer of palladium is selectively plated on the nickel layer on the exposed chip pad and first segments ends in a thickness suitable for wire bonding attachment. In a second plating system, the chip pad and first segment ends are selectively masked and a pure tin layer is selectively plated on the nickel layer on the exposed second segment ends in a thickness suitable for parts attachment.

Abstract: A highly reliable non-leaded semiconductor device having large terminal strength. A non-leaded semiconductor device having a seal member of insulative resin, tab suspension leads and leads exposed to the mounting surface of the seal member, a semiconductor element located in the seal member and fixed by an adhesive of the tab surface, and conductive wires for electrically connecting electrodes of the semiconductor element and leads to each other. At least a portion of the leads has an inverted trapezoid-like section configured of upper surface embedded in the seal member, lower surface opposed to the upper surface and exposed from the seal member, and side surfaces connecting the two side edges of the upper surface and the lower surface. The two side edges of the upper surface are formed with machined surfaces, respectively, having an end connected to upper surface and the other end connected to side surfaces.