Abstract: A flank wettable semiconductor device is assembled from a lead frame or substrate panel by at least partially undercutting the lead frame or substrate panel with a first cutting tool to expose a flank of the lead frame and applying a coating of tin or tin alloy to the exposed flank prior to singulating the lead frame or substrate panel into individual semiconductor devices. The method includes electrically interconnecting lead frame flanks associated with adjacent semiconductor devices before applying the coating of tin or tin alloy. The lead frame flanks may be electrically interconnected during wire bonding.

Abstract: The present invention provides a dicing tape-integrated wafer back surface protective film including: a dicing tape including a base material and a pressure-sensitive adhesive layer formed on the base material; and a wafer back surface protective film formed on the pressure-sensitive adhesive layer of the dicing tape, in which the wafer back surface protective film is colored. It is preferable that the colored wafer back surface protective film has a laser marking ability. The dicing tape-integrated wafer back surface protective film can be suitably used for a flip chip-mounted semiconductor device.

Abstract: An improved wafer level chip scale packaging technique is described which does not use an encapsulated via to connect between a redirection layer and a pad within the pad ring on the semiconductor die. In an embodiment, a first dielectric layer is formed such that it terminates on each die within the die's pad ring. Tracks are then formed in a conductive layer which contact one of the pads and run over the edge of an opening onto the surface of the first dielectric layer. These tracks may be used to form an electrical connection between the pad and a solder ball.

Abstract: A semiconductor package is provided, which includes: a semiconductor substrate having opposite first and second surfaces; an adhesive layer formed on the first surface of the semiconductor substrate; at least a semiconductor chip disposed on the adhesive layer; an encapsulant formed on the adhesive layer for encapsulating the semiconductor chip; and a plurality of conductive posts penetrating the first and second surfaces of the semiconductor substrate and the adhesive layer and electrically connected to the semiconductor chip, thereby effectively reducing the fabrication cost, shortening the fabrication time and improving the product reliability.

Abstract: A semiconductor package is provided, which includes: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top surface of the interposer; a redistribution layer formed on the encapsulant and the top surface of the interposer; and at least a semiconductor element disposed on the redistribution layer. The top surface of the interposer is flush with a surface of the encapsulant so as for the redistribution layer to have a planar surface for disposing the semiconductor element, thereby preventing warpage of the interposer and improving the reliability of electrical connection between the redistribution layer and the semiconductor element.

Abstract: A display driver integrated circuit (IC) that stores an output mode of driving circuit control signal in a non-volatile memory and a method of outputting the driving circuit control signal, wherein the display drive IC fixes the driving circuit control signal values using fixation wire disposed on top layers of the display driver IC, and a method of manufacturing the display driver IC.

Abstract: Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

Abstract: Embodiments relate to IC current sensors fabricated using thin-wafer manufacturing technologies. Such technologies can include processing in which dicing before grinding (DBG) is utilized, which can improve reliability and minimize stress effects. While embodiments utilize face-up mounting, face-down mounting is made possible in other embodiments by via through-contacts. IC current sensor embodiments can present many advantages while minimizing drawbacks often associated with conventional IC current sensors.

Abstract: A method and apparatus are provided for manufacturing a lead frame based thermally enhanced package (9) with exposed heat spreader lid array (96) designed to be optimized for compression mold encapsulation of an integrated circuit die (94) by including a perimeter reservoir regions (97r) in each heat spreader lid (96) for movement of mold compound (98) displaced during the mold compression process.

Abstract: A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array (310) designed for direct attachment to an array of integrated circuit die (306) by including a thermal interface adhesion layer (308) to each die (306) and encapsulating the attached heat spreader lid array (310) and array of integrated circuit die (306) with mold compound (321) except for planar upper lid surfaces of the heat spreader lids (312).

Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: cutting a substrate into a plurality of interposers; disposing the interposers on a carrier, wherein the interposers are spaced from one another by a distance; disposing at least a semiconductor element on each of the interposers; forming an encapsulant to encapsulate the interposers and the semiconductor elements; and removing the carrier. Therefore, by cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.

Abstract: A method for manufacturing a semiconductor device according to one embodiment of the present invention includes a step of covering a plurality of base plates in which respective semiconductor chips are mounted, by means of a sealing resin such that a plurality of base plates are spaced apart from each other, and a step of cutting the sealing resin between a plurality of base plates.

Abstract: A wafer is divided by setting the focal point of a laser beam inside the wafer at positions corresponding to division lines, thereby forming modified layers inside the wafer along the division lines. Each modified layer has a thickness ranging from the vicinity of the front side of the wafer to the vicinity of the back side of the wafer. An etching gas or an etching liquid is supplied to the wafer to erode the modified layers, thereby dividing the wafer into individual devices. The modified layers are not crushed, so fine particles are not generated in dividing the wafer. Accordingly, fine particles do not stick to the surface of each device and cause a reduction in quality. Further, since the modified layers are removed by etching, it is possible to prevent a reduction in die strength of each device due to the remainder of the modified layers.

Abstract: A light-emitting diode (LED) cutting method includes the following steps: positioning and retaining an LED die or an LED epitaxial substrate on a die retainer; introducing a liquid medium for preventing reflection of sound wave between a cutting tool and the die; activating a power source to drive a magnetostrictive material or piezoelectric ceramic material mounted on a machine to serve as a kinetic source by inducing volume expansion/compression that generates an up-and-down piston-like movement; and operating the cutting tool having super hard micro-particles of diamond, CBN, or SiC electroformed on the cutting tool to perform breaking cutting on an LED workpiece.

Abstract: A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.

Abstract: In one embodiment, a semiconductor device includes a first semiconductor chip disposed on a circuit board, an adhesive layer fixing the first semiconductor chip to the circuit board, and a second semiconductor chip having an outer shape smaller than that of the first semiconductor chip. At least a part of the second semiconductor chip is embedded in the adhesive layer. The adhesive layer has a thickness in a range of 95 to 150 ?m. The adhesive layer includes a cured product of a thermosetting resin whose thermal time viscosity at a time that the second semiconductor chip is embedded is in a range of 500 to 5000 Pa·s.

Abstract: Methods and apparatus for improved electromagnetic interference (EMI) shielding and thermal performance in integrated circuit (IC) packages are described. A die-up or die-down package includes a protective lid, a plurality of ground posts, an IC die, and a substrate. The substrate includes a plurality of ground planes. The IC die is mounted to the substrate. Plurality of ground posts is coupled to plurality of ground planes that surround IC die. Protective lid is coupled to plurality of ground posts. The plurality of ground posts and the protective lid from an enclosure structure that substantially encloses the IC die, and shields EMI from and radiating towards the IC die. The enclosure structure also dissipates heat generated by the IC die during operation.

Abstract: A substrate and a semiconductor chip are connected by means of flip-chip interconnection. Around connecting pads of the substrate and input/output terminals of the semiconductor chip, an underfill material is injected. The underfill material is a composite material of filler and resin. Also, a first main surface of the substrate, which is not covered with the underfill material, and the side surfaces of the semiconductor chip are encapsulated with a molding material. The molding material is a composite material of filler and resin. An integrated body of the substrate and the semiconductor chip, which are covered with the molding material, is thinned from above and below.

Abstract: A package-on-package (“PoP”) structure and a method of forming are provided. The PoP structure may be formed by forming a first set of electrical connections on a first substrate. A first material may be applied to the first set of electrical connections. A second substrate may be provided having a second set of electrical connections formed thereon. The first set of electrical connections of the first substrate having the epoxy flux applied may be contacted to the second electrical connections of the second substrate. A reflow process may be performed to electrically connect the first substrate to the second substrate. The epoxy flux applied to the first electrical connections of the first substrate may prohibit electrical bridges or shorts from forming during the reflow process.

Abstract: An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region; and an auxiliary pattern having a hollow pattern formed in the spacing layer, a material pattern located between the spacing layer and the device region, or combinations thereof.

Abstract: In various embodiments, a method for processing a wafer may include: providing a wafer having at least one die region and at least one metallization disposed over the at least one die region; covering the at least one metallization with a protecting layer; plasma etching the wafer to form at least one die.

Abstract: A method to construct configurable systems, the method including: providing a first configurable system including a first die and a second die, where the connections between the first die and the second die include through-silicon-via (“TSV”), where the first die is diced from a first wafer using first dice lines; providing a second configurable system including a third die and a fourth die, where the connections between the third die and the fourth die include through-silicon-via (“TSV”), where the third die is diced from a third wafer using third dice lines; and processing the first wafer and the third wafer utilizing at least 20 masks that are the same; where the first dice lines are substantially different than the third dice lines, and where the second die includes a configurable I/O to connect the first configurable system to external devices.

Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and fluid machining the semiconductor wafer to remove the backmetal layer from the singulation lines.

Abstract: The width of scribe lines may be reduced in semiconductor devices by applying a process technique in which trenches may be formed first from the rear side on the basis of a required width of the corresponding trenches, while subsequently it may be cut into the substrate from the front side on the basis of a reduced thickness of the corresponding saw blades, thereby also enabling a reduction of the scribe line width. Furthermore, contamination of the front side, i.e., of the metallization system, may be reduced, for instance, by performing an optional intermediate cleaning process.

Abstract: A method (90) entails placing (124) sensor elements (122) in an array (126) arranged to correspond with locations of controller dies (24) in a controller wafer (94) and encapsulating (128) the array (126) in a mold material (74) to form a panel (130) of the sensor elements (122). The sensor elements (122) include bond pads (42) that are concealed by a material section (116, 118) of the sensor elements (122). The controller wafer (94) is bonded (134) to the panel (130) to form a stacked wafer structure (136). After bonding, methodology (90) entails forming (140) conductive elements (60) on the controller wafer (95), removing material sections (100) from the controller wafer (94) and removing the material sections (116, 118) from the sensor elements (122) to expose the bond pads (42), forming (148) electrical interconnects (56), applying (152) packaging material (64), and singulating to produce sensor packages (20, 76).

Abstract: In one embodiment of the present invention, a method of forming a semiconductor device includes forming a device region in a first region of a semiconductor substrate, and forming an opening in a second region of the semiconductor substrate. The method further includes placing a semiconductor die within the opening, and forming a first metallization level over the semiconductor die and the device region.

Abstract: A manufacturing process includes forming a reconstituted wafer, including embedding semiconductor dice in a molding compound layer and forming through-wafer vias in the layer. A fan-out redistribution layer is formed on a front side of the wafer, with electrical traces interconnecting the dice, through-wafer vias, and contact pads positioned on the redistribution layer. Solder balls are positioned on the contact pads and a molding compound layer is formed on the redistribution layer, reinforcing the solder balls. A second fan-out redistribution layer is formed on a back side of the wafer, with electrical traces interconnecting back ends of the through-wafer vias and contact pads positioned on a back face of the second redistribution layer. Flip-chips and/or surface-mounted devices are coupled to the contact pads of the second redistribution layer and encapsulated in an underfill layer formed on the back face of the second redistribution layer.

Abstract: A semiconductor housing is provided that includes a metal support and a semiconductor body, a bottom side thereof being connected to the metal support. The semiconductor body has metal surfaces that are connected to pins by bond wires and a plastic compound, which completely surrounds the bond wires and partially surrounds the semiconductor body. The plastic compound has an opening on the top side of the semiconductor body, and a barrier is formed on the top side of the semiconductor body. The barrier has a top area and a base area spaced from the edges of the semiconductor body and an internal clearance of the barrier determines a size of the opening. Whereby, a portion of the plastic compound has a height greater than the barrier, and a fixing layer is formed between the base area of the barrier and the top side of the semiconductor body.

Abstract: Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.

Abstract: Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.

Abstract: A die structure, a manufacturing method and a substrate, wherein the die structure is constituted by a chip on wafer (COW) and the substrate, and the substrate is formed by stacking and then cutting a plurality of thermal and electrical conductive poles and a plurality of insulating material layers. Moreover, the fabricating of the die structure comprises a plurality of COWs carried on a carrier board is bonded on the substrate, the plurality of COWs are in contact with the plurality of thermal and electrical conductive poles on the substrate, and then the carrier board is removed. After that, a phosphor plate is adhered on the plurality of COWs so as to form a stacked structure. Thereafter, the stacked structure is cut, thus forming a plurality of die structures having at least one COW.

Abstract: A chip contact pad and a method of making a chip contact pad are disclosed. An embodiment of the present invention includes forming a plurality of contact pads over a workpiece, each contact pad having lower sidewalls and upper sidewalls and reducing a lower width of each contact pad so that an upper width of each contact pad is larger than the lower width. The method further includes forming a photoresist over the plurality of contact pads and removing portions of the photoresist thereby forming sidewall spacers along the lower sidewalls.

Abstract: A method of making contact pad sidewall spacer and pad sidewall spacers are disclosed. An embodiment includes forming a plurality of contact pads on a substrate, each contact pad having sidewalls, forming a first photoresist over the substrate, and removing the first photoresist from the substrate thereby forming sidewall spacers along the sidewalls of the plurality of the contact pads.

Abstract: A semiconductor package includes a passivation layer overlying a semiconductor substrate, a bump overlying the passivation layer, and a molding compound layer overlying the passivation layer and covering a lower portion of the bump. A sidewall of the passivation layer is covered by the molding compound layer.

Abstract: Electrical components such as integrated circuits may be mounted on a printed circuit board. To prevent the electrical components from being subjected to electromagnetic interference, radio-frequency shielding structures may be formed over the components. The radio-frequency shielding structures may be formed from a layer of metallic paint. Components may be covered by a layer of dielectric. Channels may be formed in the dielectric between blocks of circuitry. The metallic paint may be used to coat the surfaces of the dielectric and to fill the channels. Openings may be formed in the surface of the metallic paint to separate radio-frequency shields from each other. Conductive traces on the surface of the printed circuit board may be used in connecting the metallic paint layer to internal printed circuit board traces.

Abstract: In one embodiment, a dielectric material layer embedding metal structures is ablated from the chip-containing substrate by laser grooving, which is performed on dicing channels of the chip-containing substrate. Subsequently, an underfill layer is formed over the dielectric material layer in a pattern that excludes the peripheral areas of the chip-containing substrate. The physically exposed dicing channels at the periphery can be employed to align a blade to dice the chip-containing substrate. In another embodiment, an underfill layer is formed prior to any laser grooving. Mechanical cutting of the underfill layer from above dicing channels is followed by laser ablation of the dicing channels and subsequent mechanical cutting to dice a chip-containing substrate.

Abstract: A semiconductor device has a semiconductor substrate. The semiconductor device has a plurality of LSI regions that are formed on the semiconductor substrate and are provided with a first power supply wiring layer including a first power supply wire. The semiconductor device has a first power supply terminal formed on the semiconductor substrate. The semiconductor device has a second power supply wiring layer including a second power supply wire that electrically connects the first power supply wire and the first power supply terminal, the second power supply wiring layer is formed in a dicing region between the LSI regions along a dicing line that separates the LSI regions and the dicing line region. A first barrier metal film is formed at least in the LSI regions at a boundary between the first power supply wire and the second power supply wire.

Abstract: The present invention relates to a thermally releasable sheet-integrated film for semiconductor back surface, which includes: a pressure-sensitive adhesive sheet including a base material layer and a pressure-sensitive adhesive layer, and a film for semiconductor back surface formed on the pressure-sensitive adhesive layer of the pressure-sensitive adhesive sheet, in which the pressure-sensitive adhesive sheet is a thermally releasable pressure-sensitive adhesive sheet whose peel force from the film for semiconductor back surface decreases upon heating.

Abstract: A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.

Abstract: A wafer is provided having a chip side and a non-chip side, the chip side comprising a plurality of semiconductor chips. A plurality of dies are provided, each of the dies is bonded to one of the plurality of semiconductor chips. One or more trenches are formed on the chip side of the wafer. The chip side of the wafer and the plurality of dies are encapsulated with a protecting material, the protecting material substantially filling the one or more trenches. The wafer is diced to separate it into individual semiconductor packages.

Abstract: A semiconductor wafer having a multi-layer wiring structure is disclosed. The wafer comprises a plurality of chip die areas arranged on the wafer in an array and scribe line areas between the chip die areas. The scribe lines of a semiconductor wafer having USG top-level wiring layers above ELK wiring layers have at least one metal film structures substantially covering corner regions where two scribe lines intersect to inhibit delamination at the USG/ELK interface during wafer dicing operation.

Abstract: In one aspect of the present invention, a method of sawing a semiconductor wafer will be described. A semiconductor wafer is positioned in a wafer sawing apparatus that includes a sawing blade and a movable support structure that physically supports the semiconductor wafer. The semiconductor wafer is coupled with the support structure with various layers, including a die attach film, an adhesive and a base film. The die attach film is cut with the sawing blade. During the cutting operation, a contact portion of the sawing blade engages one of the layers and moves at least partly in one direction. While the contact portion of the sawing blade engages the layer, the support structure moves in the opposite direction. Various aspects of the present invention relate to arrangements and a wafer sawing apparatus that involve the aforementioned sawing method.

Abstract: A method of forming a packaged semiconductor device includes loading an array of package sites in position for saw singulation, saw singulating the array of package sites, and performing a non-electrolytic plating operation on exposed lead tips of individual packages from the array of package sites as the array of package sites is saw singulated.

Abstract: A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit.

Abstract: Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits.

Abstract: This disclosure provides systems, methods and apparatus for glass via bars that can be used in compact three-dimensional packages, including embedded wafer level packages. The glass via bars can provide high density electrical interconnections in a package. In some implementations, the glass via bars can include integrated passive components. Methods of fabricating glass via bars are provided. In some implementations, the methods can include patterning and etching photo-patternable glass substrates. Packaging methods employing glass via bars are also provided.

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. A method may include preparing a wiring board including a mounting region and a molding region surrounding the mounting region; forming a through-hole penetrating through the wiring board at the mounting region; mounting a semiconductor chip on the mounting region of the wiring board by a flip chip bonding method; and forming a molding covering the molding region of the wiring board and the semiconductor chip and filling the through-hole and a space between the semiconductor chip and the wiring board. The wiring board may have a first surface on which the semiconductor chip is mounted, and a second surface opposite to the first surface. A portion of the molding filling the through-hole has a surface coplanar with the second surface of the wiring board.

Abstract: A method and apparatus is described for forming and using a stiffener for the production of thinned integrated circuits. In one embodiment, a handle can be bonded to an integrated circuit wafer before the wafer is thinned. Electrical couplings such as mounting balls can be attached to the wafer. Individual dice can be singulated from the wafer by dicing through the wafer and the handle, producing a wafer/handle assembly. The wafer/handle assembly can be mounted to a printed circuit board before the handle is de-bonded.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first substrate, a second substrate, an interposer substrate, a semiconductor chip, a package body and a first antenna layer. The first substrate comprises a grounding segment. The interposer substrate is disposed between the second substrate and the first substrate. The semiconductor chip is disposed on the second substrate. The package body encapsulates the second substrate, the semiconductor chip and the interposer substrate, and has a lateral surface and an upper surface. The first antenna layer is formed on the lateral surface and the upper surface of the package body, and electrically connected to the grounding segment.

Abstract: In fabricating a semiconductor device first layers are formed of sintered bondable and solderable metal on a carrier strip. The first layers are patterned into first pads and second pads. A set of first pads is surrounding each second pad. The first pads are spaced from the second pad by gaps. The patterned layers are formed of agglomerate metal vertically on the first layers of sintered bondable and solderable metal of the first pads and of the second pad.