Abstract: Even when a strain sensor chip and an object to be measured are bonded to each other by using a metallic bonding material such as solder, the metallic bonding material shows the creep behavior when used under high temperature environment of, for example, 100° C. or higher, and therefore, the strain detected by the strain sensor chip is gradually reduced, and the strain is apparently reduced. In the strain sensor chip mounting structure which is one embodiment of the present application, a strain sensor chip is fixed onto a surface to be measured of the object to be measured via a metallic bonding material. And, the metallic bonding material is bonded to a metallic film that is formed on a side surface of the strain sensor chip. In this manner, temporal change in a measurement error can be suppressed.

Abstract: A method includes recording a wafer ID and a location ID of a device die in a database, and bonding the device die over a package substrate, wherein the device die and the package substrate are disposed in a package. A package ID is on the package. A mapping is established to link the wafer ID and the location ID of the device die to the package ID.

Abstract: Provided is a semiconductor flat package with improved mountability. In a semiconductor device, an end surface of a lead, which is exposed from an encapsulation resin, is covered with a plated layer, and a side end surface of the plated layer and a side end surface of the encapsulation resin are flush with each other. A material with good solder wettability is formed at a lead cut portion of the semiconductor flat package, to thereby improve solder connection strength with a circuit board. A solder fillet is formed from the lead cut portion of the semiconductor package, to thereby enable adaptation of solder automatic visual inspection after mounting.

Abstract: A method of manufacturing a semiconductor device includes providing a transfer foil. A plurality of semiconductor chips is placed on and adhered to the transfer foil. The plurality of semiconductor chips adhered to the transfer foil is placed over a multi-device carrier. Heat is applied to laminate the transfer foil over the multi-device carrier, thereby accommodating the plurality of semiconductor chips between the laminated transfer foil and the multi-device carrier.

Abstract: Provided are a solar cell and a method of manufacturing the same. The method of manufacturing the solar cell includes stacking a solar cell device layer containing GaN on a sacrificial substrate, etching the solar cell device layer to expose the sacrificial substrate, thereby forming one or more solar cell devices comprising the solar cell device layer, anisotropically etching the exposed sacrificial substrate, contacting the solar cell devices to a stamping processor to remove the solar cell devices from the sacrificial substrate, and transferring the solar cell devices onto a receiving substrate. A high temperature semiconductor process may be performed on a substrate such as a silicon substrate to transfer the solar cell devices onto the substrate, thereby manufacturing flexible solar cells. Also, a large number of solar cells may be excellently aligned on a large area. In addition, economical solar cells may be manufactured.

Abstract: A method of forming a window cap wafer (WCW) structure for semiconductor devices includes machining a plurality of cavities into a front side of a first substrate; bonding the first substrate to a second substrate, at the front side of the first substrate; removing a back side of the first substrate so as to expose the plurality of cavities, thereby defining the WCW structure comprising the second substrate and a plurality of vertical supports comprised of material of the first substrate.

Abstract: A reconfigured wafer of resin-encapsulated semiconductor packages is obtained by supporting with a resin, thereafter, a grinding process is performed on top and backside surfaces to expose only a bump interconnection electrode on a surface of a semiconductor chip. Further, a chip-scale package is obtained by a dicing process along a periphery of the chip.

Abstract: A wafer includes a first interposer having a first patterned metal layer and a second interposer having a second patterned metal layer. The wafer includes a metal connection in a scribe region of the wafer that electrically couples the first patterned metal layer of the first interposer with the second patterned metal layer of the second interposer forming a global wafer network. The wafer further includes a probe pad located in the scribe region that is electrically coupled to the global wafer network.

Abstract: A novel radiation hardened chip package technology protects microelectronic chips and systems in aviation/space or terrestrial devices against high energy radiation. The proposed technology of a radiation hardened chip package using rare earth elements and mulitlayered structure provides protection against radiation bombardment from alpha and beta particles to neutrons and high energy electromagnetic radiation.

Abstract: According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.

Abstract: A method and apparatus for enhancing the electrical and thermal performance of semiconductor packages effectively, especially for laminated packages, where sinterable materials cannot be used. The concept of this invention is to embed silver or silver-coated nanomaterials, which can be nanoparticles, nanoflakes, nanowires etc., into die backside to improve the interface between die and die attach materials, thus enhancing electrical and thermal performance through sintering and enhancing reliability by improving adhesion.

Abstract: Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.

Abstract: A method of making semiconductor die terminals and a semiconductor device with die terminals made according to the present method. At least a first mask layer is selectively printed on at least a portion of a wafer containing a plurality of the semiconductor devices to create first recesses aligned with electrical terminals on the semiconductor devices. A conductive material is deposited in a plurality of the first recesses to form die terminals on the semiconductor devices. The first mask layer is removed to expose the die terminals, and the wafer is diced into a plurality of discrete semiconductor devices.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a die attach paddle pad and a peripheral lead pad with an inner lead pad between the die attach paddle pad and the peripheral lead pad; forming a component side of the lead frame for exposing an upper portion of a peripheral lead under the peripheral lead pad; forming an encapsulation on the lead frame and the upper portion of the peripheral lead; exposing the peripheral lead pad; depositing a conductive shielding layer on the encapsulation connected to the peripheral lead pad; and forming a mounting side of the lead frame for forming a lower portion of the peripheral lead over a peripheral lead contact pad.

Abstract: Laser and plasma etch wafer dicing using UV-curable adhesive films. A mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The semiconductor wafer is coupled to a carrier substrate by a double-sided UV-curable adhesive film. The mask is patterned by laser scribing to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the ICs. The UV-curable adhesive film is partially cured by UV irradiation through the carrier. The singulated ICs are then detached from the partially cured adhesive film still attached to the carrier substrate, for example individually by a pick and place machine. The UV-curable adhesive film may then be further cured for the film's complete removal from the carrier substrate.

Abstract: Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region. In one or more embodiments, the edge sealing structure includes a conductive material that contacts a handle layer of semiconductor material, a crackstop structure is formed overlying the sealing structure, wherein the crackstop structure and the edge sealing structure provide an electrical connection between the handle layer and an active layer of semiconductor material that overlies a buried layer of dielectric material on the handle layer.

Abstract: A substrate-less composite power semiconductor device may be fabricated from a vertical conductive power semiconductor device wafer that includes a top metal layer located on a top surface of the wafer by a) forming solder bumps on top of the top metal layer; b) forming wafer level molding around the solder bumps such that the solder bumps are exposed through a top of the wafer level molding; c) grinding a back side of the device wafer to reduce a total thickness of a semiconductor material portion of the device wafer to a final thickness; and d) forming a back metal on a back surface of the wafer.

Abstract: Provided is a novel method for forming a groove composed of two smooth inclined surfaces on a surface of a flat plate formed of a nitride semiconductor crystal having an A, C, M-axes. In the present invention, a disk-shaped dicing blade is moved along a direction of the A-axis to form first and second inclined surfaces on the surface of the flat plate. The following mathematical formulae (I)-(III) are satisfied: 45 degrees??b?a?60 degrees (I) 45 degrees??b+a?60 degrees (II), 0 degrees?|a|?7.5 degrees, where angle ?b represents an angle formed between a surface of the edge and a radial direction of the dicing blade in a cross-sectional view which includes the M-axis and the C-axis. The angle a represents an angle formed between the principal surface and the M-axis.

Abstract: A package component includes a substrate, wherein the substrate has a front surface and a back surface over the front surface. A through-via penetrates through the substrate. A conductive feature is disposed over the back surface of the substrate and electrically coupled to the through-via. A first dielectric pattern forms a ring covering edge portions of the conductive feature. An Under-Bump-Metallurgy (UBM) is disposed over and in contact with a center portion of the conductive feature. A polymer contacts a sidewall of the substrate. A second dielectric pattern is disposed over and aligned to the polymer. The first and the second dielectric patterns are formed of a same dielectric material, and are disposed at substantially a same level.

Abstract: A semiconductor device includes a semiconductor substrate having a first main surface in which a recess is formed. Further, the semiconductor device includes an electrical interconnect structure which is arranged at a bottom of the recess. A semiconductor chip is located in the recess. The semiconductor chip includes a plurality of chip electrodes facing the electrical interconnect structure. Further, a plurality of electrically conducting elements is arranged in the electrical interconnect structure and electrically connected to the plurality of chip electrodes.

Abstract: An improved wafer level chip scale packaging technique is described which does not use an encapsulated via to connect between a redirection layer and a pad within the pad ring on the semiconductor die. In an embodiment, a first dielectric layer is formed such that it terminates on each die within the die's pad ring. Tracks are then formed in a conductive layer which contact one of the pads and run over the edge of an opening onto the surface of the first dielectric layer. These tracks may be used to form an electrical connection between the pad and a solder ball.

Abstract: Packaged semiconductor devices, methods of packaging semiconductor devices, and package-on-package (PoP) devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming through-package vias (TPVs) over a carrier, and coupling a semiconductor device to the carrier. The semiconductor device includes contact pads disposed on a surface thereof and an insulating material disposed over the contact pads. A molding material is formed over the carrier between the TPVs and the semiconductor device. Openings are formed in the insulating material using a laser drilling process over the contact pads, and a redistribution layer (RDL) is formed over the insulating material and the openings in the insulating material. A portion of the RDL is coupled to a top surface of each of the contact pads.

Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is a method of forming an interconnect structure, the method including forming a first post-passivation interconnect (PPI) over a first substrate, forming a second PPI over the first substrate, and forming a first conductive connector on the first PPI. The method further includes forming a second conductive connector on the second PPI, and forming a molding compound on top surfaces of the first and second PPIs and surrounding portions of the first and second connectors, a first section of molding compound being laterally between the first and second connectors, the first section of molding compound having a curved top surface.

Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The method includes: (a) forming cutting grooves in an element formation surface of a semiconductor wafer on which semiconductor elements are formed; (b) applying a protection tape on the element formation surface of the semiconductor wafer; (c) grinding a rear surface of the semiconductor wafer to thin the semiconductor wafer and to divide the semiconductor wafer into a plurality of semiconductor chips on which the semiconductor elements are formed; (d) forming an adhesive layer on the rear surface of the semiconductor wafer; (e) separating and cutting the adhesive layer for each of the semiconductor chips; and (f) removing the protection tape. The (e) is performed by spraying a high-pressure air to the adhesive layer formed on the rear surface of the semiconductor wafer while melting or softening the adhesive layer by heating.

Abstract: In one embodiment of a method of manufacturing a semiconductor device, a plurality of substantially columnar trenches are formed along a region for forming a dicing line in a semiconductor substrate having first surface and second surfaces opposed to each other, from the first surface. The substrate is subjected to a heat treatment. At least one hollow portion is formed in the substrate by migration of a material which composes the substrate. Semiconductor devices are formed in semiconductor regions of the substrate which are surrounded by the region for forming the dicing line. The semiconductor regions are provided on a side of the first surface. A portion of the substrate is removed from a side of the second surface until the thickness is reduced to a predetermined value. The substrate is divided into chips along a dicing line from at least the one hollow portion as a starting point.

Abstract: A method of forming a MEMS device provides first and second wafers, where at least one of the first and second wafers has a two-dimensional array of MEMS devices. The method deposits a layer of first germanium onto the first wafer, and a layer of aluminum-germanium alloy onto the second wafer. To deposit the alloy, the method deposits a layer of aluminum onto the second wafer and then a layer of second germanium to the second wafer. Specifically, the layer of second germanium is deposited on the layer of aluminum. Next, the method brings the first wafer into contact with the second wafer so that the first germanium in the aluminum-germanium alloy contacts the second germanium. The wafers then are heated when the first and second germanium are in contact, and cooled to form a plurality of conductive hermetic seal rings about the plurality of the MEMS devices.

Abstract: A method to prevent contamination of the principal surface side in a process of grinding the back surface side of a semiconductor wafer. At an intersection of a scribe region of a semiconductor wafer whose back surface side is to be ground, a plurality of insulating layers is laminated over the principal surface in the same manner as an insulating layer constituting a wiring layer laminated over a device region. Moreover, in the same layer as an uppermost wiring disposed at the uppermost layer among a plurality of the wiring layers formed for a device region, a metal pattern is formed. Furthermore, a second insulating layer covering the uppermost wiring is also formed over the metal pattern so as to cover the same.

Abstract: A semiconductor device has a semiconductor wafer and a first conductive layer formed over the semiconductor wafer as contact pads. A first insulating layer formed over the first conductive layer. A second conductive layer including an interconnect site is formed over the first conductive layer and first insulating layer. The second conductive layer is formed as a redistribution layer. A second insulating layer is formed over the second conductive layer. An opening is formed in the second insulating layer over the interconnect site. The opening extends to the first insulating layer in an area adjacent to the interconnect site. Alternatively, the opening extends partially through the second insulating layer in an area adjacent to the interconnect site. An interconnect structure is formed within the opening over the interconnect site and over a side surface of the second conductive layer. The semiconductor wafer is singulated into individual semiconductor die.

Abstract: According to one embodiment, a semiconductor device includes a board, a controller chip, a semiconductor chip, a sealing portion, and a component. The board includes a first surface and a second surface opposite to the first surface, the first surface comprising a terminal. The controller chip is on the second surface of the board. The semiconductor chip is on the second surface of the board. The sealing portion integrally covers the controller chip and the semiconductor chip and does not cover a region of the second surface of the board. The component is on the region of the second surface of the board to perform an operation with respect to the outside of the semiconductor device.

Abstract: Semiconductor growth substrates and associated systems and methods for die singulation are disclosed. A representative method for manufacturing semiconductor devices includes forming spaced-apart structures at a dicing street located between neighboring device growth regions of a substrate material. The method can further include epitaxially growing a semiconductor material by adding a first portion of semiconductor material to the device growth regions and adding a second portion of semiconductor material to the structures. The method can still further include forming semiconductor devices at the device growth regions, and separating the semiconductor devices from each other at the dicing street by removing the spaced-apart structures and the underlying substrate material at the dicing street.

Abstract: In one embodiment, a semiconductor package includes a clip frame with a first clip having a first support structure, a first lever, and a first contact portion, which is disposed on a front side of the semiconductor package. The first support structure is adjacent an opposite back side of the semiconductor package. The first lever joins the first contact portion and the first support structure. A first die is disposed over the first support structure of the first clip. The first die has a first contact pad on the front side of the semiconductor package. An encapsulant material surrounds the first die and the first clip.

Abstract: The present invention provides a laminated sheet that can prevent the decrease in adhering strength of a resin composition layer and the deterioration in electrical reliability and in which a back grinding tape can be peeled from a plurality of semiconductor elements collectively after dicing. The laminated sheet has a back grinding tape in which a pressure-sensitive adhesive layer is formed on a base, and a resin composition layer that is provided on the pressure-sensitive adhesive layer of the back grinding tape, wherein the tensile modulus of the pressure-sensitive adhesive layer at 23° C. is 0.1 to 5.0 MPa, and the T-peeling strength between the pressure-sensitive adhesive layer and the resin composition layer is 0.1 to 5 N/20 mm at 23° C. and 300 mm/min.

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having an upper surface and a lower surface; a device region or sensing region defined in the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; at least two recesses extending from the upper surface towards the lower surface of the semiconductor substrate, wherein sidewalls and bottoms of the recesses together form a sidewall of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to the sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.

Abstract: A fan-out package includes a molding compound, a conductive plug and a stress buffer. The conductive plug is in the molding compound. The stress buffer is between the conductive plug and the molding compound. The stress buffer has a coefficient of thermal expansion (CTE). The CTE of the stress buffer is between a CTE of the molding compound and a CTE of the conductive plug. A method of manufacturing a three dimensional includes plating a post on a substrate, and disposing a stress buffer on the sidewall of the post. The method further includes surrounding the stress buffer with a molding compound.

Abstract: Disclosed is a semiconductor device whose reliability can be improved. The semiconductor device includes: first wiring formed over a semiconductor substrate via a first insulating film; a second insulating film that includes an inorganic film covering the first wiring and that has a flat surface on which CMP processing has been performed; a third insulating film that is formed over the second insulating film and includes an inorganic film having moisture resistance higher than that of the second insulating film; and second wiring formed over the third insulating film. The thickness of the second wiring is 10 times or more larger than that of the first wiring, and the second wiring is located over the third insulating film without an organic insulating film being interposed between itself and the third insulating film.

Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced.

Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing a semiconductor element in a groove of a carrier; forming a dielectric layer on the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second of the carrier on a sidewall of the groove intact for the second portion to function as a supporting part. The present invention does not require formation of a silicon interposer, therefore the overall cost of the final product is much reduced.

Abstract: In a high volume method for manufacturing a microelectronic package, a spacer element and a first die, i.e., microelectronic element, can be attached face-down to a surface of a substrate, contacts on the first die facing a first through opening of the substrate. Then, a second die can be attached face-down atop the first die and the spacer element, contacts on the second die disposed beyond an edge of the first die and facing a second through opening in the substrate. Electrical connections can then be formed between each of the first and second dies and the substrate. The first and second dies can be transferred from positions of a single diced wafer which are selected to maximize compound speed bin yield of the microelectronic package.

Abstract: A stiffened semiconductor die package has a semiconductor die including an integrated circuit. The die has an active side with die bonding pads and an opposite inactive side. A conductive frame that acts as a ground plane surrounds all edges of the die and a mold compound covers the conductive frame and the edges of the die. A thermally conductive sheet is attached to the inactive side of the die. A dielectric support structure with external connector pads with solder deposits is attached to the active side of the die. The external connector pads are selectively electrically coupled to the die bonding pads.

Abstract: There is provided a method of fabricating a semiconductor device, method including: a) forming semiconductor elements in plural element regions surrounded by assumed dicing lines on a first principal surface of a semiconductor wafer; b) grinding the second principal surface in such a way that an outer peripheral portion of a second principal surface on the opposite side of the first principal surface of the semiconductor wafer becomes thicker than an inner peripheral portion of the second principal surface; c) forming a metal film, in such a way as to avoid sections corresponding to the dicing lines, on the second principal surface that has been ground in the grinding step; and d) cutting the semiconductor wafer from the second principal surface side along portions where the metal film is not formed on the dicing lines.

Abstract: The present invention provides a method for plasma dicing a substrate, the method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing a work piece onto the work piece support, said work piece having a support film, a frame and the substrate; loading the work piece onto the work piece support; applying a tensional force to the support film; clamping the work piece to the work piece support; generating a plasma using the plasma source; and etching the work piece using the generated plasma.

Abstract: The present invention provides an encapsulant with a base for use in semiconductor encapsulation, for collectively encapsulating a device mounting surface of a substrate on which semiconductor devices are mounted, or a device forming surface of a wafer on which semiconductor devices are formed, the encapsulant comprising the base, an encapsulating resin layer composed of an uncured or semi-cured thermosetting resin formed on one surface of the base, and a surface resin layer formed on the other surface of the base. The encapsulant enables a semiconductor apparatus having a good appearance and laser marking property to be manufactured.

Abstract: A method of fabricating a wafer level package includes preparing a wafer including a plurality of first semiconductor chips, mounting a plurality of second semiconductor chips on the wafer, disposing the wafer on a lower mold and disposing an upper mold so as to surround edges of a top surface of the wafer, dispensing a molding member on the wafer, and pressurizing the molding member by using a plunger so as to fabricate a wafer level package in which a top surface of each of the plurality of second semiconductor chips is exposed.

Abstract: Provided are methods of forming semiconductor modules. The method includes forming a high polymer material layer having an adhesive property on a support substrate, adhering a semiconductor chip to the support substrate using the high polymer material layer, bonding the semiconductor chip adhered to the support substrate to a flexible panel, and removing the support substrate.

Abstract: Microelectronic components and methods forming such microelectronic components are disclosed herein. The microelectronic components may include a plurality of electrically conductive vias in the form of wire bonds extending from a bonding surface of a substrate, such as surfaces of electrically conductive elements at a surface of the substrate.

Abstract: A method of manufacturing a semiconductor device includes: providing a first substrate that includes internal wiring, the first substrate including an array of chip mounting regions that includes a first chip mounting region; placing the first substrate on a first carrier line; providing a first semiconductor chip; placing the first semiconductor chip on a first moveable tray; vertically aligning the first chip mounting region of the first substrate with the first semiconductor chip, and performing initial bonding of the first semiconductor chip to the first chip mounting region of the first substrate; and performing subsequent bonding on the initially-bonded first semiconductor chip and first mounting region of the first substrate, thereby more strongly bonding the first semiconductor chip to the first substrate at the first mounting region. The initial bonding occurs after performing a subsequent bonding of at least one other semiconductor chip on the first substrate.

Abstract: A method for producing a semiconductor device in accordance with various embodiments may include providing a semiconductor workpiece attached to a first carrier; dicing the semiconductor workpiece and the carrier so as to form at least one individual semiconductor chip; mounting the at least one semiconductor chip with a side facing away from the carrier, to an additional carrier.

Abstract: A semiconductor device has a semiconductor wafer with a plurality of semiconductor die separated by a non-active region. The semiconductor die can be circular or polygonal with three or more sides. A plurality of bumps is formed over the semiconductor die. A portion of semiconductor wafer is removed to thin the semiconductor wafer. A wafer ring is mounted to mounting tape. The semiconductor wafer is mounted to the mounting tape within the wafer ring. The mounting tape includes translucent or transparent material. A penetrable layer is applied over the bumps formed over the semiconductor wafer. An irradiated energy from a laser is applied through the mounting tape to the non-active region to form a modified region within the non-active region. The semiconductor wafer is singulated along the modified region to separate the semiconductor die.

Abstract: Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes forming one or more redistribution layers over an encapsulated die having a frontside bond pad area and a frontside passivated non-bond pad area. The redistribution layers are formed to have a frontside opening over the non-bond pad area of the encapsulated die. A primary heat sink body is provided in the frontside opening and thermally coupled to the encapsulated die. A contact array is formed over the redistribution layers and is electrically coupled to a plurality bond pads located on the frontside bond pad area of the encapsulated die.

Abstract: Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method comprises encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body. The outer molded body has a portion, which circumscribes the core redistribution layer. One or more topside redistribution layers are produced over the core redistribution layer. A contact array is formed over the topside redistribution layer and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers.