Abstract: In a liquid crystal display (LCD) device having a thin film transistor (TFT), the TFT includes a source electrode, a drain electrode and a semiconductor layer. At least one of the source electrode and drain electrode includes a first layer including copper and a second layer forming an oxide layer and covering the first layer. The semiconductor layer has a substantially linear current-voltage relationship with said source electrode or drain electrode including said first and second layers, when a voltage is applied between the semiconductor layer and said source electrode or drain electrode.

Abstract: A thin film transistor substrate includes a color filter layer and a gate line. The color filter layer has a reverse taper shape, which is used to pattern the gate line without a separate mask. Thus, the total number of masks used to manufacture the thin film transistor substrate can be reduced, thereby reducing the manufacturing cost and improving the productivity.

Abstract: An object is to improve the aperture ratio of a semiconductor device. The semiconductor device includes a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate. The driver circuit includes a channel-etched thin film transistor for driver circuit and a driver circuit wiring formed using metal. Source and drain electrodes of the thin film transistor for the driver circuit are formed using a metal. A channel layer of the thin film transistor for the driver circuit is formed using an oxide semiconductor. The display portion includes a bottom-contact thin film transistor for a pixel and a display portion wiring formed using an oxide conductor. Source and drain electrode layers of the thin film transistor for the pixel are formed using an oxide conductor. A semiconductor layer of the thin film transistor for the pixel is formed using an oxide semiconductor.

Abstract: In an active matrix display device, electric characteristics of thin film transistors included in a circuit are important, and performance of the display device depends on the electric characteristics. Thus, by using an oxide semiconductor film including In, Ga, and Zn for an inverted staggered thin film transistor, variation in electric characteristics of the thin film transistor can be reduced. Three layers of a gate insulating film, an oxide semiconductor layer and a channel protective layer are successively formed by a sputtering method without being exposed to air. Further, in the oxide semiconductor layer, the thickness of a region overlapping with the channel protective film is larger than that of a region in contact with a conductive film.

Abstract: A TFT array substrate includes a substrate, at least one gate line and gate electrode, a gate insulating layer, and at least one channel component, source electrode, drain electrode and data line. The gate line and gate electrode are disposed on the substrate, wherein both of the gate line and gate electrode have first and second conductive layers, the first conductive layer is formed on the substrate, the first conductive layer contains molybdenum nitride , the second conductive layer is formed on the first conductive layer, and the second conductive layer contains copper. The gate insulating layer is disposed on the gate line, gate electrode and the substrate. The channel component is disposed on the gate insulating layer. The source electrode and drain electrode are disposed on the channel component, and data line is disposed on the gate insulating layer.

Abstract: A pixel structure disposed on a substrate including a thin film transistor (TFT), a passivation layer, and a pixel electrode is provided. The TFT includes a gate, a dielectric layer, a channel layer, and a source/drain sequentially disposed on the substrate. The source/drain is disposed on a portion of the channel layer and has a semiconductor layer, a barrier layer and a metal layer. The barrier layer is disposed on a portion of the semiconductor layer. The metal layer is disposed on the barrier layer. The barrier layer is in contact with the semiconductor layer and the metal layer. Both of the metal layer and the barrier layer are positioned within a projection area of the semiconductor layer. The passivation layer covers the TFT and the dielectric layer and has a first opening exposing the source/drain. The pixel electrode is electrically connected to the TFT through the first opening.

Abstract: A method of manufacturing a thin film transistor array substrate and a structure of the same are disclosed. The manufacturing method merely requires two steps of mask fabrication to accomplish the manufacture of thin film transistor array, in which the manufacturing method utilizes a first mask fabrication step to define a pattern of a source electrode and a drain electrode of the thin film transistor, and a partially-exposed dielectric layer, and utilizes a second mask fabrication step to define an arrangement of a transparent conductive layer. The manufacturing method and structure can dramatically reduce the manufacturing cost of masks and simplify the whole manufacturing process.

Abstract: A thin film transistor (TFT) and a method of fabricating the same are disclosed. The TFT includes a substrate, a gate electrode disposed over the substrate, a gate insulating layer disposed over the gate electrode, a semiconductor layer disposed over the gate insulating layer and including a polycrystalline silicon (poly-Si) layer, an ohmic contact layer disposed over a predetermined region of the semiconductor layer, an insulating interlayer disposed over substantially an entire surface of the substrate including the ohmic contact layer, and source and drain electrodes electrically connected to the ohmic contact layer through contact holes formed in the interlayer insulating layer. A barrier layer is interposed between the semiconductor layer and the ohmic contact layer. Thus, when an off-current of a bottom-gate-type TFT is controlled, degradation of characteristics due to a leakage current may be prevented using a simple process.

Abstract: A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes.

Abstract: A production method of a semiconductor element having a channel includes forming a resist pattern film on a thin film formed on a substrate, and pattering the thin film by etching. The production method also includes forming a second resist pattern film by applying a fluid resist material inside a channel groove after channel etching or inside a resist groove formed above a channel region before channel etching. The production method may also include forming a gate electrode, a gate insulating film, a semiconductor film, and a conductive film on an insulating substrate. The method may include applying the fluid resist material inside the channel groove, thereby forming the second resist pattern film, and patterning the semiconductor film using at least the second resist pattern film.

Abstract: A method for fabricating a display includes providing a first substrate divided into a pixel part and first and second pad parts, forming a gate electrode and a gate line in the pixel part of the first substrate and forming a gate pad line in the first pad part of the first substrate, forming a first insulation film and a semiconductor film over the gate electrode, the gate line and the gate pad line, forming an active pattern over the gate electrode from the semiconductor film with the first insulation film interposed therebetween and forming a contact hole exposing a portion of the gate pad line using a single mask, forming source and drain electrodes in the pixel part, forming a pixel electrode in the pixel part, forming a gate pad electrode electrically connected with the gate pad line via the contact hole, forming a second insulation film over the pixel electrode and the gate pad electrode, exposing a portion of the pixel electrode and at least one portion of the gate pad electrode, and attaching the fir

Abstract: The present invention provides an active matrix substrate that is capable of reliably connecting a plurality of conductive layers that are arranged with an insulating layer therebetween. The active matrix substrate of the present invention has a first conductive layer (CS) and a second conductive layer (30), and an insulating layer (22) formed to cover the first conductive layer (CS) is provided. The first conductive layer (CS) has an end portion (CS1) formed to protrude within an opening portion (H1) formed in the insulating layer (22), and the second conductive layer (30) is provided to cover at least a part of the edge of the opening portion (H1) and to be connected directly to the end portion (CS1) of the first conductive layer (CS) within the opening portion (H1).

Abstract: Embodiments of the disclosed technology provide an amorphous oxide thin film transistor (TFT), a method for preparing an amorphous oxide TFT, and a display panel. The amorphous oxide thin film transistor includes: a gate electrode, a gate insulating layer, a semiconductor active layer, a source electrode and a drain electrode. The semiconductor active layer comprises a channel layer and an ohmic contact layer, and the channel layer has a greater content of oxygen than the ohmic contact layer; the channel layer contacts the gate insulating layer, and the ohmic contact layer comprises two separated ohmic contact regions, one of which contacts the source electrode and the other of which contacts the drain electrode.

Abstract: In a method of manufacturing a thin film transistor substrate, a semiconductor pattern is formed on a substrate, a first etch stop layer and a second etch stop layer are sequentially formed on the semiconductor pattern, and the second etch stop layer and the first etch stop layer are sequentially patterned to form a second etch stop pattern and a first etch stop pattern. Thus, when the second etch stop layer is patterned using an etchant, the first etch stop layer covers the semiconductor pattern, thereby preventing the semiconductor pattern from being etched by the etchant.

Abstract: To suppress deterioration in electrical characteristics in a transistor including an oxide semiconductor layer or a semiconductor device including the transistor. In a transistor in which a channel layer is formed using an oxide semiconductor, a silicon layer is provided in contact with a surface of the oxide semiconductor layer. Further, the silicon layer is provided in contact with at least a region of the oxide semiconductor layer, in which a channel is formed, and a source electrode layer and a drain electrode layer are provided in contact with regions of the oxide semiconductor layer, over which the silicon layer is not provided.

Abstract: A formation of a gate electrode provided over an oxide semiconductor layer of a thin film transistor is performed together with a patterning of the oxide semiconductor layer.

Abstract: Methods for fabricating array substrates are provided. A method for fabricating an array substrate includes forming a first metal layer over a substrate and then patterned by a first photolithography to forming a gate line, a gate electrode connecting the gate line, and a pad over the substrate. An insulating layer, a semiconductor layer, and an ohmic contact layer are formed over the substrate to cover the gate line, the gate electrode and the pad. The ohmic contact layer, the semiconductor layer, and portions of the insulating layer are patterned by a second photolithography to forming a semiconductor structure over the substrate and a via hole in the insulating layer over the pad to exposing a part of the pad.

Abstract: A gate electrode, a gate insulation film and an inorganic oxide film are formed in this order on a substrate, and a source electrode and a drain electrode are formed to partially cover the inorganic oxide film. Then, oxidation treatment is applied to reduce the carrier density at a region of the inorganic oxide film which is not covered by the electrodes and is used as a channel region of a semiconductor device.

Abstract: A method and apparatus of fabricating a thin film transistor is disclosed, which patterns an ohmic contact layer by a laser patterning process so that it is capable of preventing a semiconductor layer from being damaged, and reducing fabrication time, wherein the method comprises forming a gate electrode pattern on a substrate; forming a gate insulating layer on the gate electrode pattern; sequentially forming a semiconductor layer pattern and an ohmic contact layer pattern on the gate insulating layer; forming source and drain electrode patterns on the ohmic contact layer pattern, wherein the source and drain electrode patterns are provided at a fixed interval therebetween; and removing the ohmic contact layer pattern exposed between the source and drain electrode patterns through the use of laser.

Abstract: Provided is a precursor composition for an oxide semiconductor. The precursor composition for the oxide semiconductor includes a metal complex compound formed by a metal ion and an organic ligand, wherein the precursor composition is represented by the following Formula 1. MAn ??(Formula 1( Herein, M is a metal ion, A is an organic ligand which includes ?-substituted carboxylate, and n is a natural number.

Abstract: An object of the present invention is to provide a thin film transistor fabricating method including a simplified step of forming contact holes. This method involves previously removing a gate insulating film (115) on a gate electrode (110) which is not covered with a channel layer (120) in a TFT (100). Hence, an insulating film formed on the gate electrode (110) which is not covered with the channel layer (120) becomes equal in thickness to an insulating film formed on a source region (120a) and a drain region (120b). Therefore, a contact hole (155) reaching a surface of the gate electrode (110) can be formed simultaneously with a contact hole (135a) reaching a surface of the source region (120a) and a contact hole (135b) reaching a surface of the drain region (120b).

Abstract: To reduce variation among TFTs in manufacture of a semiconductor device including n-type thin film transistors and p-type thin film transistors. Further, another object of the present invention is to reduce the number of masks and manufacturing steps, and manufacturing time. A method of manufacturing a semiconductor device includes forming an island-shaped semiconductor layer of a first thin film transistor, then, forming an island-shaped semiconductor layer of the second thin film transistor. In the formation of the island-shaped semiconductor layer of the second thin film transistor, a gate insulating film in contact with the island-shaped semiconductor layer of the second thin film transistor is used as a protection film (an etching stopper film) for the island-shaped semiconductor layer of the first thin film transistor.

Abstract: An LCD is manufactured to provide a wide viewing angle device and may reduce manufacturing costs according to an embodiment. The LCD includes a substrate, a gate line disposed on the substrate, a gate insulating layer disposed on the gate line, a semiconductor layer disposed on the gate insulating layer, a data line contacting the semiconductor layer, a drain electrode contacting the semiconductor layer and separated from the data line, a pixel electrode contacting the drain electrode, a passivation layer disposed on the pixel electrode, and a common electrode disposed on the passivation layer and including a branch electrode overlapping the pixel electrode. In one embodiment, the pixel electrode contacts an end portion of a thin film transistor. The LCD manufacturing process may be shortened and may save manufacturing costs because the LCD process need not make contact holes to connect the pixel electrode and the TFT.

Abstract: A display substrate includes a driving element, a switching element, a gate line, a data line, a driving voltage line and an electroluminescent element. The driving element includes a driving control electrode formed from a first conductive layer, and a driving input electrode and a driving output electrode formed from a second conductive layer. The switching element includes a switching control electrode formed from the second conductive layer, and a switching input electrode and a switching output electrode formed from a third conductive layer. The gate and data lines are formed from the second and third conductive layers, respectively. The driving voltage line is formed from the third conductive layer. Thus, misalignment between upper and lower patterns may be prevented to improve the reliability of a manufacturing process and increase an aperture ratio, thereby enhancing display quality.

Abstract: The following processes are included: preparing a substrate; forming a first gate electrode above the substrate; forming a second gate electrode above the substrate and adjacent to the first gate electrode; forming a gate insulating film on the first gate electrode and the second gate electrode; forming, on the gate insulating film, a noncrystalline semiconductor film at least in a first region above the first gate electrode and a second region above the second gate electrode; irradiating the noncrystalline semiconductor film a laser beam having continuous convex light intensity distributions; and forming a first source electrode and a first drain electrode above the first region, and a second source electrode and a second drain electrode above the second region. In the irradiating, when irradiating the first region with an inner region of the laser beam, the second region is irradiated with an outer region of the laser beam.

Abstract: An object of this invention is to provide a semiconductor device in which TFTs with high mobility are arranged in both of display and peripheral circuit areas. A semiconductor device fabricating method according to the present invention includes the steps of: irradiating an amorphous silicon layer (34) with energy, thereby obtaining a microcrystalline silicon layer; and forming a doped semiconductor layer (35) on the amorphous silicon layer (34). In the step of irradiating, the amorphous silicon layer (34) is irradiated with energy that has a first quantity, thereby forming a first microcrystalline silicon layer (34A) including a channel layer for a first TFT (30A), and is also irradiated with energy that has a second quantity, which is larger than the first quantity, thereby forming a second microcrystalline silicon layer (34B) including a channel layer for a second TFT (30B).

Abstract: A manufacturing method of thin film transistors is provided. The manufacturing method includes: providing a substrate; forming a gate electrode; forming a gate insulating layer; forming a patterned oxide semiconductor layer; forming a source electrode and a drain electrode; and executing a localized laser treatment. A laser beam is used to irradiate at least a part of the patterned oxide semiconductor layer in the localized laser treatment. An electrical resistitivity of the patterned oxide semiconductor layer irradiated by the laser beam is lower than an electrical resistitivity of the patterned oxide semiconductor layer without being irradiated by the laser beam.

Abstract: A bi-layer pseudo-spin field-effect transistor (BiSFET) is disclosed. The BiSFET includes a first and second conduction layers separated by a tunnel dielectric. The BiSFET transistor also includes a first gate separated from the first conduction layer by an insulating dielectric layer, and a second gate separated from the second conduction layer by an insulating layer. These conduction layers may be composed of graphene. The voltages applied to the first and/or second gates can control the peak current and associated voltage value for current flow between top and bottom conduction channels, and interlayer current voltage characteristic exhibiting negative differential resistance. BiSFETs may be used to make a variety of logic gates. A clocked power supply scheme may be used to facilitate BiSFET-based logic.

Abstract: A pixel structure and a manufacturing method thereof and a display panel are provided. An electrode material layer, a shielding material layer, an inter-layer dielectric material layer, a semiconductor material layer and a photoresist-layer are sequentially formed on a substrate. The semiconductor material layer, the inter-layer dielectric material layer, the shielding material layer and the electrode material layer are patterned using the photoresist-layer as a mask to form a semiconductor pattern, an inter-layer dielectric pattern, a shielding pattern and a pixel electrode. A source/drain electrically connected to the pixel electrode and covering a portion of the semiconductor pattern is formed on the pixel electrode. A channel is another portion of the semiconductor uncovered by the source/drain.

Abstract: Integrated circuit multilayer integration techniques are provided. In one aspect, a method of fabricating an integrated circuit is provided. The method includes the following steps. A substrate is provided. A plurality of interconnect layers are formed on the substrate arranged in a stack, each interconnect layer comprising one or more metal lines, wherein the metal lines in a given one of the interconnect layers are larger than the metal lines in the interconnect layers, if present, above the given interconnect layer in the stack and wherein the metal lines in the given interconnect layer are smaller than the metal lines in the interconnect layers, if present, below the given interconnect layer in the stack. At least one transistor is formed on a top-most layer of the stack.

Abstract: Thin film transistors (TFT) and methods of manufacturing the same. A TFT includes a line-shaped gate of uniform thickness. A cross-section of the gate is curved where a side surface and a top surface meet. The gate includes one, or two or more gate lines.

Abstract: The present invention relates to a thin film transistor and a method of manufacturing the same. More particularly, the present invention relates to a thin film transistor that includes a zinc oxide material including Si as a channel material of a semiconductor layer, and a method of manufacturing the same.

Abstract: A display device including the thin film transistor, and a method of manufacturing the display device are provided. The thin film transistor comprising a first gate electrode, a second gate electrode formed on the first gate electrode, a first semiconductor formed on the first gate electrode and including a polycrystalline semiconductor, a second semiconductor formed on the second gate electrode and including an amorphous semiconductor.

Abstract: To improve the reliability of contact with an anisotropic conductive film in a semiconductor device such as a liquid crystal display panel, a terminal portion (182) of a connecting wiring (183) on an active matrix substrate is electrically connected to an FPC (191) by an anisotropic conductive film (195). The connecting wiring (183) is manufactured in the same process with a source/drain wiring of a TFT on the active matrix substrate, and is made of a lamination film of a metallic film and a transparent conductive film. In the connecting portion with the anisotropic conductive film (195), a side surface of the connecting wiring (183) is covered with a protecting film (173) made of an insulating material.

Abstract: A microcrystalline semiconductor film with high crystallinity is manufactured. In addition, a thin film transistor with excellent electric characteristics and high reliability, and a display device including the thin film transistor are manufactured with high productivity. A deposition gas containing silicon or germanium is introduced from an electrode including a plurality of projecting portions provided in a treatment chamber of a plasma CVD apparatus, glow discharge is caused by supplying high-frequency power, and thereby crystal particles are formed over a substrate, and a microcrystalline semiconductor film is formed over the crystal particles by a plasma CVD method.

Abstract: The display device having a thin film transistor formed on a substrate including a display portion is provided. The thin film transistor including: a gate electrode; a gate insulating film formed so as to cover the gate electrode; a semiconductor laminated film formed on top the gate insulating film so as to extend over the gate electrode, the semiconductor laminated film being formed by laminating at least a polycrystalline semiconductor film and an amorphous semiconductor film, a first electrode and a second electrode disposed on top of the semiconductor laminated film so as to be opposed to each other across a region superposing the gate electrode. In the display device, the semiconductor laminated film is formed immediately below a wiring extending from the first electrode and immediately below a wiring extending from the second electrode.

Abstract: A thin film transistor includes a gate electrode, a gate insulating layer on the gate electrode, a semiconductor on the gate insulating layer, and a drain electrode and a source electrode on the semiconductor and spaced apart from each other. Each of the drain electrode and the source electrode includes a first metal diffusion preventing layer which prevents diffusion of metal atoms, and a second metal diffusion preventing layer on the first metal diffusion preventing layer. At least one of the first and second metal diffusion preventing layers includes grains in a columnar structure, which are in a direction substantially perpendicular to a lower layer. First grain boundaries of the first metal diffusion preventing layer and second grain boundaries of the second metal diffusion preventing layer are substantially discontinuous in a direction perpendicular to the semiconductor.

Abstract: A method of fabricating a polycrystalline silicon layer includes: forming an amorphous silicon layer on a substrate; crystallizing the amorphous silicon layer into a polycrystalline silicon layer using a crystallization-inducing metal; forming a metal layer pattern or metal silicide layer pattern in contact with an upper or lower region of the polycrystalline silicon layer corresponding to a region excluding a channel region in the polycrystalline silicon layer; and annealing the substrate to getter the crystallization-inducing metal existing in the channel region of the polycrystalline silicon layer to the region in the polycrystalline silicon layer having the metal layer pattern or metal silicide layer pattern. Accordingly, the crystallization-inducing metal existing in the channel region of the polycrystalline silicon layer can be effectively removed, and thus a thin film transistor having an improved leakage current characteristic and an OLED display device including the same can be fabricated.

Abstract: Provided is a display device which includes: a gate electrode; a first semiconductor layer in a crystallized state which is formed over the gate electrode; a source electrode and a drain electrode which are formed over the first semiconductor layer; and a second semiconductor layer which extends from a side of the first semiconductor layer and is interposed between one of the source electrode and the drain electrode and the first semiconductor layer, wherein the second semiconductor layer includes a first portion which is formed in a crystallized state and brought into contact with the first semiconductor layer, and a second portion which has lower crystallinity than the first portion.

Abstract: The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode on the gate electrode; and a pixel electrode electrically connected to the drain electrode.

Abstract: A thin-film transistor device manufacturing method of forming a crystalline silicon film of stable crystallinity using a laser of a wavelength in a visible region is provided. The thin-film transistor device manufacturing method forms a plurality of gate electrodes above a substrate. A gate insulation layer is formed on the plurality of gate electrodes. An amorphous silicon layer is formed on the gate insulation layer. The amorphous silicon layer is crystallized using predetermined laser light to produce a crystalline silicon layer. A source electrode and a drain electrode are formed on the crystalline silicon layer in a region that corresponds to each of the plurality of gate electrodes. A film thickness of the gate insulation layer and a film thickness of the amorphous silicon layer satisfy predetermined conditional expressions.

Abstract: A display apparatus includes a substrate and a plurality of pixels disposed on the substrate. Each pixel includes a gate electrode disposed on the substrate, a gate dielectric layer disposed on the substrate and the gate electrode, an oxide semiconductor pattern disposed on the gate dielectric layer, a first insulating pattern disposed on the oxide semiconductor pattern that overlaps the gate electrode, a second insulating pattern disposed on the oxide semiconductor pattern and spaced apart from the first insulating pattern, source and drain electrodes spaced apart from each other on the oxide semiconductor pattern, a pixel electrode pattern disposed on the second insulating pattern to make contact with the source electrode, and a channel area defined where the oxide semiconductor pattern overlaps the gate electrode. A high carrier mobility channel is formed in the channel area when a turn-on voltage is applied to the gate electrode.

Abstract: In a display substrate and a method of manufacturing the display substrate, the display substrate includes a data line, a channel pattern, an insulating pattern and a pixel electrode. The data line extends in a direction on a base substrate. The channel pattern is disposed in a separate region between an input electrode connected to the data line and an output electrode spaced apart from the input electrode. The channel pattern makes contact with the input electrode and the output electrode on the input and output electrodes. The insulating pattern is spaced apart from the channel pattern on the base substrate and includes a contact hole exposing the output electrode. The pixel electrode is formed on the insulating pattern to make contact with the output electrode through the contact hole. Thus, a damage of the oxide semiconductor layer may be minimized and a manufacturing process may be simplified.

Abstract: Disclosed herein is a manufacturing method of a thin film transistor including: forming a channel layer made of an oxide semiconductor above a gate electrode with a gate insulating film provided therebetween, forming a channel protection film made of a conductive material adapted to cover the channel layer and forming a pair of source and drain electrodes in such a manner as to be in contact with the channel protection film; and removing the region of the channel protection film between the source/drain electrodes by etching relying on selectivity between the conductive material and crystalline oxide semiconductor.

Abstract: A pixel structure is disclosed. The pixel structure includes a substrate, a first data line having at least one end formed on the substrate, a first insulation layer overlying the first data line and exposing a part of the end of the first data line, a shielding electrode disposed on the first insulation layer and overlapped with the first data line, a second data line formed on the first insulation layer and electrically connected to the exposed end of the first data line, a second insulation layer overlying the shielding electrode and the second data line, and a pixel electrode formed on the second insulation layer and overlapped with the shielding electrode. The invention also provides a method for fabricating the pixel structure.

Abstract: In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.

Abstract: An object is to suppress deterioration in electric characteristics in a transistor including an oxide semiconductor layer or a semiconductor device including the transistor. In a transistor in which a channel layer is formed using an oxide semiconductor, a silicon layer is provided in contact with a surface of the oxide semiconductor layer, an impurity semiconductor layer is provided over the silicon layer, and a source electrode layer and a drain electrode layer are provided to be electrically connected to the impurity semiconductor layer.

Abstract: A method of manufacturing a thin film transistor array substrate includes: forming a gate pattern on a substrate; forming a first gate insulating film and a second gate insulating film on the substrate; forming a source/drain pattern and a semiconductor pattern on the substrate; forming a passivation film on the substrate; forming a photo-resist pattern on the passivation film; patterning the passivation film using the photo-resist pattern to form a passivation film pattern, the patterning of the passivation film including over-etching the passivation film to form an open region in the passivation film; forming a transparent electrode film on the substrate; removing the photo-resist pattern and a portion of the transparent electrode film on the photo-resist pattern; and forming a pixel electrode on the first gate insulating layer.

Abstract: A method for making a flexible semiconductor device includes the following steps. A rigid substrate is provided. A flexible substrate is provided, and placed on the rigid substrate. A semiconductor device is directly formed on the flexible substrate using a semiconductor process. After the rigid substrate is removed, the flexible semiconductor device is formed.

Abstract: An object is to provide a film deposition apparatus in which the amount of leakage from the outside of the chamber to the inside of the chamber is reduced. Even if leakage occurs from the outside of the chamber to the inside of the chamber, oxygen and nitrogen included in an atmosphere that surrounds the outer wall of the chamber are reduced as much as possible and the atmosphere is filled with a noble gas or hydrogen, whereby the inside of the chamber is kept cleaner at 1/100 or less, preferably, 1/1000 or less of oxygen concentration and nitrogen concentration than those in the air. Since the space with high airtightness is provided adjacent to the outside of the chamber, the chamber is covered with a bag and a high-purity argon gas is supplied to the bag.