Abstract: A method for manufacturing a flexible semiconductor device comprises (i) forming an insulating film on the upper surface of a resin film, (ii) forming a pattern of extraction electrodes on the upper surface of the resin film, (iii) forming a semiconductor layer on the insulating film in such a manner that the semiconductor layer is in contact with the pattern of extraction electrodes, and (iv) forming a sealing resin layer on the upper surface of the resin film in such a manner that the sealing resin layer covers the semiconductor layer and the pattern of extraction electrodes, wherein at least one of the stepsof the above steps (i) to (iv) is carried out by a printing method. With this manufacturing method, various layers can be formed by a simple printing process without using a vacuum process, photolithography, or the like.

Abstract: The present invention has an object of providing a TFT in which generation of an OFF current is reduced by an efficient manufacturing method. A thin film transistor 100 according to the present invention has a gate electrode 12 formed on a substrate 10, an insulating layer 14 formed on the gate electrode 12, a microcrystalline amorphous silicon layer 18 and an amorphous silicon layer 16 that are formed on the insulating layer 14, a semiconductor layer 20 containing an impurity formed on the amorphous silicon layer 16, and a source electrode 22A and a drain electrode 22B that are formed on the semiconductor layer 20 containing an impurity. The microcrystalline amorphous silicon layer 18 and the semiconductor layer 20 containing an impurity are connected to each other through the amorphous silicon layer 16 without being in direct contact with each other.

Abstract: Disclosed herein is a thin film transistor array substrate. The thin film transistor array substrate includes a display area and a non-display area. The non-display area includes a signal line, a connecting line and a metal contact. The connecting line is formed in a first patterned metal layer. The signal line and the metal contact are formed in a second patterned metal layer. The connecting line is connected to the signal line by a first through-hole, and the connecting line is connected to the metal contact by a second through-hole Furthermore, a method of fabricating the thin film transistor array substrate is also disclosed.

Abstract: The embodiments of the present invention disclose an array substrate and manufacturing method thereof, and a display device. The array substrate provided in an embodiment of the present invention comprises: a substrate, and a gate metal layer, an active layer and a source/drain metal layer formed on the substrate; wherein, on at least one side of the gate metal layer, there is formed an isolation buffer layer, and/or, on at least one side of the source/drain metal layer, there is formed an isolation buffer layer; furthermore, the isolation buffer layer is made of molybdenum oxide.

Abstract: A method of manufacturing a thin-film semiconductor device according to the present disclosure includes: preparing a substrate; forming a gate electrode above the substrate; forming a first insulating film on the gate electrode; forming a semiconductor thin film that is to be a channel layer, on the first insulating film; forming a second insulating film on the semiconductor thin film; irradiating the second insulating film with a beam so as to increase a transmittance of the second insulating film; and forming a source electrode and a drain electrode above the channel layer.

Abstract: In a method for manufacturing an organic transistor element, an electrode is subjected to wet etching into a predetermined pattern on an organic semiconductor layer. In the process for performing wet etching on the electrode so as to obtain a predetermined pattern, an etching liquid containing a dopant of the organic semiconductor layer is used to perform wet etching on the electrode and, simultaneously, the organic semiconductor layer is doped with the dopant.

Abstract: A threshold voltage of a thin film transistor is adjusted. The thin film transistor is manufactured through the steps of: introducing a semiconductor material gas into a treatment chamber; forming a semiconductor film in the treatment chamber over a gate insulating layer provided covering a gate electrode; evacuating the semiconductor material gas in the treatment chamber; introducing rare gas into the treatment chamber; performing plasma treatment on the semiconductor film in the treatment chamber; forming an impurity semiconductor film over the semiconductor film; processing the semiconductor film and the impurity semiconductor film into island shapes, so that a semiconductor stack is formed; forming source and drain electrodes in contact with an impurity semiconductor layer included in the semiconductor stack. Argon is preferably used as the rare gas. The rare gas element is preferably contained in the semiconductor film at 2.5×1018 cm?3 or more.

Abstract: A method for manufacturing a LCD panel includes providing a substrate defining a TFT region and a pixel region; forming a transparent conductive layer and a first metal layer on the substrate in that order; forming a gate line in the TFT region, and a pixel electrode within the pixel region via a first photo-etching process; forming an insulating layer and a semiconductor layer on the substrate in that order; removing the insulating layer and the semiconductor layer from the pixel region; removing the first metal layer from the pixel region; forming a second metal layer on the substrate; forming a source electrode and a drain electrode in the TFT region via a second photo-etching process, and forming a protecting layer above the substrate.

Abstract: A thin film transistor including: a substrate; a gate electrode formed on the substrate; a gate insulating layer formed on the gate electrode and exposed portions of the substrate; an oxide semiconductor layer formed on the gate insulating layer to correspond to the gate electrode, and comprising an HfInZnO-based oxide semiconductor, wherein the concentration of Hf is from about 9 to about 15 at % based on 100 at % of the total concentration of Hf, In, and Zn; and source and drain regions respectively formed to extend on both sides of the oxide semiconductor layer and the gate insulating layer.

Abstract: Carbon nanotubes can be aligned with compatibility with semiconductor manufacturing processes, with scalability for forming smaller devices, and without performance degradation related to structural damages. A planar structure including a buried gate electrode and two embedded electrodes are formed. After forming a gate dielectric, carbon nanotubes are assembled in a solution on a surface of the gate dielectric along the direction of an alternating current (AC) electrical field generated by applying a voltage between the two embedded electrodes. A source contact electrode and a drain contact electrode are formed by depositing a conductive material on both ends of the carbon nanotubes. Each of the source and drain contact electrodes can be electrically shorted to an underlying embedded electrode to reduce parasitic capacitance.

Abstract: A Thin Film Transistor (TFT) includes a substrate, a semiconductor layer disposed on the substrate a first source electrode and a first drain electrode spaced apart from each other on the semiconductor layer, a channel area disposed in the semiconductor layer between the first source electrode and the first drain electrode, an etching prevention layer disposed on the channel area, the first source electrode, and the first drain electrode and a second source electrode in contact with the first source electrode, and a second drain electrode in contact with the first drain electrode.

Abstract: The present invention provides an array substrate, comprising: a base substrate; a pixel electrode pattern and a gate pattern formed on the base substrate, the gate pattern comprises a gate scanning line and a gate electrode of a transistor, both of the gate scanning line and the gate electrode comprise transparent conductive metal layer and the gate metal layer stacking on the substrate, each pixel electrode in the pixel electrode pattern comprises transparent conductive metal layer; a gate insulating layer on the pixel electrode pattern and the gate pattern, an active layer pattern on the gate insulating layer and corresponding to the gate electrode, a via hole in the gate insulating layer for exposing the pixel electrode; and a source/drain pattern on the gate insulating layer, the source/drain pattern comprises a data scanning line crossing with the gate scanning line, source and drain electrodes of the transistor, and the drain electrode is in contact with the pixel electrode through the via hole.

Abstract: An object is to provide a thin film transistor with small off current, large on current, and high field-effect mobility, A silicon nitride layer and a silicon oxide layer which is formed by oxidizing the silicon nitride layer are stacked as a gate insulating layer, and crystals grow from an interface of the silicon oxide layer of the gate insulating layer to form a microcrystalline semiconductor layer; thus, an inverted staggered thin film transistor is manufactured. Since crystals grow from the gate insulating layer, the thin film transistor can have a high crystallinity, large on current, and high field-effect mobility. In addition, a buffer layer is provided to reduce off current.

Abstract: In a thin film transistor, first and second thin film transistors are connected to an Nth gate line and an Mth data line, and first and second sub pixel electrodes are connected to the first and second thin film transistors, respectively. A third thin film transistor includes a gate electrode connected to an (N+1)th gate line, a semiconductor layer overlapping with the gate electrode, a source electrode connected to the second sub pixel electrode and partially overlapping with the gate electrode, and a drain electrode facing the source electrode. A first auxiliary electrode is connected to the drain electrode and arranged on the same layer as the first and second sub pixel electrodes. An opposite electrode is arranged on the same layer as the gate line and at least partially overlaps with the first auxiliary electrode with at least one insulating layer disposed therebetween.

Abstract: The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.

Abstract: Provided are an organic TFT manufacturing method whereby flow of ink into an unnecessary area can be suppressed and excellent characteristics and high reliability can be obtained, and an organic TFT. The organic TFT manufacturing method comprises a step of providing a source electrode and a drain electrode on a base member; a step of providing a bank layer, which has an opening on a channel between the source electrode and the drain electrode, an opening on a predetermined area of the base member, and a groove or grooves around the opening on the predetermined area, which surround the opening on the predetermined area; and a step of supplying an organic semiconductor solution to the opening of the bank layer formed on the channel to form an organic semiconductor layer.

Abstract: A method of manufacturing a thin film transistor array substrate and a structure of the same are disclosed. The manufacturing method merely requires two steps of mask fabrication to accomplish the manufacture of thin film transistor array, in which the manufacturing method utilizes a first mask fabrication step to define a pattern of a source electrode and a drain electrode of the thin film transistor, and a partially-exposed dielectric layer, and utilizes a second mask fabrication step to define an arrangement of a transparent conductive layer. The manufacturing method and structure can dramatically reduce the manufacturing cost of masks and simplify the whole manufacturing process.

Abstract: A thin-film transistor array device includes: a driving TFT including a first crystalline semiconductor film including crystal grains having a first average grain size; and a switching TFT including a second crystalline semiconductor film including crystal grains having a second average grain size that is smaller than the first average grain size. The first crystalline semiconductor film and the second crystalline semiconductor film are formed at the same time by irradiating a noncrystalline semiconductor film using a laser beam having a Gaussian light intensity distribution such that a temperature of the noncrystalline semiconductor film is within a range of 600° C. to 1100° C., and the first crystalline semiconductor film is formed such that the temperature of the noncrystalline semiconductor film is within a temperature range of 1100° C. to 1414° C. due to latent heat generated by the laser irradiation.

Abstract: A thin film transistor, including a transparent channel pattern, a transparent gate insulating layer in contact with the channel pattern, a passivation film pattern disposed on the channel pattern, a source/drain coupled to the channel pattern through a via hole in the passivation film pattern, and a gate facing the channel pattern, the gate insulating layer interposed between the gate and the channel pattern, wherein the passivation film pattern includes at least one of polyimide, photoacryl, and spin on glass (SOG).

Abstract: It is an object to increase the mobility of a thin film transistor having an active layer including a microcrystalline semiconductor film. Upon fabricating an inverted staggered type TFT 10, a substrate is vacuum-transferred to a plasma enhanced CVD apparatus such that a surface of a microcrystalline silicon film (active layer 40) exposed by gap etching is not exposed to the air. An insulating film 80 is deposited by the plasma enhanced CVD apparatus so as to completely cover the exposed surface of the microcrystalline silicon film. By this, even if the microcrystalline silicon film is exposed to the air, oxygen cannot be adsorbed on the surface thereof and thus diffusion of oxygen into the microcrystalline silicon film can be suppressed. In addition, since N+ silicon films composing contact layers 50a and 50b directly contact with the microcrystalline silicon film, the contact resistance can be reduced.

Abstract: A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided.

Abstract: A method for manufacturing a semiconductor device having favorable electric characteristics with high productivity is provided. A first microcrystalline semiconductor film is formed over an oxide insulating film under a first condition that mixed phase grains with high crystallinity are formed at a low particle density. After that, a second microcrystalline semiconductor film is stacked over the first microcrystalline semiconductor film under a second condition that a space between the mixed phase grains are filled by the crystal growth of the mixed phase grains of the first microcrystalline semiconductor film.

Abstract: Provided are a manufacturing method for a thin film transistor, and a thin film transistor manufactured by the manufacturing method. In the manufacturing method, a semiconductor layer and an insulating layer for stopping etching, which are sequentially stacked, are etched by dry etching and wet etching using a single photoresist pattern, and patterning the semiconductor layer and the insulating layer into a channel layer and an etch stop layer, respectively, thereby simplifying the manufacturing process of the thin film transistor.

Abstract: A semiconductor device includes a gate electrode formed on an insulating substrate, a gate insulating film covering the gate electrode, a semiconductor layer formed on a surface of the gate insulating film and having a channel region facing the gate electrode, and an electrode layer connected to the semiconductor layer. An island-shaped interlayer insulating film covering the channel region is formed on a surface of the semiconductor layer. An end portion of the interlayer insulating film is interposed between the semiconductor layer and the electrode layer. Outer edges of the interlayer insulating film are located further inside than respective corresponding outer edges of the semiconductor layer by the same width, as viewed in a normal direction of a surface of the insulating substrate. The electrode layer is connected to an end portion of the semiconductor layer.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate and a 3D structure disposed over the substrate. The semiconductor device further includes a dielectric layer disposed over the 3D structure, a WFMG layer disposed over the dielectric layer, and a gate structure disposed over the WFMG layer. The gate structure traverses the 3D structure and separates a source region and a drain region of the 3D structure. The source and drain region define a channel region therebetween. The gate structure induces a stress in the channel region.

Abstract: Some embodiments include a method of manufacturing electronic devices on both sides of a carrier substrate and electronic devices thereof. Other embodiments of related methods and structures are also disclosed.

Abstract: A thin-film semiconductor device for a display apparatus according to the present disclosure includes: a gate electrode above a substrate; a gate insulating film above the gate electrode; a semiconductor layer above the gate electrode; a first electrode above the semiconductor layer; a second electrode in a same layer as the first electrode; an interlayer insulating film covering the first electrode and the second electrode; a gate line above the interlayer insulating film; a first power supply line electrically connected to the second electrode and in a same layer as the second electrode; and a second power supply line in a same layer as the gate line. Furthermore, the gate electrode and the gate line are electrically connected via a first conductive portion, and the first power supply line and the second power supply line are electrically connected via a second conductive portion.

Abstract: A pixel structure disposed on a substrate having an array of pixel areas is provided. The common electrode wire is positioned only in a portion of the pixel area. A first capacitance storage electrode is disposed in each of the pixel areas and electrically connected between two adjacent common electrode wires. A gate insulation layer covers the scan line, the gate electrode, the common electrode wire and the first capacitance storage electrode. A semiconductor layer is disposed on the gate insulation layer above the gate electrode. The source and the drain are disposed on two sides of the semiconductor layer. A passivation layer is disposed on the substrate to cover the data line, the source and the drain. The passivation layer above the drain has a contact window. A pixel electrode is electrically connected with the drain through the contact window.

Abstract: A fabricating method of a pixel structure is provided. A substrate has an array of pixel areas. The common electrode wire is positioned only in a portion of the pixel area. A first capacitance storage electrode is formed in each of the pixel areas and electrically connected between two adjacent common electrode wires. A gate insulation layer covers the scan line, the gate electrode, the common electrode wire and the first capacitance storage electrode. A semiconductor layer is formed on the gate insulation layer above the gate electrode. The source and the drain is formed on two sides of the semiconductor layer. A passivation layer is formed on the substrate to cover the data line, the source and the drain. A pixel electrode is formed in each of the pixel areas, and the pixel electrode is electrically connected with the drain through the contact window.

Abstract: Disclosed is a thin film transistor, comprising a first conductive layer, a first insulation layer, an amorphous silicon layer, an ohmic contact layer, a second insulation layer, a second conductive layer, a protective layer and a transparent electrode layer. The present invention also relates to a manufacture method of the thin film transistor. The thin film transistor and the manufacture method of the present invention implements merely three stages of photolithography processes to complete the manufacture of the thin film transistor, and therefore to save the manufacture cost and the process time of the thin film transistor.

Abstract: A method of fabricating a thin film transistor array substrate is disclosed.

Abstract: A TFT 17 provided on a substrate 3 is provided. The TFT 17 includes a gate electrode 31, a gate insulating film 32, a semiconductor 33, a source electrode 34, a drain electrode 35, and a protection film 36. The semiconductor 33 includes a metal oxide semiconductor. The semiconductor 33 has a source portion 33a which is in contact with the source electrode 34, a drain portion 33b which is in contact with the drain electrode 35, and a channel portion 33c which is exposed through the source electrode 34 and the drain electrode 35. A conductive layer 37 having a relatively small electrical resistance is formed in each of the source portion 33a and the drain portion 33b. The conductive layer 37 is removed from the channel portion 33c.

Abstract: A thin film transistor includes a substrate with a recess formed therein, a channel region received in the recess, a gate insulating layer formed on the channel region, a gate electrode formed on the gate insulating layer, and a source region and a drain region connecting the channel region, respectively. The gate insulating layer and the gate electrode are positioned between the source region and the drain region. The channel region is made of a nitride compound semiconductor. A method of manufacturing the thin film transistor is also provided.

Abstract: In an oxide semiconductor layer, a degree of oxidation S1 of a portion located on the side of the gate insulating film, and a degree of oxidation S2 of surface layer portions located in connection regions with source and drain electrodes have a relation of S2<S1 within a range in which the oxide semiconductor layer has predetermined electric resistance, and a degree of oxidation S3 of a surface layer portion of the channel region is made higher than the degrees of oxidation S1, S2 of the other regions within the range in which the oxide semiconductor layer has the predetermined electric resistance, by annealing the oxide semiconductor layer in an oxygen-containing atmosphere after formation of the source electrode and the drain electrode.

Abstract: A silicon compound film is dry etched by parallel-plate type dry etching using an etching gas including at least COF2.

Abstract: An organic light emitting display apparatus and a method of manufacturing the organic light emitting display apparatus, whereby the manufacturing process is simplified and the electric characteristics of the organic light emitting display apparatus are improved. The organic light emitting display apparatus includes: a gate electrode that includes a first conductive layer including ITO, a second conductive layer on the first conductive layer, a third conductive layer on the second conductive layer and including ITO, and a fourth conductive layer on the third conductive layer and including IZO or AZO; and a pixel electrode formed in the same layer level as the gate electrode and including a first electrode layer that includes ITO, a second electrode layer on the first electrode layer, a third electrode layer on the second electrode layer and including ITO, and a fourth electrode layer on the third electrode layer and including IZO or AZO.

Abstract: A source electrode and a drain electrode are formed by a stack of a titanium layer, a molybdenum nitride layer, an aluminum layer, and a molybdenum nitride layer, the titanium layer is formed by dry etching, and an oxide semiconductor layer is formed by performing annealing in an oxygen-containing atmosphere after formation of the source electrode and the drain electrode.

Abstract: A display device includes: a substrate; an infrared sensing transistor on the substrate; a readout transistor connected to the infrared sensing transistor; a power source line; and a light blocking member on the infrared sensing transistor, where the infrared sensing transistor includes a light blocking film on the substrate, a first gate electrode contacting and overlapping the light blocking film and connected to a power source line, a first semiconductor layer on the first gate electrode overlapping the light blocking film, and first source and drain electrodes on the first semiconductor layer, where the readout transistor includes a second gate electrode on the substrate, a second semiconductor layer on the second gate electrode and overlapping the second gate electrode, and second source and drain electrodes the second semiconductor layer, and where the power source line and the first gate electrode are at a same layer.

Abstract: A thin film transistor is provided. A thin film transistor according to an exemplary embodiment of the present invention includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a semiconductor layer disposed on the substrate and including at least a portion overlapping the gate electrode; a gate insulating layer disposed between the gate line and the semiconductor layer; and a source electrode and a drain electrode disposed on the substrate and facing each other over a channel region of the semiconductor layer. The gate insulating layer includes a first region and a second region, the first region corresponds to the channel region of the semiconductor layer, the first region is made of a first material, the second region is made of a second material, and the first material and the second material have different atomic number ratios of carbon and silicon.

Abstract: The present invention provides a thin film transistor using an oxide semiconductor as a channel, controlling threshold voltage to a positive direction, and realizing improved reliability. The thin film transistor includes: a gate electrode; a pair of source/drain electrodes; an oxide semiconductor layer provided between the gate electrode and the pair of source/drain electrodes and forming a channel; a first insulating film as a gate insulating film provided on the gate electrode side of the oxide semiconductor layer; and a second insulating film provided on the pair of source/drain electrodes side of the oxide semiconductor layer. The first insulating film and/or the second insulating film contain/contains fluorine.

Abstract: Provided is a method of manufacturing an oxide semiconductor thin film transistor using a transparent oxide semiconductor as a material for a channel. The method of manufacturing the oxide semiconductor thin film transistor includes forming a passivation layer on a channel layer and performing an annealing process for one hour or more at a temperature of about 100° C. or above.

Abstract: Provided is a polysilicon thin film transistor having a trench type bottom gate structure using copper and a method of making the same. The polysilicon thin film transistor includes: a transparent insulation substrate; a seed pattern that is formed in a pattern corresponding to that of a gate electrode on the transparent insulation substrate, and that is used to form the gate electrode; a trench type guide portion having a trench type contact window in which an upper portion of the seed pattern is exposed; the gate electrode that is formed by electrodepositing copper on a trench of the exposed seed pattern; a gate insulation film formed on the upper portions of the gate electrode and the trench type guide portion, respectively; and a polysilicon layer in which a channel region, a source region and a drain region are formed on the upper portion of the gate insulation film.

Abstract: A thin film transistor (TFT) includes a gate electrode, a gate insulating layer, a first protective pattern, a second protective pattern, a source electrode, a drain electrode, a semiconductor channel layer, and a passivation layer. The first protective pattern and the second protective pattern are disposed on the gate insulating layer above the gate electrode. The source electrode is disposed on the gate insulating layer and the first protective pattern. The drain electrode is disposed on the gate insulating layer and the second protective pattern. The semiconductor channel layer is disposed on the gate insulating layer, the source electrode, and the drain electrode. In an extending direction from the source electrode to the drain electrode, a length of the first protective pattern is shorter than that of the source electrode, and a length of the second protective pattern is shorter than that of the drain electrode.

Abstract: A method of manufacturing a thin-film transistor array includes: forming a gate insulating layer on gate electrodes; forming an amorphous silicon layer on the gate insulating layer; generating a crystalline silicon layer by crystallizing the amorphous silicon layer; and forming source electrodes and drain electrodes. The thicknesses of the gate insulating layer on the gate electrode is within a range in which there is a positive correlation between light absorbances of the amorphous silicon layer above the gate electrodes for the laser light and equivalent oxide thicknesses of the gate insulating layer on the gate electrodes. The thicknesses of the amorphous silicon layer above the gate electrodes is within a range in which variation of the light absorbances according to variation of the thicknesses of the amorphous silicon layer is within a predetermined range from a first standard.

Abstract: To provide a semiconductor device including an oxide semiconductor, which has stable electric characteristics and has high reliability. To provide a method for manufacturing the semiconductor device. The semiconductor device includes a gate electrode, a gate insulating film formed over the gate electrode, an oxide semiconductor film formed over the gate insulating film, a source electrode and a drain electrode formed over the oxide semiconductor film, and a protective film. The protective film includes a metal oxide film, and the metal oxide film has a film density of higher than or equal to 3.2 g/cm3.

Abstract: Provided a display device including a thin film transistor. The thin film transistor includes a gate electrode, a gate insulating layer which covers the gate electrode, an oxide semiconductor film above the gate insulating layer, a source electrode and a drain electrode which are respectively provided in contact with a first region and a second region, which are provided in the upper surface of the oxide semiconductor film, and a channel protective film which is provided in contact with a third region between the first region and the second region. In plan view, a region of the oxide semiconductor film, which overlaps with the gate electrode, is smaller than the third region, and a portion of the oxide semiconductor film except for a portion which overlaps with the gate electrode has a resistance lower than the portion.

Abstract: This disclosure provides systems, methods and apparatus for fabricating thin film transistor devices. In one aspect, a substrate including a silicon layer on the substrate surface is provided. A metal layer is formed on the silicon layer. A first dielectric layer is formed on the metal layer and exposed regions of the substrate surface. The metal layer and the silicon layer are treated, and the metal layer reacts with the silicon layer to form a silicide layer and a gap between the silicide layer and the dielectric layer. An amorphous silicon layer is formed on the first dielectric layer. The amorphous silicon layer is heated and cooled. The amorphous silicon layer overlying the substrate surface cools at a faster rate than the amorphous silicon layer overlying the gap.

Abstract: A method of producing a transistor includes providing a substrate including in order a first electrically conductive material layer and a second electrically conductive material layer. The first electrically conductive material layer has a thickness. A resist material layer is deposited over the second electrically conductive material layer. The resist material layer is patterned to expose a portion of the second electrically conductive material layer. Some of the second electrically conductive material layer is removed to expose a portion of the first electrically conductive material layer. The second electrically conductive material layer is caused to overhang the first electrically conductive material layer by removing some of the first electrically conductive material layer.

Abstract: Disclosed are a transistor including a gate insulation layer and an organic passivation layer of a polymer thin film, and a fabrication method thereof. The transistor comprises a substrate, a gate electrode formed on the substrate, a gate insulation layer including a polymethacrylic acid thin film, formed on the gate electrode and the substrate, a channel layer formed on the gate insulation layer, source electrode and drain electrode formed on the channel layer so as to expose at least a part of the channel layer, and an organic passivation layer including a polymethacrylic acid thin film, formed on the source electrode, drain electrode and the partially exposed channel layer.

Abstract: A method of forming a display device including source/drain electrodes on a substrate, a pixel electrode, an insulating partition wall layer, a channel-region semiconductor layer. Source/drain electrodes of a thin-film transistor are formed on the substrate, while a pixel electrode is connected to the source/drain electrodes. The insulating partition wall layer is formed on the substrate, where the partition wall layer has a first opening extending to between the source electrode and the drain electrode. Furthermore, a channel-region semiconductor layer is formed by depositing a semiconductor layer over the partition wall layer. The channel-region semiconductor layer is on the bottom of the first opening to be separate from a upper part of the partition wall layer.