Abstract: A method for manufacturing a thin film transistor having high electric characteristics with high productivity. In the method for forming a channel region of a dual-gate thin film transistor including a first gate electrode and a second gate electrode which faces the first gate electrode with the channel region provided therebetween, a first microcrystalline semiconductor film is formed under a first condition for forming a microcrystalline semiconductor film in which a space between crystal grains is filled with an amorphous semiconductor, and a second microcrystalline semiconductor film is formed over the first microcrystalline semiconductor film under a second condition for promoting crystal growth.

Abstract: A thin film transistor substrate includes a substrate, a gate electrode on the substrate, an active layer on or below the gate electrode (the active layer at least partially overlapping the gate electrode) including a first active region and a second active region, the first active region and the second active region facing each other and extending beyond the gate electrode, a source electrode electrically connected to the first active region and a drain electrode electrically connected to the second active region, wherein the active layer includes a recess region which is at least partially recessed from a surface of the active layer facing the gate electrode, and the recess region includes a portion extending between the first active region and the second active region.

Abstract: A thin film transistor (TFT) that includes a gate, an oxide semiconductor layer, a gate insulator, a source, and a drain is provided. The gate insulator is located between the oxide semiconductor layer and the gate. The source and the drain are in contact with different portions of the oxide semiconductor layer. Each of the source and the drain has a ladder-shaped sidewall that is partially covered by the oxide semiconductor layer. A method for fabricating the above-mentioned TFT is also provided.

Abstract: With a TFT using an oxide semiconductor film, there is such an issue that oxygen deficit is generated in a surface region of the oxide semiconductor film after performing plasma etching of a source/drain electrode, thereby increasing the off-current. Provided is a TFT which includes: a gate electrode on an insulating substrate; a gate insulating film on the gate electrode; an oxide semiconductor film containing indium on the gate insulating film; and a source/drain electrode on the oxide semiconductor film. Further, the peak position derived from an indium 3d orbital in the XPS spectrum of a surface layer in a part of the oxide semiconductor film where the source/drain electrode is not superimposed is shifted towards a high energy side than the peak position derived from the indium 3d orbital in the XPS spectrum of an oxide semiconductor region existing in a lower part of the surface layer.

Abstract: The present invention provides a liquid crystal display device having a large holding capacitance in the inside of a pixel. A liquid crystal display device includes a first substrate, a second substrate arranged to face the first substrate in an opposed manner, and liquid crystal sandwiched between the first substrate and the second substrate. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode thereof connected to the video signal line and a second electrode thereof connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film formed above the first silicon nitride film, a capacitance electrode formed above the organic insulation film, and a second silicon nitride film formed above the capacitance electrode and below the pixel electrode. The second silicon nitride film is a film which is formed at a temperature lower than a forming temperature of the first silicon nitride film.

Abstract: In a manufacturing method for thin film transistors, the following procedure is taken: a sacrifice layer comprised of a metal oxide semiconductor is formed over a conductive layer comprised of a metal oxide semiconductor; a metal film is formed over the sacrifice layer; the metal film is processed by dry etching; and the portion of the sacrifice layer exposed by this dry etching is subjected to wet etching.

Abstract: A thin-film transistor device which is a bottom-gate thin-film transistor device, includes: a gate electrode formed above a substrate; a gate insulating film formed above the gate electrode; a crystalline silicon thin film formed above the gate insulating film and having a channel region; an amorphous silicon thin film formed above the crystalline silicon thin film including the channel region; and a source electrode and a drain electrode formed above the amorphous silicon thin film, in which an optical bandgap of the amorphous silicon thin film and an off-state current of the thin-film transistor device have a positive correlation.

Abstract: A thin-film semiconductor device according to the present disclosure includes: a substrate; a gate electrode formed above the substrate; a gate insulating film formed on the gate electrode; a channel layer that is formed of a polycrystalline semiconductor layer on the gate insulating film; an amorphous semiconductor layer formed on the channel layer and having a projecting shape in a surface; and a source electrode and a drain electrode that are formed above the amorphous semiconductor layer, and a first portion included in the amorphous semiconductor layer and located closer to the channel layer has a resistivity lower than a resistivity of a second portion included in the amorphous semiconductor layer and located closer to the source and drain electrodes.

Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle ?1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle ?2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

Abstract: A method of manufacturing a thin film transistor includes sequentially forming a gate and at least one insulation layer on a substrate, forming a source electrode and a drain electrode on the at least one insulation layer, and forming a channel layer formed of a semiconductor on a part of the source electrode and the drain electrode, wherein the gate, the source electrode, and the drain electrode are formed by using a hybrid inkjet printing apparatus.

Abstract: It is an object to provide a method for manufacturing a thin film transistor, in which the number of masks to be used is small. A thin film transistor is manufactured as follows: a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked; a resist mask having a recessed portion is formed thereover with the use of a multi-tone mask; a thin-film stack body is formed with first etching; a gate electrode layer is formed with second etching in which an etched first conductive film is side-etched; and then a source electrode and a drain electrode and the like are formed. A crystalline semiconductor film is used for the semiconductor film.

Abstract: A thin film transistor having a channel region including a nanoconductor layer. The nanoconductor layer can be a dispersed monolayer of nanotubes or nanowires formed of carbon. The thin film transistor generally includes a gate terminal insulated by a dielectric layer. The nanoconductor layer is placed on the dielectric layer and a layer of semiconductor material is developed over the nanoconductor layer to form the channel region of the thin film transistor. A drain terminal and a source terminal are then formed on the semiconductor layer. At low field effect levels, the operation of the thin film transistor is dominated by the semiconductor layer, which provides good leakage current performance. At high field effect levels, the charge transfer characteristics of the channel region are enhanced by the nanoconductor layer such that the effective mobility of the thin film transistor is enhanced.

Abstract: To improve the reliability of contact with an anisotropic conductive film in a semiconductor device such as a liquid crystal display panel, a terminal portion of a connecting wiring on an active matrix substrate is electrically connected to an FPC by an anisotropic conductive film. The connecting wiring is made of a lamination film of a metallic film and a transparent conductive film. In the connecting portion with the anisotropic conductive film, a side surface of the connecting wiring is covered with a protecting film made of an insulating material, thereby exposure to air of the metallic film can be avoided.

Abstract: A thin film transistor array substrate is disclosed. The thin film transistor array substrate includes: gate lines and data lines formed to cross each other in the center of a gate insulation film on a substrate and to define pixel regions; a thin film transistor formed at each intersection of the gate and data lines; a passivation film formed on the thin film transistors; a pixel electrode formed on each of the pixel regions and connected to the thin film transistor through the passivation film; a gate pad connected to each of the gate lines through a gate linker; and a data pad connected to each of the data lines through a data linker. The data pad is formed of a gate pattern, and the data line is formed of a data pattern. The data linker is configured to connect the data pad formed of the gate pattern with the data line formed of the data pattern using a connection wiring.

Abstract: A display substrate includes a gate line, a gate insulation layer, a data line, a switching element, a protection insulation layer, a gate pad portion and a data pad portion. The gate insulation layer is disposed on the gate line. The switching element is connected to the gate line and the data line. The protection insulation layer is disposed on the switching element. The gate pad portion includes a first gate pad electrode which makes contact with an end portion of the gate line through a first hole formed through the gate insulation layer, and a second gate pad electrode which makes contact with the first gate pad electrode through a second hole formed through the protection insulation layer. The data pad portion includes a data pad electrode which makes contact with an end portion of the data line through a third hole formed through the protection insulation layer.

Abstract: It is an object to reduce characteristic variation among transistors and reduce contact resistance between an oxide semiconductor layer and a source electrode layer and a drain electrode layer, in a transistor where the oxide semiconductor layer is used as a channel layer. In a transistor where an oxide semiconductor is used as a channel layer, at least an amorphous structure is included in a region of an oxide semiconductor layer between a source electrode layer and a drain electrode layer, where a channel is to be formed, and a crystal structure is included in a region of the oxide semiconductor layer which is electrically connected to an external portion such as the source electrode layer and the drain electrode layer.

Abstract: The present invention provides methods for manufacturing a thin film transistor (TFT) array substrate and a display panel. The method for manufacturing the TFT array substrate comprises the following steps: forming a plurality of gate electrodes, a gate insulating layer, a semiconductor layer, an ohmic contact layer, an electrode layer and a photo-resist layer on a transparent substrate in sequence; using a multi tone mask to pattern the photo-resist layer; forming a plurality of source electrodes and a plurality of drain electrodes at both sides of the channels, respectively; heating the photo-resist layer; etching the semiconductor layer; removing the photo-resist layer; forming a passivation layer on the channels, the source electrodes and the drain electrodes; and forming a pixel electrode layer on the passivation layer. The present invention can reduce an amount of the required masks in the fabrication process, and only one wet etching is required to etch the metal material on the TFT array substrate.

Abstract: A method for manufacturing a thin film transistor includes the step of forming a gate electrode (11aa) on an insulating substrate, the step of forming a gate insulating layer (12) to cover the gate electrode (11aa), and thereafter, forming an oxide semiconductor layer (13a) on the gate insulating layer (12), the step of forming a source electrode (16aa) and a drain electrode (16b) on the oxide semiconductor layer (13a) by dry etching, with a channel region (C) of the oxide semiconductor layer being exposed, and the step of supplying oxygen radicals to a channel region of the oxide semiconductor layer.

Abstract: In one aspect of this invention, a pixel structure includes a scan line formed on a substrate and a data line formed over the substrate defining a pixel area, a switch formed inside the pixel area on the substrate, a shielding electrode having a first portion and a second portion extending from the first portion, and formed over the scan line, the data line and the switch, where the first portion is overlapped with the switch and the second portion is overlapped with the data line, and a pixel electrode having a first portion and a second portion extending from the first portion, and formed over the shielding electrode in the pixel area, where the first portion is overlapped with the first portion of the shielding electrode so as to define a storage capacitor therebetween and the second portion has no overlapping with the second portion of the shielding electrode.

Abstract: A thin film transistor may include a passivation layer formed of a metal-containing conductive material. The thin film transistor includes: a gate electrode; a gate insulating layer positioned on the gate electrode; a channel layer positioned on the gate insulating layer; a source electrode and a drain electrode which are in contact with the channel layer while being spaced apart from each other; and a passivation layer including a metal-containing conductive material and positioned on the channel layer while being spaced apart from each of the source electrode and the drain electrode. The passivation layer serves to prevent transmission of light, oxygen, water and/or impurities into the channel layer and to improve the electrical characteristics of the thin film transistor.

Abstract: A method for fabricating a pixel structure includes providing a substrate having a pixel area. A first metal layer, a gate insulator and a semiconductor layer are formed on the substrate and patterned by using a first half-tone mask or a gray-tone mask to form a transistor pattern, a lower capacitance pattern and a lower circuit pattern. Next, a dielectric layer and an electrode layer both covering the three patterns are sequentially formed and patterned to expose a part of the lower circuit pattern, a part of the lower capacitance pattern and a source/drain region of the transistor pattern. A second metal layer formed on the electrode layer and the electrode layer are patterned by using a second half-tone mask or the gray-tone mask to form an upper circuit pattern, a source/drain pattern and an upper capacitance pattern. A portion of the electrode layer constructs a pixel electrode.

Abstract: A thin film transistor (TFT) array substrate includes a TFT on a substrate, the TFT including an active layer, gate electrode, source electrode, drain electrode, first insulating layer between the active layer and the gate electrode, and second insulating layer between the gate electrode and the source and drain electrodes; a pixel electrode on the first insulating layer and the second insulating layer, the pixel electrode being connected to one of the source electrode and drain electrode; a capacitor including a lower electrode on a same layer as the gate electrode and an upper electrode including the same material as the pixel electrode; a third insulating layer directly between the second insulating layer and the pixel electrode and between the lower electrode and the upper electrode; and a fourth insulating layer covering the source electrode, the drain electrode, and the upper electrode, and exposing the pixel electrode.

Abstract: A thin film transistor and a method for manufacturing the same are provided. A top-gate thin film transistor is fabricated by a process using two gray-tone photomasks and a lift-off method. Therefore, the method can save cost of photomasks and processes comparing to a conventional fabrication method.

Abstract: In an organic light-emitting display device and a method of manufacturing the same, the display device may include: a thin-film transistor including an active layer, a gate electrode including a first electrode which includes nano-Ag on an insulating layer formed on the active layer and a second electrode on the first electrode, a source electrode, and a drain electrode; an organic light-emitting device including a pixel electrode electrically connected to the thin-film transistor and formed of the same layer as, and using the same material used to form, the first electrode, an intermediate layer including an emissive layer, and an opposite electrode covering the intermediate layer and facing the pixel electrode; and a pad electrode formed of the same layer as, and using the same material used to form, the first electrode in a pad area located outside of a light-emitting area.

Abstract: A display device including a display element and a thin-film transistor for controlling light emission from the display element. The thin-film transistor includes: a gate electrode formed on an insulating support substrate; a gate insulating film formed on the substrate so as to cover the gate electrode; a channel layer formed on the gate insulating film; a channel protective layer formed on the top surface of the channel layer; a pair of contact layers formed on the top surface of the channel protective layer and connected to the channel layer; and a source electrode and a drain electrode each connected to the pair of contact layers. The pair of contact layers has an interface contacting the side surface of the channel layer.

Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.

Abstract: There is provided a method of manufacturing a semiconductor device including: forming a gate electrode on a substrate ; forming a gate insulating layer of which a recessed portion is formed in a region in which a channel formation region is to be formed, on the substrate and the gate electrode; forming the channel formation region including an organic semiconductor material within the recessed portion based on a coating method; and forming source/drain electrodes on portions of the channel formation region from on the gate insulating layer.

Abstract: A TFT array substrate includes a semiconductive oxide layer disposed on an insulating substrate and including a channel portion, a gate electrode overlapping the semiconductive oxide layer, a gate insulating layer interposed between the semiconductive oxide layer and the gate electrode, and a passivation layer disposed on the semiconductive oxide layer and the gate electrode. At least one of the gate insulating layer and the passivation layer includes an oxynitride layer, and the oxynitride layer has a higher concentration of oxygen than that of nitrogen in a location of the oxynitride layer closer to the semiconductive oxide layer.

Abstract: A thin film transistor substrate including a thin film transistor having a drain electrode with an electrode portion, which overlaps with a semiconductor layer, and an extended portion, which extends from the electrode portion and has a portion overlapping with a storage electrode or storage electrode line. A passivation layer is arranged on the drain electrode, and it has a contact hole that partially exposes the extended portion of the drain electrode without exposing a step in the extended portion caused by the storage electrode or storage electrode line. A pixel electrode is arranged on the passivation layer and is electrically connected with the extended portion of the drain electrode through the contact hole.

Abstract: The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.

Abstract: The thin film transistor manufacturing apparatus comprises a surface modification layer forming means, which forms a surface modification layer on a substrate, an illuminating part, which irradiates light that includes ultraviolet rays, a mask, on which the patterns of the source electrode and the drain electrode are drawn, a projection optical system, which illuminates a mask using light from the illuminating part and projects the pattern of the mask to the substrate as a pattern image, and a coating part, which coats a fluid electrode material to a region in which the surface modification layer has been modified by projection of the pattern image in order to form the source electrode and the drain electrode.

Abstract: The object is to suppress deterioration in electrical characteristics in a semiconductor device comprising a transistor including an oxide semiconductor layer. In a transistor in which a channel layer is formed using an oxide semiconductor, a p-type silicon layer is provided in contact with a surface of the oxide semiconductor layer. Further, the p-type silicon layer is provided in contact with at least a region of the oxide semiconductor layer, in which a channel is formed, and a source electrode layer and a drain electrode layer are provided in contact with regions of the oxide semiconductor layer, over which the p-type silicon layer is not provided.

Abstract: A textured thin film transistor is comprised of an insulator sandwiched between a textured gate electrode and a semi-conductor. A source electrode and drain electrode are fabricated on a surface of the semi-conductor. The textured gate electrode is fabricated such that a surface is modified in its texture and/or geometry, such modifications affecting the transistor current.

Abstract: A thin film transistor including a gate electrode, a semiconductor layer, a gate insulating layer, a source electrode, a drain electrode and a graphene pattern. The semiconductor layer overlaps with the gate electrode. The gate insulating layer is disposed between the gate electrode and the semiconductor layer. The source electrode overlaps with the semiconductor layer. The drain electrode overlaps with the semiconductor layer. The drain electrode is spaced apart from the source electrode. The graphene pattern is disposed between the semiconductor layer and at least one of the source electrode and the drain electrode.

Abstract: A thin-film transistor used for a display device includes a gate electrode formed on an insulating substrate; a gate insulating film formed on the substrate so as to cover the gate electrode; a semiconductor layer composed of first semiconductor layer and second semiconductor layer formed on the gate insulating film; an ohmic contact layer formed on the semiconductor layer; and a source electrode and a drain electrode formed on the ohmic contact layer so as to be spaced from each other. The transistor further includes an etching stopper made of spin-on glass (SOG) on a channel-forming region of the semiconductor layer.

Abstract: A method of manufacturing an array substrate for a fringe field switching mode liquid crystal display includes: forming an auxiliary insulating layer having a first thickness; forming first and second photoresist patterns on the auxiliary insulating layer; performing an ashing to remove the second photoresist pattern and expose the auxiliary insulating layer therebelow; performing a dry etching to remove the auxiliary insulating layer not covered by the first photoresist pattern and expose a first passivation layer and to form an insulating pattern below the first photoresist pattern, the insulating pattern and the first photoresist pattern forming an undercut shape; forming a transparent conductive material layer having a fourth thickness less than the first thickness; and performing a lift-off process to remove the first photoresist pattern and the transparent conductive material layer thereon together and form a pixel electrode.

Abstract: An OLED device includes a thin film transistor including an active layer, a gate bottom electrode, a gate top electrode, an insulating layer covering the gate electrode, and a source electrode and a drain electrode on the insulating layer contacting the active layer; an organic light-emitting device electrically connected to the thin film transistor and including a sequentially stacked pixel electrode, on the same layer as the gate bottom electrode, emissive layer, and, opposite electrode, a pad bottom electrode on the same layer as the gate bottom electrode and a pad top electrode pattern on the same layer as the gate top electrode, the pad top electrode pattern including openings exposing the pad bottom electrode, and an insulation pattern covering the upper surface of the pad top electrode pattern on the same layer as the insulating layer, on an upper surface of the pad bottom electrode.

Abstract: An organic light-emitting display device including a TFT comprising an active layer, a gate electrode comprising a lower gate electrode and an upper gate electrode, and source and drain electrodes insulated from the gate electrode and contacting the active layer; an organic light-emitting device electrically connected to the TFT and comprising a pixel electrode formed in the same layer as where the lower gate electrode is formed; and a pad electrode electrically coupled to the TFT or the organic light emitting device and comprising a first pad electrode formed in the same layer as in which the lower gate electrode is formed, a second pad electrode formed in the same layer as in which the upper gate electrode is formed, and a third pad electrode comprising a transparent conductive oxide, the first, second, and third pad electrodes being sequentially stacked.

Abstract: A substrate; a gate electrode formed above the substrate; a gate insulating film formed above the gate electrode; a crystalline silicon semiconductor layer formed above the gate insulating film; an amorphous silicon semiconductor layer formed above the crystalline silicon semiconductor layer; an organic protective film made of an organic material and formed above the amorphous silicon semiconductor layer; and a source electrode and a drain electrode formed above the amorphous silicon semiconductor layer interposing the organic protective film are included, and a charge density of the negative carriers in the amorphous silicon semiconductor layer is at least 3×1011 cm?2.

Abstract: A thin film transistor array substrate having a high charge mobility and that can raise a threshold voltage, and a method of fabricating the thin film transistor array substrate are provided. The thin film transistor array substrate includes: an insulating substrate; a gate electrode formed on the insulating substrate; an oxide semiconductor layer comprising a lower oxide layer formed on the gate electrode and an upper oxide layer formed on the lower oxide layer, such that the oxygen concentration of the upper oxide layer is higher than the oxygen concentration of the lower oxide layer; and a source electrode and a drain electrode formed on the oxide semiconductor layer and separated from each other.

Abstract: A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and a method for manufacturing the thin film transistor and the display device in a high yield are provided. In the thin film transistor, a gate electrode, a gate insulating film, crystal grains that mainly contain silicon and are provided for a surface of the gate insulating film, a semiconductor film that mainly contains germanium and covers the crystal grains and the gate insulating film, and a buffer layer in contact with the semiconductor film that mainly contains germanium overlap with one another. Further, the display device has the thin film transistor.

Abstract: A method for manufacturing a flexible semiconductor device includes (i) forming an insulating film on the upper surface of metal foil, (ii) forming an extraction electrode pattern on the upper surface of the metal foil, (iii) forming a semiconductor layer on the insulating film such that the semiconductor layer is in contact with the extraction electrode pattern, (iv) forming a sealing resin layer on the upper surface of the metal foil such that the sealing resin layer covers the semiconductor layer and the extraction electrode pattern, and (v) forming electrodes by etching the metal foil, the metal foil being used as a support for the insulating film, the extraction electrode pattern, the semiconductor layer, and the sealing resin layer formed in (i) to (iv) and used as a constituent material for the electrodes in (v). The metal foil need not be stripped, and a high-temperature process can be used.

Abstract: An organic EL device includes a base layer including a substrate, a partitioning portion disposed on the base layer and defining first and second film-formation regions adjacent to each other, a first organic EL element disposed on the base layer at a position overlapping the first film-formation region in plan view, a second organic EL element disposed on the base layer at a position overlapping the second film-formation region in plan view, a first drive circuit section disposed in the base layer to control driving of the first organic EL element, and a second drive circuit section disposed in the base layer to control driving of the second organic EL element. At least part of the first drive circuit section and at least part of the second drive circuit section overlap the first film-formation region in plan view.

Abstract: A thin film transistor substrate includes a base substrate; a first insulating layer disposed on the base electrode; source and drain electrodes disposed on the first insulating layer to be spaced apart from each other; a semiconductor layer disposed on the source electrode, the drain electrode, and the first insulating layer; a second insulating layer disposed on the semiconductor layer; and a gate electrode disposed on the second insulating layer to overlap with the source electrode and the drain electrode.

Abstract: Transistor devices having nanoscale material-based channels (e.g., carbon nanotube or graphene channels) and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.

Abstract: The number of photomasks is reduced in a method for manufacturing a liquid crystal display device which operates in a fringe field switching mode, whereby a manufacturing process is simplified and manufacturing cost is reduced. A first transparent conductive film and a first metal film are sequentially stacked over a light-transmitting insulating substrate; the first transparent conductive film and the first metal film are shaped using a multi-tone mask which is a first photomask; an insulating film, a first semiconductor film, a second semiconductor film, and a second metal film are sequentially stacked; the second metal film and the second semiconductor film are shaped using a multi-tone mask which is a second photomask; a protective film is formed; the protective film is shaped using a third photomask; a second transparent conductive film is formed; and the second transparent conductive film is shaped using a fourth photomask.

Abstract: To provide a method for manufacturing a transistor which has little variation in characteristics and favorable electric characteristics. A gate insulating film is formed over a gate electrode; a semiconductor layer including a microcrystalline semiconductor is formed over the gate insulating film; an impurity semiconductor layer is formed over the semiconductor layer; a mask is formed over the impurity semiconductor layer, and then the semiconductor layer and the impurity semiconductor layer are etched with use of the mask to form a semiconductor stacked body; the mask is removed and then the semiconductor stacked body is exposed to plasma generated in an atmosphere containing a rare gas to form a barrier region on a side surface of the semiconductor stacked body; and a wiring over the impurity semiconductor layer of the semiconductor stacked body is formed.

Abstract: The roughness and structural height of printed metal lines is used to pin a fluid. This fluid deposits a top contact material which is connected to the bottom printed contacts through pinholes in the hydrophobic polymer layer. This results in a sandwich-like contact structure achieved in a self-aligned deposition process and having improved source-drain contact for all-additive printed circuits. In one form, the present technique is used for thin film transistor applications, but it may be applied to electrodes in general.

Abstract: To suppress deterioration in electrical characteristics in a transistor including an oxide semiconductor layer or a semiconductor device including the transistor. In a transistor in which a channel layer is formed using an oxide semiconductor, a silicon layer is provided in contact with a surface of the oxide semiconductor layer. Further, the silicon layer is provided in contact with at least a region of the oxide semiconductor layer, in which a channel is formed, and a source electrode layer and a drain electrode layer are provided in contact with regions of the oxide semiconductor layer, over which the silicon layer is not provided.

Abstract: A liquid crystal display device includes a substrate having a display region and a non-display region. In the display region, the gate line and a data line cross to define a pixel region and a thin film transistor is disposed at the crossing portion of the gate and data lines. The thin film transistor includes a gate electrode and source and drain electrodes. A peripheral line having a plurality of openings is disposed in the non-display region. The openings are slits, rectangles, circles, or triangles. The openings relieve plasma during dry-etching of the peripheral line. A pixel electrode is connected to the drain electrode in the pixel region.