Abstract: Preparing a substrate; forming a plurality of gate electrodes above the substrate; forming a gate insulating layer above the gate electrodes; forming an amorphous silicon layer above the gate insulating layer; forming crystalline silicon layer regions by irradiating the amorphous silicon layer in regions above the gate electrodes with a laser beam having a wavelength from 473 nm to 561 nm so as to crystallize the amorphous silicon layer in the regions above the gate electrodes, and forming an amorphous silicon layer region in a region other than the regions above the gate electrodes; and forming source electrodes and drain electrodes above the crystalline silicon layer regions are included, and a thickness of the gate insulating layer and a thickness of the amorphous silicon layer satisfy predetermined expressions.

Abstract: A thin film transistor substrate includes a substrate; a gate electrode on the substrate; a semiconductor pattern on the gate electrode; a source electrode on the semiconductor pattern; a drain electrode on the semiconductor pattern and spaced apart from the source electrode; a pixel electrode connected to the drain electrode; and a common electrode partially overlapped with the pixel electrode. The semiconductor pattern is in a same layer of the thin film transistor substrate as the pixel electrode and has an electrical property different from an electrical property of the pixel electrode.

Abstract: A mask includes: a substrate that includes a central area and a peripheral area disposed around the central area; and lenses disposed in rows and columns, in the central area and the peripheral area. The lenses of opposing sides of the peripheral area may be disposed in different rows or columns. For a given amount of input light, the lenses of the peripheral area may focus less light on a substrate than the lenses of the central area. The mask may be disposed over the substrate in different positions, and then the substrate may be irradiated through the mask, while the mask is in each of the positions. The peripheral portion of the mask may be disposed over the same area of the substrate, while the mask is in different ones of the positions.

Abstract: A TFT includes a supporting substrate, a gate electrode formed on the supporting substrate, a gate insulation film formed on the substrate so as to cover the gate electrode, a first semiconductor layer formed across from the gate electrode with respect to the gate insulation film, a second semiconductor layer formed on the first semiconductor layer, and having a first thickness and a second thickness which is greater than the first thickness, an ohmic contact layer formed on the second semiconductor layer, and a source electrode and a drain electrode formed on the ohmic contact layer, spacing apart with each other.

Abstract: A method of fabricating a thin-film transistor (TFT) substrate includes forming a gate electrode on a substrate; forming an insulating film on the gate electrode; forming an amorphous semiconductor pattern on the insulating film; and forming a source electrode separated from a drain electrode on the amorphous semiconductor pattern; forming a light-concentrating layer, which includes a protrusion, on the amorphous semiconductor pattern, the source electrode, and the drain electrode; and crystallizing at least part of the amorphous semiconductor pattern by irradiating light to the protrusion of the light-concentrating layer.

Abstract: A method for manufacturing a flexible semiconductor device includes (i) forming an insulating film on the upper surface of metal foil, (ii) forming an extraction electrode pattern on the upper surface of the metal foil, (iii) forming a semiconductor layer on the insulating film such that the semiconductor layer is in contact with the extraction electrode pattern, (iv) forming a sealing resin layer on the upper surface of the metal foil such that the sealing resin layer covers the semiconductor layer and the extraction electrode pattern, and (v) forming electrodes by etching the metal foil, the metal foil being used as a support for the insulating film, the extraction electrode pattern, the semiconductor layer, and the sealing resin layer formed in (i) to (iv) and used as a constituent material for the electrodes in (v). The metal foil need not be stripped, and a high-temperature process can be used.

Abstract: Embodiments of the present invention disclose an array substrate and a manufacturing method thereof. The method comprises forming a patterned active layer on a gate insulating layer, the active layer covering a part of the gate insulating layer; forming a source/drain electrode material layer on the active layer and the gate insulating layer; forming a patterned insulating layer on the source/drain electrode material layer; conducting an etching process by using the insulating layer as a mask, so as to etch the source/drain electrode material layer to form a source electrode and a drain electrode, etch a part of the insulating layer to form a via hole in the insulating layer over the drain electrode, and etch a part of the active layer between the source electrode and the drain electrode to form a channel.

Abstract: In case that a conventional TFT is formed to have an inversely staggered type, a resist mask is required to be formed by an exposing, developing, and droplet discharging in forming an island-like semiconductor region. It resulted in the increase in the number of processes and the number of materials. According to the present invention, a process can be simplified since after forming a source region and a drain region, a portion serving as a channel region is covered by an insulating film serving as a channel protecting film to form an island-like semiconductor film, and so a semiconductor element can be manufactured by using only metal mask without using a resist mask.

Abstract: Processes for metal fill in replacement metal gate integration schemes and resultant devices are provided herein. The method includes forming a dummy gate on a semiconductor substrate. The dummy gate includes forming a metal layer between a first material and a second material. The method further includes partially removing the dummy gate to form an opening bounded by a spacer material. The method further includes forming a recess in the spacer material to widen a portion of the opening. The method further includes removing a remaining portion of the dummy gate through the opening to form a trench having the recess forming an upper portion thereof. The method further includes filling the trench and the recess with a replacement metal gate stack.

Abstract: An array substrate for a display device and its fabrication method are disclosed. The array substrate for a display device includes: a gate wiring and a gate electrode connected to the wiring formed on a substrate; a gate insulating layer formed on the gate electrode; an active layer and a barrier metal layer stacked with the gate insulating layer interposed therebetween on the gate electrode; a data wiring formed on the barrier metal layer and source and electrodes connected to the data wiring; a passivation film formed on the source and drain electrodes and the data wiring and having a contact hole exposing a portion of the drain electrode, the barrier metal layer and the active layer; and a pixel electrode formed on the passivation film and being in contact with the drain electrode and the barrier metal layer including the active layer.

Abstract: A method for crystallizing a thin film A gate insulating film formed on a substrate so as to cover a gate electrode. A light absorption layer is formed thereon through a buffer layer. Energy lines Lh are applied to the light absorption layer from a continuous-wave laser such as a semiconductor laser. This anneals only a surface side of the light absorption layer Lh and produces a crystalline silicon film obtained by crystallizing the amorphous silicon film using heat generated by thermal conversion of the energy lines Lh at the light absorption layer and heat of the annealing reaction.

Abstract: The invention provides a display device and a method for manufacturing thereof by increasing a material efficiently as well as simplifying steps. Also, the invention provides a technique for forming a pattern such as a wiring, that is used for forming a display device, to have a predetermined shape with an excellent controllability. The method for manufacturing a display device includes the steps of: forming a lyophobic region; selectively irradiating laser beam in the lyophobic region to form a lyophilic region; selectively discharging a composition, that contains a conductive material, in the lyophilic region to form a gate electrode layer; forming a gate insulating layer and a semiconductor layer over the gate electrode layer; discharging a composition containing a conductive material over the semiconductor layer to form a source electrode layer and a drain electrode layer; and forming a pixel electrode layer on the source or drain electrode layer.

Abstract: A method for manufacturing a thin film transistor includes forming a semiconductor layer, a wiring layer and a patterned mask layer in sequence on a substrate on which a gate electrode and a gate insulating layer are formed; patterning the wiring layer and the semiconductor layer based on the patterned mask layer while irradiating external light; removing at least a part of the mask layer; forming a channel portion by etching the wiring layer while controlling irradiation of the external light. Further, the method for manufacturing the thin film transistor can obtain an improved structure by forming the semiconductor layer made of an oxide which reacts to external light irradiated thereto, thus capable of adjusting a selectivity between the semiconductor layer and the wiring layer.

Abstract: A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and methods for manufacturing the thin film transistor and the display device are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed over the gate insulating film, a pair of buffer layers formed over the microcrystalline semiconductor film, a pair of semiconductor films to which an impurity element imparting one conductivity type is added and which are formed over the pair of buffer layers, and wirings formed over the pair of semiconductor films to which the impurity element imparting one conductivity type is added. A part of the gate insulating film or the entire gate insulating film, and/or a part of the microcrystalline semiconductor or the entire microcrystalline semiconductor includes the impurity element which serves as a donor.

Abstract: A top gate and bottom gate thin film transistor (TFT) are provided with an associated fabrication method. The TFT is fabricated from a substrate, and an active metal oxide semiconductor (MOS) layer overlying the substrate. Source/drain (S/D) regions are formed in contact with the active MOS layer. A channel region is interposed between the S/D regions. The TFT includes a gate electrode, and a gate dielectric interposed between the channel region and the gate electrode. The active MOS layer may be ZnOx, InOx, GaOx, SnOx, or combinations of the above-mentioned materials. The active MOS layer also includes a primary dopant such as H, K, Sc, La, Mo, Bi, Ce, Pr, Nd, Sm, Dy, or combinations of the above-mentioned dopants. The active MOS layer may also include a secondary dopant.

Abstract: A method of manufacturing a wire may include forming a wire pattern, which at least includes a first conductive layer, a second conductive layer, and a third conductive layer arranged in the order stated on a substrate. At least the second conductive layer may have higher etch selectivity than the first and third conductive layers. Side holes may be formed by removing portions of the second conductive layer at ends of the wire pattern, and fine wires may be formed by injecting a masking material into the side holes and patterning the wire pattern by using the masking material as a mask.

Abstract: A method of depositing elongated nanostructures that allows accurate positioning and orientation is described. The method involves printing or otherwise depositing elongated nanostructures in a carrier solution. The deposited droplets are also elongated, usually by patterning the surface upon which the droplets are deposited. As the droplet evaporates, the fluid flow within the droplets is controlled such that the nanostructures are deposited either at the edge of the elongated droplet or the center of the elongated droplet. The described deposition technique has particular application in forming the active region of a transistor.

Abstract: An embodiment of the invention provides a manufacturing method of a thin film transistor including: providing a substrate; sequentially forming a gate electrode, a gate insulating layer covering the gate electrode, and an active layer on the substrate; forming a conductive layer on the active layer and including a source electrode, a drain electrode, and a separating portion connecting therebetween; forming a first photoresist layer on the conductive layer and covering the source electrode and the drain electrode and exposing the separating portion; oxidizing the separating portion into an insulating metal oxide layer so as to electrically insulate the source electrode from the drain electrode; and removing the first photoresist layer.

Abstract: A method for manufacturing a transistor with stable electric characteristics and little signal delay due to wiring resistance, used in a semiconductor device including an oxide semiconductor film. A semiconductor device including the transistor is provided. A high-performance display device including the transistor is provided.

Abstract: An embodiment of the invention provides a manufacturing method of a thin-film transistor includes: providing a substrate; sequentially forming a gate electrode, a gate insulating layer, and an active layer on the substrate; forming an insulating metal oxide layer covering the active layer, wherein the insulating metal oxide layer including a metal oxide of a first metal; forming a metal layer covering the active layer, wherein the metal layer includes a second metal; forming a source electrode and a drain electrode on the metal layer with a trench separating therebetween; removing the metal layer exposed by the trench; and performing an annealing process to the metal layer and the insulating metal oxide layer, such that the metal layer reacts with the insulating metal oxide layer overlapping the metal layer to form a conducting composite metal oxide layer including the first metal and the second metal.

Abstract: A method of planarizing a substrate includes forming a conductive pattern on a first surface of a base substrate, forming a positive photoresist layer on the base substrate and the conductive pattern, exposing the positive photoresist layer to light by irradiating a second surface of the base substrate opposite to the first surface with light, developing the positive photoresist layer to form a protruded portion on the conductive pattern, forming a planarizing layer on the base substrate and the protruded portion and eliminating the protruded portion.

Abstract: A method of fabricating a thin film transistor includes sequentially forming a first metal layer on a substrate and a second metal layer of copper on the first metal layer; performing a plasma process to form a copper nitride layer on the second metal layer; patterning the copper nitride layer, the second metal layer and the first metal layer to form a gate electrode; forming a first gate insulating layer of silicon nitride on the substrate including the gate electrode; forming a second gate insulating layer of silicon oxide on the first gate insulating layer; forming a semiconductor layer on the second gate insulating layer formed of an oxide semiconductor material; and forming a source electrode and a drain electrode on the semiconductor layer, the source electrode spaced apart from the drain electrode.

Abstract: A TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line crossing the gate line to define a pixel region; a drain electrode which is opposite to the source electrode with a channel in between; a semiconductor layer defining the channel between the source electrode and the drain electrode; a pixel electrode in the pixel region and connected to the drain electrode; a channel passivation layer on the channel of the semiconductor layer; a gate pad extending from the gate line, where a semiconductor pattern and a transparent conductive pattern are formed; a data pad connected to the data line, where the transparent conductive pattern is formed; and a gate insulating layer formed under the semiconductor layer, the gate line and the gate pad, and the data line and the data pad.

Abstract: The present invention discloses a thin film transistor array substrate and a manufacturing method for the same. A transparent conductive layer and a first metal layer are deposited on a substrate, and a multi-tone mask is utilized to form a gate electrode and a common electrode. A gate insulative layer and a semi-conductive layer are deposited on the substrate with the gate electrode and the common electrode, and the semi-conductive layer is patterned by a second mask to retain a region of the semi-conductive layer that is there-above the gate electrode. A second metal layer is deposited on the substrate with the gate insulative layer along with the retained semi-conductive layer, and the second metal layer is patterned by a third mask to form a source electrode, a drain electrode, and a pixel electrode. The present invention provides a simple manufacturing method.

Abstract: A thin film transistor is provided. The thin film transistor disposed on a substrate includes a gate electrode, a gate dielectric layer, a patterned semiconductor layer, a source electrode, a drain electrode covered with an anticorrosive conductive layer, a patterned passivation layer and a transparent conductive layer. The anticorrosive conductive layer includes indium tin oxide or indium zinc oxide, and is used to prevent the drain electrode from being over etched during the process of etching the passivation layer. A method for manufacturing the thin film transistor is also provided herein.

Abstract: A fin field effect transistor (FinFET) structure and method of making the FinFET including a silicon fin that includes a channel region and source/drain (S/D) regions, formed on each end of the channel region, where an entire bottom surface of the channel region contacts a top surface of a lower insulator and bottom surfaces of the S/D regions contact first portions of top surfaces of a lower silicon germanium (SiGe) layer. The FinFET structure also includes extrinsic S/D regions that contact a top surface and both side surfaces of each of the S/D regions and second portions of top surfaces of the lower SiGe layer. The FinFET structure further includes a replacement gate or gate stack that contacts a conformal dielectric, formed over a top surface and both side surfaces of the channel region.

Abstract: The present invention provides a thin film transistor (TFT) array substrate and a method for manufacturing the same. After depositing a first metal layer on a substrate, a first mask is utilized to form gate electrodes. After depositing a gate insulating layer and a semiconductor layer on the substrate, a second mask is utilized to pattern the semiconductor layer, so as to keep portions of the semiconductor layer above the gate electrodes. After depositing a transparent and electrically conductive layer and a second metal layer on the substrate, a multi tone mask is utilized to form source electrodes, drain electrodes, pixel electrodes and common electrodes. The present invention can simplify the manufacturing process thereof.

Abstract: A pixel structure includes a substrate; a scan line; a gate electrode; an insulating layer disposed on the scan line, the gate electrode and the substrate; a channel and a data line disposed on the insulating layer; a source electrode and a drain electrode disposed on the channel; a passivation layer; a pixel electrode and a connecting electrode. The data line does not overlap the scan line. The passivation layer disposed on the source electrode and the drain electrode includes a first contact hole partially exposing the drain electrode, and a plurality of second contact holes partially exposing the data line or the scan line. The pixel electrode disposed on the passivation layer is electrically connected to the drain electrode through the first contact hole. Furthermore, the connecting electrode disposed on the passivation layer is electrically connected to the data line or the scan line through the second contact holes.

Abstract: An array substrate including a substrate having a pixel region, a gate line and a gate electrode on the substrate, the gate electrode being connected to the gate line, a gate insulating layer on the gate line and the gate electrode, an oxide semiconductor layer on the gate insulating layer, an auxiliary pattern on the oxide semiconductor layer, and source and drain electrodes on the auxiliary pattern, the source and drain electrodes being disposed over the auxiliary pattern and spaced apart from each other to expose a portion of the auxiliary pattern, the exposed portion of the auxiliary pattern exposing a channel region and including a metal oxide over the channel region, wherein a data line crosses the gate line to define the pixel region and is connected to the source electrode, a passivation layer on the source and drain electrodes and the data line.

Abstract: A TFT array substrate includes a substrate, at least one gate line and gate electrode, a gate insulating layer, and at least one channel component, source electrode, drain electrode and data line. The gate line and gate electrode are disposed on the substrate, wherein both of the gate line and gate electrode have first and second conductive layers, the first conductive layer is formed on the substrate, the first conductive layer contains molybdenum nitride , the second conductive layer is formed on the first conductive layer, and the second conductive layer contains copper. The gate insulating layer is disposed on the gate line, gate electrode and the substrate. The channel component is disposed on the gate insulating layer. The source electrode and drain electrode are disposed on the channel component, and data line is disposed on the gate insulating layer.

Abstract: It is an object of the present invention to provide a thin film transistor in which an oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn) is used and contact resistance of a source or a drain electrode layer is reduced, and a manufacturing method thereof. An IGZO layer is provided over the source electrode layer and the drain electrode layer, and source and drain regions having lower oxygen concentration than the IGZO semiconductor layer are intentionally provided between the source and drain electrode layers and the gate insulating layer, so that ohmic contact is made.

Abstract: The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.

Abstract: An object is to stabilize electric characteristics of a semiconductor device including an oxide semiconductor to increase reliability. The semiconductor device includes an insulating film; a first metal oxide film on and in contact with the insulating film; an oxide semiconductor film partly in contact with the first metal oxide film; source and drain electrodes electrically connected to the oxide semiconductor film; a second metal oxide film partly in contact with the oxide semiconductor film; a gate insulating film on and in contact with the second metal oxide film; and a gate electrode over the gate insulating film.

Abstract: A method of forming a semiconductor device includes performing a first pre-amorphous implantation process on a substrate, where the substrate has a gate stack. The method further includes forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate, and performing a second annealing process on the substrate and the second stress film.

Abstract: A photolithography process for forming an island-shaped semiconductor layer is omitted, and a transistor is formed by at least two photolithography processes: a photolithography process for forming a gate electrode (including a wiring or the like formed from the same layer as the gate electrode) and a photolithography process for forming a source electrode and a drain electrode (including a wiring or the like formed from the same layer as the source electrode and the drain electrode). By using electron beam exposure, a transistor in which a distance between the source electrode and the drain electrode (channel length) is short can be formed. For example, a transistor whose channel length is less than 50 nm can be obtained.

Abstract: There are provided a thin-film transistor suppressing influence of light and having stable characteristics, and a method of manufacturing the thin-film transistor, as well as a display unit and an electronic apparatus. The thin-film transistor includes: a gate electrode; an oxide semiconductor film having a channel region that faces the gate electrode; and a protective film covering at least the channel region and containing an aluminum lower oxide (AlXOY, where 0<Y/X<3/2) that absorbs light.

Abstract: One of the objects of the present invention is to provide a thin film transistor using an oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn), in which the contact resistance between the oxide semiconductor layer and a source and drain electrodes is reduced, and to provide a method for manufacturing the thin film transistor. An ohmic contact is formed by intentionally providing a buffer layer having a higher carrier concentration than the IGZO semiconductor layer between the IGZO semiconductor layer and the source and drain electrode layers.

Abstract: It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.

Abstract: It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.

Abstract: A method for manufacturing a display panel includes; formation of a lower gate line, disposal of a semiconductor on the lower gate line, disposal of a lower data line substantially perpendicular to the lower gate line, disposal of an insulating layer having a plurality of trenches exposing the lower gate line and the lower data line on the lower data line, disposal of an upper gate line directly on the lower gate line and within the plurality of trenches, and disposal of an upper data line directly on the lower data line and within the plurality of trenches.

Abstract: A circuit including an inverter is provided for a wiring layer. A semiconductor device is provided with a wiring layer circuit which is formed over an insulating film and includes at least one inverter element. The inverter is provided with a first transistor element and a resistance element which is connected to the first transistor via a connection node. The first transistor element is provided with a gate electrode which is embedded in an interlayer insulating film including the insulating film, a gate insulating film which is formed over the interlayer insulating film and the gate electrode, and a first semiconductor layer which is formed over the gate insulating film between a source electrode and a drain electrode. The resistance element is provided with a second semiconductor layer which functions as a resistance. The first semiconductor layer and the second semiconductor layer are formed in the same layer.

Abstract: A method for fabricating a thin-film transistor is provided whereby isolation of transistor devices is realized and the performance and the stability of the product thin-film transistor are improved. The thin-film transistor includes a substrate; a gate electrode laminated on the substrate; a gate insulating layer laminated on the substrate and the gate electrode; a recessed portion provided in the gate insulating layer; a semiconductor layer formed in the recessed portion of the gate insulating layer; and a source electrode and a drain electrode connected to the semiconductor layer at respective positions which are spaced apart from each other.

Abstract: A manufacturing method of a thin film transistor (TFT) includes forming a gate electrode including a metal that can be combined with silicon to form silicide on a substrate and forming a gate insulation layer by supplying a gas which includes silicon to the gate electrode at a temperature below about 280° C. The method further includes forming a semiconductor on the gate insulation layer, forming a data line and a drain electrode on the semiconductor and forming a pixel electrode connected to the drain electrode.

Abstract: An array substrate comprises a substrate provided with a circuit pattern and covering layers that cover the upper surfaces and side surfaces of respective portions of the circuit pattern.

Abstract: An etchant for forming double-layered signal lines and electrodes of a liquid crystal display device includes hydrogen peroxide (H2O2), a phosphate, F-ions, an organic acid having a carboxyl group (—COOH), a copper (Cu) inhibitor, and a hydrogen peroxide (H2O2) stabilizer, wherein each of the double-layered signal lines and electrodes of the liquid crystal display device includes a first layer of one of aluminum (Al), aluminum alloy (Al-alloy), titanium (Ti), titanium alloy (Ti-alloy), tantalum (Ta), and a tantalum alloy (Ta-alloy) and a second layer of copper (Cu).

Abstract: A pixel structure includes a substrate, a gate line, a data line, a semiconductor pattern, a non-metal source electrode pattern, a non-metal drain electrode pattern, and a pixel electrode. The gate line and the data line are disposed on the substrate. The semiconductor pattern is disposed on the gate line, and the semiconductor pattern overlaps two corresponding edges of the gate line along a vertical projective direction. The non-metal source electrode pattern and the non-metal drain electrode pattern are disposed on the semiconductor pattern. The non-metal source electrode pattern and the non-metal drain electrode pattern are respectively disposed on two corresponding edges of the gate line. The non-metal source electrode pattern is partially disposed between the data line and the gate line. The pixel electrode is electrically connected to the non-metal drain electrode pattern.

Abstract: A thin film transistor (“TFT”) includes a gate electrode, a gate insulating layer, a source electrode, a drain electrode and a semiconductor layer. The gate insulating layer is disposed on the gate electrode. The source electrode is disposed on the gate insulating layer. The drain electrode is disposed on the gate insulating layer. The drain electrode is spaced apart from the source electrode. The semiconductor layer is disposed on the gate insulating layer. The semiconductor layer makes contact with a side surface of the source electrode and a side surface of the drain electrode.

Abstract: An etchant composition for etching a transparent electrode is provided, the etchant composition includes an inorganic acid, an ammonium (NH4+)-containing compound, a cyclic amine compound, and the remaining amount of water.

Abstract: A transistor includes a semiconductor layer, a gate spacer on the semiconductor layer, a gate dielectric comprising a first portion above the semiconductor layer and a second portion on sidewalls of the gate spacer, a work function metal layer comprising a first portion on the first portion of the gate dielectric and a second portion on sidewalls of the gate dielectric, a gate conductor on the first portion of the work function layer and abutting the second portion of the work function layer, a dielectric layer on the semiconductor layer and abutting the gate spacer, an oxide film above only one of the work function layer and the gate conductor, an oxide cap, source/drain regions, and a source/drain contact passing through the dielectric layer and contacting an upper surface of one of the source/drain regions. A portion of the source/drain contact is located directly on the oxide cap.

Abstract: Provided is an active matrix substrate manufacturing method, including the steps of: selectively forming a laminated structure pattern, by forming the laminated structure on a glass substrate (2), by forming a first photosensitive resin pattern (PR) on the laminated structure, and by selectively forming the laminated structure pattern using the first photosensitive resin pattern (PR), the laminated structure including a metal layer (a scanning signal line (11) material), a gate insulative layer (30), and a semiconductor layer (31, 33) (transistor material); fluorinating a surface of the first photosensitive resin pattern (PR) by dry-etching with fluorine gas; applying a coating-type transparent insulative resin (60) onto the glass substrate (2) to fill a space in the laminated structure pattern; and removing the fluorinated first photosensitive resin pattern (PR).