Abstract: In a non-volatile semiconductor memory device, the device is miniaturized by increasing the coupling ratio between a floating gate and a control gate electrode and reducing the write voltage. In a non-volatile memory device (a so-called floating gate type flash memory 300)) having a floating gate electrode FG in an insulation film (a tunnel oxide film (4), an ONO film structure (9)) between a semiconductor layer (a Si substrate (1)) and a control gate electrode CG, wherein charge is accumulated in the floating gate electrode FG, thereby causing a change in the threshold voltage of a transistor, and thus storing data, the floating gate electrode FG faces substantially the entire surfaces of a bottom surface and a side of the control gate electrode CG via the insulation film (the ONO film structure (9)).

Abstract: The method of the present invention includes the steps of forming doped regions in the semiconductor substrate. A pad oxide layer is formed on the semiconductor substrate. A masking layer is formed on the pad oxide. A masking layer, the pad layer and the semiconductor substrate are patterned to form a trench therein. A gap-filling material is refilled into the trench and over the semiconductor substrate. A portion of the gap-filling material is removed to upper surface of the masking layer. Next step is to remove the masking layer. A first conductive layer is formed along the surface of the substrate, then removing a portion of the first conductive layer to expose an upper surface of the gap-filling material. A dielectric layer is formed on the first conductive layer and a second conductive layer is formed on the tunneling dielectric layer.

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, and an array formed thereby, whereby each memory cell includes a trench formed into a surface of a semiconductor substrate, spaced apart source and drain regions with a channel region formed therebetween. The drain region is formed underneath the trench, and the channel region includes a first portion that extends substantially vertically along a sidewall of the trench and a second portion that extends substantially horizontally along the surface of the substrate. An electrically conductive floating gate is formed over and insulated from at least a portion of the channel region and a portion of the source region. An electrically conductive control gate is formed having a first portion disposed in the trench and a second portion formed over but insulated from the floating gate.

Abstract: A method for manufacturing a split-gate flash memory cell, comprising the steps of forming an active region on a semiconductor substrate; forming a buffer layer on the semiconductor substrate; forming a first dielectric layer on the buffer layer; removing part of the first dielectric layer; defining an opening; removing the buffer layer within the opening; forming a gate insulating layer and floating gates; forming a source region in the semiconductor substrate; depositing a conformal second dielectric layer on the opening; removing the buffer layer outside the first dielectric layer and the floating gates; and forming an oxide layer and control gates.

Abstract: A new device and technique to realize an improved integrated circuit device incorporates an improved polysilicon upper surface. This improvement is achieved by approximately planarizing an upper surface of the polysilicon layer. First, the polysilicon layer is preferably formed as a relatively thicker layer as compared to the layer thickness in a conventional device. Then a portion of the polysilicon layer is removed, preferably utilizing a chemical mechanical polish technique. Thus, this embodiment achieves a relatively planarized upper surface of the polysilicon layer. Then, for example, a conventional metal or silicide layer may be formed upon the relatively planarized polysilicon layer. This approximately planarized upper surface of the polysilicon layer allows for a silicide layer to be formed with a relative reduction in the amount and/or severity of the conventional word line voids and seams.

Abstract: A process for manufacturing a semiconductor memory device includes double polysilicon level non-volatile memory cells and shielded single polysilicon level non-volatile memory cells in the same semiconductor material chip. A first memory cell includes a MOS transistor having a first gate electrode and a second gate electrode superimposed and respectively formed by definition in a first and a second layer of conductive material. A second memory cell is shielded by a layer of shielding material for preventing the information stored in the second memory cell from being accessible from the outside. The second memory cell includes a MOS transistor with a floating gate electrode formed simultaneously with the first gate electrode of the first cell by definition of the first layer of conductive material. The layer of shielding material is formed by definition of the second layer of conductive material.

Abstract: A process for the manufacturing of electronic devices, including memory cells, involving forming, on a substrate of semiconductor material, multilayer stacks including a floating gate region, an intermediate dielectric region, and a control gate region; forming a protective layer extending on top of the substrate and between the multilayer stacks and having a height at least equal to the multilayer stacks. The step of forming multilayer stacks includes the step of defining the control gate region on all sides so that each control gate region is completely separate from adjacent control gate regions. The protective layer isolates the multilayer stacks from each other at the sides. Word lines of metal extend above the protective layer and are in electrical contact with the gate regions.

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, along with strap regions interlaced within the array and a peripheral region adjacent the array containing related logic devices. Structure planarization is enhanced by utilizing a pattern of dummy material in the peripheral region. The control gates of the memory cells and the logic gates of the logic devices are formed separately so each can be independently optimized.

Abstract: A non-volatile semiconductor memory device according to the present invention has a semiconductor substrate and a memory cell having a floating gate provided through a tunnel insulating layer on the semiconductor substrate, and a control gate provided through an inter-layer insulting layer on said floating gate. The inter-insulating layer includes a silicon oxide layer contiguous to said floating gate, a first silicon nitride layer provided by a CVD method on the silicon oxide layer and a second silicon nitride layer provided on said first silicon nitride layer and having a lower trap density than that of the first silicon nitride layer. The inter-insulating layer may includes a silicon oxide layer contiguous to said floating gate and a silicon oxide layer deposited on said silicon oxide layer and having a quantity of hydrogen content on the order of 1019/cm3 or less.

Abstract: In a method of fabricating a semiconductor device having a gate all around(GAA) structure transistor, an SOI substrate having a SOI layer, a buried oxide layer, and a bottom substrate is prepared. The SOI layer is patterned to form an active layer pattern. An etch stopping layer having an etch selectivity with respect to the buried oxide layer and the active layer pattern is stacked on the active layer pattern. The etch stopping layer pattern is patterned and removed at the gate region crossing the active layer pattern at the channel region, to form an etch stopping layer pattern and to expose the buried oxide layer. The buried oxide layer is isotropically etched using the etch stopping layer pattern as an etch mask to form a cavity at the channel region bottom of the active layer pattern. A conductive material fills the cavity and a space between the etch stopping layer pattern at the gate region. In this manner, the number of photolithography processes required for forming the device is reduced.

Abstract: According to the present invention, there is disclosed a 2-transistors type flash memory, wherein a memory-transistor is composed of layers of structure consisting of a floating gate and a control gate separated by a first insulating film; and, at least, a gate electrode of a select-transistor is composed of a single layer of a polysilicon film, which is formed from the same layer as the floating gate electrode of the memory-transistor and then doped to have an enhanced dopant concentration by ion implantation performed in the step of forming source-drain regions of the transistors.

Abstract: A novel flash memory structure is disclosed, which includes a tunnel oxide layer on a semiconductor substrate, an array of gate electrode stacks formed on the tunnel oxide layer, and alternating source/drain regions formed between the stacks. A first dielectric layer is formed over the stacks and the substrate with a source line opening down to the source regions. A source line is formed above the source regions, partially filling the source line opening. The source line is located between the gate electrode stacks and has a surface level below a top surface of the stacks. A second dielectric layer is formed over the source line and the first dielectric layer with a plug opening down to the drain regions. A drain metal plug is formed over the drain regions, filling the plug opening. A metal bit line is formed over the second dielectric layer contacting the drain metal plug.

Abstract: Structures and methods for Flash memory which reduce the tunneling time to speed up storage and retrieval of data in memory devices are provided. The flash memory cell includes a first source/drain region and a second source/drain region separated by a channel region. A first gate opposes. A first gate insulator separates the first gate from the channel. The first gate insulator includes a graded composition gate insulator. A second gate is separated from the first gate insulator by a second gate insulator. The above structures and methods produce gate insulators with less charging at the interface between composite insulator layers and provide gate insulators with low surface state densities. The systems and methods substantially reduce large barrier heights or energy problems by using dielectrics having suitably, adjustably lower barrier heights in contact with the polysilicon floating gate.

Abstract: Structures and methods are provided for SRAM cells having a novel, non-volatile floating gate transistor, e.g. a non-volatile memory component, within the cell which can be programmed to provide the SRAM cell with a definitive asymmetry so that the cell always starts in a particular state. The SRAM cells include a pair of cross coupled transistors. At least one of the cross coupled transistors includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator.

Abstract: A method for testing a semiconductor wafer. An array of probes is coupled to the semiconductor wafer. Then a voltage difference is applied across a plurality of adjacent metal line pairs (e.g., wordline and/or bitline pairs) of one or more SRAM arrays of at least one die. Application of the voltage difference induces failure of metal stringers or defects between the adjacent lines. Additionally, the voltage can be applied across respective pairs of substantially all parallel metal lines of the one or more SRAM arrays of more that one die of the semiconductor wafer.

Abstract: An improved method of fabricating a non-volatile semiconductor device having a BPTEOS oxide film is provided. The present method utilizes the step of performing a RTA at a temperature of about 800° C. immediately after the deposition of the BPTEOS film so as to densify and stabilize the same. Then, a CMP step is performed so as to planarize the BPTEOS film.

Abstract: A method for producing a self-aligned split-gate EEPROM memory cell is provided. The memory cell has a cell size smaller than the traditional spilt-gate structure without sacrificing program disturb immunity. Moreover, the problem current of the memory cell is much lower than the stack-gate structure. The method includes steps of: providing a silicone substrate, forming a select gate on the silicone substrate, growing a tunnel oxide layer on exposed surfaces of the silicon substrate, forming a floating gate self-aligned to one side of the select gate, performing an ion implantation to form a source region and a drain region on the silicone substrate, and forming a control gate over the floating gate and the select gate, wherein the control gate, the floating gate and the select gate are insulated from one another.

Abstract: The present invention relates to a memory cell structure of a flash memory and a method for fabricating the same and, more particularly, to a flash memory having annular floating gates. The present invention uses the capacitance coupling between the source and the floating gate to form a channel in the substrate under the floating gate. Hot electrons are injected into the floating gate or released from the floating gate to the control gate through inerpoly dieletric by injection point on the top of floating gate In the proposed memory cell, a floating gate is etched to form an annular shape situated between a drain, a source, and two field oxides. An interpoly dielectric and a control gate are stacked in turn on the floating gate and on the surface of the substrate not covered by the floating gate through means of self-alignment. An injection point not covered by the SiN film of the interpoly dielectric is formed on the top of the floating gate.

Abstract: A device and a method for refreshing the voltage of a circuit line that provides the capability of bringing the circuit line to a ground voltage or to a first voltage. The method provides storing the circuit line voltage in a capacitor; and controlling, by means of the stored voltage, a switch connecting the circuit line to a second voltage of absolute value greater than the first voltage, whereby the circuit line is set to the second voltage if, during the step of storing, the circuit line was at the first voltage.

Abstract: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

Abstract: Each memory cell is a memory transistor which is provided on a top side of a semiconductor body and has a gate electrode which is arranged in a trench located between a source region and a drain region that are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by a dielectric material. At least between the source region and the gate electrode and between the drain region and the gate electrode, there is an oxide-nitride-oxide layer sequence. The layer sequence is provided for the purpose of trapping charge carriers at the source and the drain.

Abstract: The electrical performance of a dielectric film for capacitive coupling in an integrated structure is enhanced by forming the polycrystalline electrically conductive layer coupled with the dielectric film substantially unigranular over the coupling area, commonly to be defined by patterning the stacked dielectric and conductive layers. The process forms a polycrystalline silicon film having exceptionally large grains of a size on the same order of magnitude as the dimensions of the patterned details. These exceptionally large grains are obtained by preventing the formation of “precursor nuclei” of subsequent grain formation and growth at the deposition interface with the dielectric that are apparently formed during the first instants of silicon CVD deposition and by successively growing the crystallites at a sufficiently low annealing temperature.

Abstract: A process for the manufacturing of electronic devices, including memory cells, involving forming, on a substrate of semiconductor material, multilayer stacks including a floating gate region, an intermediate dielectric region, and a control gate region; forming a protective layer extending on top of the substrate and between the multilayer stacks and having a height at least equal to the multilayer stacks. The step of forming multilayer stacks includes the step of defining the control gate region on all sides so that each control gate region is completely separate from adjacent control gate regions. The protective layer isolates the multilayer stacks from each other at the sides. Word lines of metal extend above the protective layer and are in electrical contact with the gate regions.

Abstract: Memory elements, switching elements, and peripheral circuits to constitute a nonvolatile memory are integrally formed on a substrate by using TFTs. Since semiconductor active layers of memory element TFTs are thinner than those of other TFTs, impact ionization easily occurs in channel regions of the memory element TFFs. This enables low-voltage write/erase operations to be performed on the memory elements, and hence the memory elements are less prone to deteriorate. Therefore, a nonvolatile memory capable of miniaturization can be provided.

Abstract: A nonvolatile memory device with a high coupling ratio is disclosed. The nonvolatile memory device includes a semiconductor substrate having shallow trench isolation (STI) formed therein and active regions defined. On the active regions, a floating gate is provided with a gate dielectric layer interposed. On the floating gate, a control gate is provided with a second dielectric layer interposed. The width of the floating gate is narrower than the active regions when viewed in transverse cross-section. A lighted doped region is optionally provided in the substrate at positions which are not covered by the floating gate. A manufacturing method for forming such memory device is also disclosed.

Abstract: A flash memory cell comprising a series of floating gate devices being connected to one-another through their source electrodes, which are self-aligned to their respective gate electrodes, where a local tungsten interconnect makes a substantially continuous connection to the self-aligned sources. The flash memory cell is formed by forming floating gate devices having their source electrodes connected together by a conductively doped active area, forming a nitride barrier layer overlying each transistor gate, forming a planarized insulation layer over the nitride barrier layer, removing portions of the planarized insulation layer while using the nitride barrier layer to self-align an interconnect via to the source electrodes, forming a tungsten-based interconnect into the interconnect via, the tungsten-based interconnect running a major length of the source electrodes being connected together and making contact therebetween, and forming a tungsten-based drain plug for each floating gate device.

Abstract: A method of forming a Flash EEPROM device with a gate electrode stack includes forming a tunnel oxide layer, a floating gate electrode layer, a dielectric layer, and a control gate layer on a doped silicon semiconductor substrate. Then form source/drain regions in the substrate. Next, form a surface P+ doped halo region in the surface of the N+ source region juxtaposed with the control gate electrode. The P+ halo region is surrounded by the N+ source region. The result is a device which is erased by placing a negative voltage of about −10V on the control gate and a positive voltage of about 5V on the combined source region/halo region to produce accumulation of holes in the channel which distributes the flow of electrons into the channel rather than concentrating the electrons near the interface between the source region and the edge of the tunnel oxide layer. The tunnel oxide layer has a thickness from about 70 Å to about 120 Å.

Abstract: A contactless channel write/erase flash memory cell structure and its fabricating method for increasing the level of integration is disclosed. The present invention utilizes a buried diffusion method to form an N+-doped region that acts as a drain of the flash memory cell and a P-doped region underneath an oxide layer. The N+-doped region and the P-doped region extend to in a bit line direction and a metal contact is used to connect the two away from any of the N+-doped region and the P-doped region of the flash memory cell for decreasing the numbers of the metal contacts in the flash memory cell and reducing dimensions of the device.

Abstract: The present invention provides a manufacturing method of a semiconductor device having a single semiconductor substrate, for forming a first processing circuit portion and a second processing circuit portion having mutually different thicknesses of gate oxide films on the single semiconductor substrate including the steps of: forming a first gate oxide film over the semiconductor substrate; sequentially forming an insulating film and a first conducting layer over the entire surface of the first gate oxide film; eliminating those portions ranging from the first gate oxide film to the first conducting layer, which portions are included within an element forming region of the first processing circuit portion; and forming, only in the element forming region of the first processing circuit portion, a second gate oxide film having a thickness different from that of the first gate oxide film.

Abstract: A non-volatile memory device includes a tunnel oxide layer, a charge storage layer, a blocking insulating layer, and a gate electrode that are sequentially stacked, as well as an impurity diffusion layer in an active region at both sides of the gate electrode. The gate electrode crosses active regions between device isolation layers formed in a predetermined area of a semiconductor substrate, and an edge of the charge storage layer is extended to have a protruding part that protrudes from the gate electrode. In order to form a charge storage layer having a protruding part, a stack insulating layer including first to third insulating layers is formed in an active region between the device isolation layers formed in the substrate. A plurality of gate electrodes crossing the active region are formed on the stack insulating layer, and a sidewall spacer is formed on both sidewalls of the gate electrode.

Abstract: A semiconductor memory comprises: a first conductivity type semiconductor substrate and one or more memory cells each constituted of an island-like semiconductor layer having a recess on a sidewall thereof, a charge storage layer formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, and a control gate formed on the charge storage layer, wherein at least one charge storage layer of said one or more memory cells is partially situated within the recess formed on the sidewall of the island-like semiconductor layer.

Abstract: A nonvolatile memory comprises a substrate having trenches formed therein, a first dielectric layer is formed on said substrate. Protruding isolations are formed in said trenches and protruding over a surface of said substrate, thereby forming cavity between thereof. A first conductive layer is formed on said first dielectric layer and in said cavity. A second dielectric layer is formed on said second conductive layer and a second conductive layer is formed on said second dielectric layer as a control gate.

Abstract: A nonvolatile semiconductor memory includes a trench isolation provided in a semiconductor substrate and an interlayer insulator provided on the semiconductor substrate. The trench isolation defines an active area extending in a first direction at the semiconductor substrate. The interlayer insulator has a wiring trench extending in a second direction intersecting the first direction. A first conductive material layer is provided at the cross-point of the active area and the wiring trench so that it is insulated from the active area. A second conductive material layer is provided in the wiring trench so that it is insulated from the first conductive material layer. A metal layer is provided in the wiring trench so that it is electrically in contact the second conductive material layer.

Abstract: An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices.

Abstract: An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices.

Abstract: A simple and easy method for exercising quality control over memory cell inter-layer dielectric film within a short period of time, using a memory array or single memory formed in the scribe area, without stressing nonvolatile semiconductor memory cells and a method of manufacturing a nonvolatile semiconductor memory device; whereby a single nonvolatile memory is formed in an area other than a chip area on a semiconductor wafer and used after completion of a wafer manufacturing process to perform an inter-layer dielectric film quality control process for evaluating the write saturation characteristic, cut out nondefective chips only, and conduct a plastic molding process, achieving an increased yield after chip cutting.

Abstract: A method is provided for fabricating memory devices on a semiconductor substrate using a dual damascene process. The method includes the steps of forming at least one dummy gate structure for at least one memory device on the semiconductor substrate, depositing dielectric material on surroundings of the at least one dummy gate structure, etching the dielectric material and the at least one dummy gate structure to form at least one control gate void and at least one floating gate void, forming a gate dielectric layer on a bottom surface of the at least one floating gate void, depositing floating gate material on the gate dielectric layer in the at least one floating gate void to form a floating gate, depositing a dielectric layer on the floating gate, and depositing control gate material on the dielectric layer in the at least one control gate void to form a control gate.

Abstract: A contact-less array of self-aligned, triple polysilicon, source side injection, nonvolatile memory cells with metal-overlaid wordlines includes: a plurality of pairs of stacks of first, second and third layer polysilicon arrange in rows; a drain region between the two stacks in each pair of polysilicon stacks, the drain regions being self-aligned to the edges of the two stacks; and a source region between each of the two adjacent pairs of polysilicon stacks, the source regions being self-aligned to side-wall spacers formed adjacent to edges of the polysilicon stacks such that each source region is laterally spaced an equal distance from the edges of the two stacks of polysilicon between which the source region is located.

Abstract: A nonvolatile memory device and a method of forming the nonvolatile memory device having a shallow trench isolation structure and having a device isolation layer having a protruding portion above a substrate surface includes forming a gate oxide, a lower conductive layer pattern, and a hard mask layer; patterning the hard mask layer; isotropically etching the lower conductive layer to form a lower conductive layer pattern having a sloped sidewall profile where a width of a lower portion of the lower conductive layer pattern is smaller than a width of an upper portion of the lower conductive layer pattern; etching the gate oxide layer and the substrate, using the hard mask pattern as an etch mask, to form a trench; and forming a device isolation layer contacting with a sidewall of the lower conductive layer pattern in the trench.

Abstract: A semiconductor substrate has a V-shape structure positioned in the semiconductor substrate. A first ion implantation process is then performed to form a first doping region around the V-shape structure in the semiconductor substrate. Following this, a first dielectric layer is formed on surfaces of the semiconductor substrate and the first doping region. A floating gate is formed on the first dielectric layer over the first doping region and a second dielectric layer is formed on the floating gate, respectively. A controlling gate is then formed on the second dielectric layer. Finally, a second ion implantation process is performed utilizing the controlling gate as a mask to form a second doping region in the semiconductor substrate.

Abstract: A non-volatile semiconductor memory device and the fabricating method thereof, wherein control gates respectively formed at the active areas of the resultant structure for getting a corresponding pair of split floating gates continuously overlapped and buried diffusion areas formed at the substrate of the periphery of the field insulating layer positioned between neighboring source areas to prevent the source areas from being electrically disconnected by the field insulating layer, even if the floating gate pattern and the control gate pattern are respectively made by separate processes, so that there will be no mismatching between the aforementioned two patterns, thereby leading to no tendency of showing different characteristics of memory cells in accordance with odd/even numbered word lines, the schematic characteristic of cells makes it possible to program and erase a byte, and one contact hole is not used at each bit line, the number of contact holes gets small, thereby making it possible to scale down c

Abstract: A semiconductor device has, in one embodiment, two wells of different conductivity types formed in a semiconductor substrate. The two wells are arranged to be adjacent to each other to form a junction therebetween. A field oxide film is formed to cover the junction at a main surface of the semiconductor substrate. Other field oxide films or field-shield isolation structures may be formed to isolate circuit elements from one another in the wells.

Abstract: The flash memory structure includes a substrate having trenches formed therein, a first dielectric layer and a first conductive layer are stacked on the substrate. Isolations are formed in the trenches and protruding over the surface of the substrate, wherein the first conductive layer is also protruded over the isolations. A second conductive layer is lying the surface of the first conductive layer and a second dielectric layer formed thereon. A third conductive layer is formed on the second dielectric layer. The floating gate is consisted of first conductive layer and the second conductive layer.

Abstract: An identifier is provided for an integrated circuit with a memory composed of a multiplicity of memory cells. The circuit has a manufacture-related memory cell defect pattern formed of defective memory cells. The method of identifying the integrated circuit utilizes the memory cell defect pattern to generate a circuit identification number for identifying the integrated circuit.

Abstract: A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to isolation, to source and to word line. This multi-self-aligned structure, which provides the maximum shrinkage of the cell that is possible, is also disclosed. The multi-self-alignment is accomplished by first defining the floating gate at the same time the trench isolation is formed, and then self-aligning the source to the floating gate by using a nitride layer as a hard mask in place of the traditional polyoxide, and finally forming a polysilicon spacer to align the word line to the floating gate. Furthermore, a thin floating gate is used to form a thin and sharp poly tip through the use of a “smiling effect” to advantage.

Abstract: A simplified DSCP process makes non-self-aligned floating gate semiconductor memory cells of the FLOTOX EEPROM type as incorporated to a cell matrix having control circuitry associated therewith, wherein each cell has a selection transistor associated therewith. The process includes at least the following steps: growing or depositing a gate dielectric layer of the selection transistor and the cell; tunnel masking to define the tunnel area with a dedicated etching step for cleaning the semiconductor surface; growing the tunnel oxide; depositing and doping the first polysilicon layer poly1.

Abstract: A nonvolatile memory array is encased in a P-well, and the P-well encased in a deep N-well, the two wells separating the memory array from the integrated circuit substrate and from the other circuitry of the integrated circuit. At the same time the deep N-well is formed for the nonvolatile memory array, deep N-wells are formed for the high-voltage P-channel transistors of the logic circuitry. At the same time the P-well is formed for the nonvolatile memory array, P-wells are formed for the low-voltage N-channel transistors. The memory array contains nonvolatile cells of the type used in ultra-violet-erasable EPROMs. During erasure, the isolated-well formation allows the source, the drain and the channel of selected cells to be driven to a positive voltage. The isolated well is also driven to a positive voltage equal to, or slightly greater than, the positive voltage applied to the source and drain, thus eliminating the field-plate breakdown-voltage problem.

Abstract: A method for shrinking a semiconductor device and minimizing auto-doping problem is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.

Abstract: In a method of fabricating a microstructure for microfluidics applications, a first layer of etchable material is formed on a suitable substrate. A mechanically stable support layer is formed over the etchable material. A mask is applied over the support to expose at least one opening in the mask. An anistropic etch is then performed through the opening to create a bore extending through the support layer to said layer of etchable material. After performing an isotropic etch through the bore to form a microchannel in the etchable material extending under the support layer, a further layer is deposited over the support layer until overhanging portions meet and thereby close the microchannel formed under the opening.

Abstract: A method for manufacturing a semiconductor device comprising a nonvolatile memory transistor of a stacked gate structure having a floating gate and a control gate, and a MOS transistor of a single gate structure, wherein the method comprises the steps of forming a first insulation film that becomes a gate oxide film of the transistors on a semiconductor substrate; forming a first conductive layer on the first insulation film; removing, from the first conductive layer, a region for separating a floating gate in a direction perpendicular to a direction in which the control gate is formed extendedly; forming a second insulation layer on the first conductive layer; forming a second conductive layer on the second insulation film; patterning the second conductive layer so as to form the control gate; and patterning the first conductive layer to form the stacked gate structure and the single gate structure.