Including Insulated Gate Field Effect Transistor Having Gate Surrounded By Dielectric (i.e., Floating Gate) Patents (Class 438/201)
  • Patent number: 7118954
    Abstract: A method for fabricating metal-oxide-semiconductor devices is provided. The method includes forming a gate dielectric layer on a substrate; depositing a polysilicon layer on the gate dielectric layer; forming a resist mask on the polysilicon layer; etching the polysilicon layer not masked by the resist mask, thereby forming a gate electrode; etching a thickness of the gate dielectric layer not covered by the gate electrode; stripping the resist mask; forming a salicide block resist mask covering the gate electrode and a portions of the remaining gate dielectric layer; etching away the remaining gate dielectric layer not covered by the salicide block resist mask, thereby exposing the substrate and forming a salicide block lug portions on two opposite sides of the gate electrode; and making a metal layer react with the substrate, thereby forming a salicide layer that is kept a distance ā€œdā€ away from the gate electrode.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: October 10, 2006
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Ming Lin, Ming-Tsung Tung, Chin-Hung Liu
  • Patent number: 7115458
    Abstract: Methods and apparatus utilizing a stepped floating gate structure to facilitate reduced spacing between adjacent cells without significantly impacting parasitic capacitance. The stepped structure results in a reduced surface area of a first floating gate in close proximity to an adjacent floating gate with substantially no reduction in coupling area, thus facilitating a reduction in parasitic capacitance leading to improved gate coupling characteristics. Also, because of the reduced surface area exposed to adjacent floating gates, the floating gates may be formed with reduced spacing, thus further leading to improved gate coupling characteristics.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: October 3, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Paul J. Rudeck
  • Patent number: 7112489
    Abstract: A method of implanting a middle of line (MOL) implant layer of a flash memory device that does not require a descumming step is disclosed. In a first embodiment, the method includes depositing a negative tone resist over the MOL implant layer. Portions of the negative tone resist in and above a plurality of trenches are not exposed to optical radiation, while portions surrounding the plurality of trenches are exposed. The unexposed portions are developed out thereby leaving a bottom surface of each trench substantially free of a resist residue. Implants can be placed in the MOL implant layer without the need for a descumming step. In a second embodiment, a bi-layer resist is deposited on the MOL implant layer, wherein the bi-layer resist includes a silicon containing top layer and a bottom layer. The bi-layer resist is patterned to expose a portion of the bottom layer that resides in and above a plurality of trenches.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: September 26, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christopher F. Lyons, Anna Minvielle, Marina V. Plat
  • Patent number: 7102190
    Abstract: A structure for flash memory cells is disclosed, Isolation regions are formed in a semiconductor region separating cells and also separating programming bit line channel regions of a cell from reading bit line charmel regions of a cell. A conductive floating gates has a first portion in the programming bit line channel region of a cell and a second portion in the reading bit line channel region of the cell and a third connecting portion passing over an isolation region.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: September 5, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiang-Tai Lu, Chia-Ta Hsieh
  • Patent number: 7101749
    Abstract: A non-volatile semiconductor memory device according to the present invention has a semiconductor substrate and a memory cell having a floating gate provided through a tunnel insulating layer on the semiconductor substrate, and a control gate provided through an inter-layer insulting layer on said floating gate. The inter-insulating layer includes a silicon oxide layer contiguous to said floating gate, a first silicon nitride layer provided by a CVD method on the silicon oxide layer and a second silicon nitride layer provided on said first silicon nitride layer and having a lower trap density than that of the first silicon nitride layer. The inter-insulating layer may includes a silicon oxide layer contiguous to said floating gate and a silicon oxide layer deposited on said silicon oxide layer and having a quantity of hydrogen content on the order of 1019/cm3 or less.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: September 5, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Seiichi Mori
  • Patent number: 7098096
    Abstract: A method of fabricating a multi-bit flash memory, having a control gate, a floating gate, a source region, a drain region and a channel region. An isolation region is formed in the floating gate to partition the floating gate into a plurality of conductive blocks. The conductive blocks are arranged in an array with rows extending from the source region to the drain region. Each row of the array has two conductive blocks. Before any data is written to the flash memory, the channel regions under the conductive blocks of the same row have the same threshold voltage, while the channel regions under the conductive blocks of different rows have different threshold voltage.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: August 29, 2006
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Kent Kuohua Chang
  • Patent number: 7091130
    Abstract: A plurality of memory cell devices is formed by using an intermediate dual polysilicon-nitride control electrode stack overlying nanoclusters. The stack includes a first-formed polysilicon-nitride layer and a second-formed polysilicon-containing layer. The second-formed polysilicon-containing layer is removed from areas containing the plurality of memory cells. In one form the second-formed polysilicon-containing layer also contains a nitride portion which is also removed, thereby leaving the first-formed polysilicon-nitride layer for the memory cell devices. In another form the second-formed ploysilicon-containing layer does not contain nitride and a nitride portion of the first-formed polysilicon-nitride layer is also removed. In the latter form a subsequent nitride layer is formed over the remaining polysilicon layer. In both forms a top portion of the device is protected from oxidation, thereby preserving size and quality of underlying nanoclusters.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: August 15, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Rajesh A. Rao, Ramachandran Muralidhar, Robert F. Steimle, Gowrishankar L. Chindalore
  • Patent number: 7084453
    Abstract: A semiconductor memory device and method for making the same, where a memory cell and high voltage MOS transistor are formed on the same substrate. An insulating layer is formed having a first portion that insulates the control and floating gates of the memory cell from each other, and a second portion that insulates the poly gate from the substrate in the MOS transistor. The insulating layer is formed so that its first portion has a smaller thickness than that of its second portion.
    Type: Grant
    Filed: May 19, 2004
    Date of Patent: August 1, 2006
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Geeng-Chuan Chern, Amitay Levi, Dana Lee
  • Patent number: 7081380
    Abstract: A method of forming a conductive pattern of a semiconductor device includes forming a conductive layer is on a substrate, forming a polishing protection layer on the substrate including over the conductive layer, and forming a step compensation layer on the polishing protection layer to reduce the step presented by the layer that is the polishing protection layer. The conductive layer is the exposed by removing select portions of the step compensation layer and the polishing protection layer. The conductive pattern is ultimately formed on the substrate by etching the exposed conductive layer. By planarization the intermediate structure several times once the step compensation layer is formed, a highly uniform conductive layer is sure to be formed.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: July 25, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Don-Woo Lee, Chul-Soon Kwon, Chang-Yup Lee
  • Patent number: 7060549
    Abstract: SRAM devices utilizing tensile-stressed strain films and methods for fabricating such SRAM devices are provided. An SRAM device, in one embodiment, comprises an NFET and a PFET that are electrically coupled and physically isolated. The PFET has a gate region, a source region, and a drain region. A tensile-strained stress film is disposed on the gate region and at least a portion of the source region and the drain region of the PFET. A method for fabricating a cell of an SRAM device comprises fabricating an NFET and a PFET overlying a substrate. The PFET and the NFET are electically coupled and are physically isolated. A tensile-strained stress film is deposited on the gate region and at least a portion of the source region and the drain region of the PFET.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: June 13, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark Craig, Karsten Wieczorek, Manfred Horstmann
  • Patent number: 7053437
    Abstract: A semiconductor memory device including memory cells, each memory cell including: a gate insulating film formed on a semiconductor substrate; a gate electrode formed on the gate insulating film; a channel region located below the gate electrode; a pair of source and drain regions arranged on a opposite sides, respectively, of the channel region, the source and drain regions having a conductive type opposite to that of the channel region; and memory functional units located on opposite sides, respectively, of the gate electrode, each memory functional unit including a charge retaining portion and an anti-dissipation insulator, the charge retaining portion being made of a material serving to store charges, the anti-dissipation insulator serving to prevent the stored charges from being dissipated by separating the charge retaining portion from both the gate electrode and the substrate, wherein a distance between a side wall of the gate electrode and a side of the charge retaining portion facing each other (T2) i
    Type: Grant
    Filed: May 19, 2004
    Date of Patent: May 30, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Iwata, Takayuki Ogura, Akihide Shibata
  • Patent number: 7049188
    Abstract: A lateral doped channel. A first doping material is implanted substantially vertically into a region adjacent to a gate structure. A diffusion process diffuses the first doping material into a channel region beneath the gate structure. A second doping material is implanted substantially vertically into the region adjacent to a gate structure. The second implantation forms source/drain regions and may terminate the channel region. The channel region thus comprises a laterally non-uniform doping profile which beneficially mitigates the short channel effect and is highly advantageous as compensation for manufacturing process variations in channel length.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: May 23, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nga-Ching Wong, Timothy Thurgate, Sameer S. Haddad
  • Patent number: 7037785
    Abstract: Disclosed is a method of manufacturing the flash memory device.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: May 2, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventors: Cha Deok Dong, Ho Min Son
  • Patent number: 7029968
    Abstract: A method of forming a polysilicon-insulator-polysilicon (PIP) capacitor in a mixed mode semiconductor device. A floating gate of a split gate transistor and a bottom electrode of a PIP capacitor are formed from a first polysilicon layer using a single lithography mask. Poly-oxide regions are formed over the floating gate and the bottom electrode, and an oxide layer is formed over the poly-oxide regions and other exposed material layers. A nitride layer is deposited over the oxide layer. The nitride layer is patterned to expose at least a portion of the poly-oxide region over the bottom electrode. The exposed oxide layer and poly-oxide region are removed from over the bottom electrode. A second polysilicon layer is deposited over the structure, and a control gate of the split gate transistor and a top electrode of the PIP capacitor are formed from the second polysilicon layer using a single lithography mask.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: April 18, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Kuo-Chi Tu
  • Patent number: 7026196
    Abstract: A method for forming a field effect transistor includes: forming a conductive region on an isolation layer formed on a substrate, and a cap dielectric layer on the conductive region; forming a sacrificial dielectric layer over the isolation layer and the cap dielectric layer, and on sidewalls of the conductive region; removing a portion of the sacrificial dielectric layer on the cap dielectric layer; removing the cap dielectric layer; removing remaining portions of the sacrificial dielectric layer; forming a gate on the conductive region; and forming source/drain (S/D) regions within the conductive region and adjacent to the gate. A field effect transistor includes a conductive region over an isolation layer formed on a substrate, the conductive region being substantially without undercut at the region within the isolation layer beneath the conductive region; a gate on the conductive region; and S/D regions within the conductive region and adjacent to the gate.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: April 11, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuan-Ping Hou, Jhi-Cherng Lu, Kuang-Hsin Chen, Hsun-Chih Tsao
  • Patent number: 7027328
    Abstract: Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, Gd2O3, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: April 11, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Jerome M. Eldridge, Kie Y. Ahn
  • Patent number: 7023043
    Abstract: An improved charge storing device and methods for providing the same, the charge storing device comprising a conductor-insulator-conductor (CIC) sandwich. The CIC sandwich comprises a first conducting layer deposited on a semiconductor integrated circuit. The CIC sandwich further comprises a first insulating layer deposited over the first conducting layer in a flush manner. The first insulating layer comprises a structure having a plurality of oxygen cites and a plurality of oxygen atoms that partially fill the oxygen cites, wherein the unfilled oxygen cites define a concentration of oxygen vacancies.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: April 4, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Howard E. Rhodes, Gurtej Sandhu, F. Daniel Gealy, Thomas M. Graettinger
  • Patent number: 7022573
    Abstract: A stacked gate vertical flash memory and a fabrication method thereof. The stacked gate vertical flash memory comprises a semiconductor substrate with a trench, a source conducting layer formed on the bottom of the trench, an insulating layer formed on the source conducting layer, a gate dielectric layer formed on a sidewall of the trench, a conducting spacer covering the gate dielectric layer as a floating gate, an inter-gate dielectric layer covering the conducting spacer, and a control gate conducting layer filled in the trench.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: April 4, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Ching-Nan Hsiao, Ying-Cheng Chuang, Chi-Hui Lin
  • Patent number: 7022571
    Abstract: A quantum structure and the forming method based on the difference in characteristic of two matters is provided. The forming method includes several steps. At first, providing a first dielectric layer for forming a second dielectric layer thereon. The second dielectric layer has major elements and impurities contained. Treating the second dielectric layer to drive the impurities to form the quantum structure. For example, oxidizing the major elements to drive the impurities in the first dielectric layer to form the quantum structure in said first dielectric layer because the oxidizing capability of the major elements is stronger than that of the impurities.
    Type: Grant
    Filed: May 1, 2003
    Date of Patent: April 4, 2006
    Assignee: United Microelectronics Corp.
    Inventors: Ting-Chang Chang, Po-Tsun Liu
  • Patent number: 7018898
    Abstract: The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions (2) for a selection transistor (AT) and a memory transistor (ST) being formed in a substrate (1). The memory transistor (ST) has a first insulation layer (3), a charge storage layer (4), a second insulation layer (5) and a memory transistor control layer (6), while the selection transistor (AT) has a first insulation layer (3?) and a selection transistor control layer (4*). By using different materials for the charge storage layer (4) and the selection transistor control layer (4*), it is possible to significantly improve the charge retention properties of the memory cell by adapting the substrate doping with electrical properties remaining the same.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: March 28, 2006
    Assignee: Infineon Technologies AG
    Inventors: Franz Schuler, Georg Tempel
  • Patent number: 7012304
    Abstract: An integrated circuit including a performance circuit occupying a first area of an integrated circuit substrate and a protection circuit coupled to the performance circuit and occupying a second area of an integrated circuit substrate separate from the first area. Also, a method of forming an integrated circuit including the steps of: Forming a performance circuit occupying a first area of an integrated circuit substrate, forming a protection circuit occupying a second area of an integrated circuit separate from the first area, and coupling the protection circuit to the performance circuit.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: March 14, 2006
    Assignee: Intel Corporation
    Inventors: Sanjay Dabral, Krishna Seshan
  • Patent number: 7012295
    Abstract: The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-electrode dielectric. A select transistor has a second cell site gate insulator having a same thickness as the first cell site gate insulator, a second lower conductive layer on the second cell site gate insulator, a second inter-electrode dielectric on the second lower conductive layer, and a second upper conductive layer on the second inter-electrode dielectric. The peripheral transistor has a first peripheral site gate insulator having a thickness thinner than the first cell site gate insulator.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: March 14, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuhiro Sato, Makoto Sakuma, Fumitaka Arai
  • Patent number: 7005338
    Abstract: A floating gate (110) of a nonvolatile memory cell is formed in a trench (114) in a semiconductor substrate (220). A dielectric (128) covers the surface of the trench. The wordline (140) has a portion overlying the trench. The cell's floating gate transistor has a first source/drain region (226), a channel region (224), and a second source/drain region (130). The dielectric (128) is stronger against leakage near at least a portion of the first source/drain region (122) than near at least a portion of the channel region. The stronger portion (128.1) of the additional dielectric improves data retention without increasing the programming and erase times if the programming and erase operations do not rely on a current through the stronger portion. Additional dielectric (210) has a portion located below the top surface of the substrate between the trench and a top part of the second source/drain region (130). The second source/drain region has a part located below the additional dielectric and meeting the trench.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: February 28, 2006
    Assignee: ProMOS Technologies Inc.
    Inventors: Yi Ding, Vei-Han Chan
  • Patent number: 7005345
    Abstract: In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: February 28, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshitake Yaegashi, Kazuhiro Shimizu, Seiichi Aritome
  • Patent number: 7005344
    Abstract: A floating gate transistor has a reduced barrier energy at an interface between a gallium nitride (GaN) or gallium aluminum nitride (GaAlN) floating gate an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: February 28, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Patent number: 6989303
    Abstract: A method of manufacturing a semiconductor memory integrated circuit intended to improve properties and reliability of its peripheral circuit includes the step of forming a tunnel oxide film (21a) in the cell array region, gate oxide film (21b) for a high-voltage circuit and gate oxide film (21c) for a low-voltage circuit both in the peripheral circuit to respectively optimum values of thickness, and covering them with a first-layer polycrystalline silicon film (22). After that, device isolation grooves (13) are formed and buried with a device isolation insulating film (14). The first-layer polycrystalline silicon film (24) is a non-doped film, and after device isolation, a second-layer polycrystalline silicon film (24) is doped with phosphorus in the cell array region to form floating gates made of the first-layer polycrystalline silicon film (22) and the second-layer polycrystalline silicon film (24).
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: January 24, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Seiichi Mori
  • Patent number: 6987046
    Abstract: The present invention discloses a method for manufacturing a flash memory device including the steps of: sequentially forming a first polysilicon film for a floating gate electrode, a first oxide film, a polysilicon film for a hard mask and a second oxide film on a semiconductor substrate; etching and patterning the second oxide film and the polysilicon film for the hard mask, by forming photoresist patterns on a predetermined region of the second oxide film, and removing the photoresist patterns; forming spacers on the sidewalls of the polysilicon film for the hard mask, by forming and etching a polysilicon film for forming spacers on the whole surface of the resulting structure; removing the exposed first oxide film and a predetermined thickness of second oxide film formed on the patterned polysilicon film for the hard mask; forming floating gate electrode patterns by performing first and second etching processes by using the patterned polysilicon film for the hard mask and the spacers as an etch mask; perf
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: January 17, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventors: In Kwon Yang, Byoung Ki Lee, Jung Woong Lee
  • Patent number: 6982456
    Abstract: A nonvolatile semiconductor memory device according to the present invention has a control gate electrode which is formed on the upper stage of a stepped portion formed in the principal surface of a substrate with a first insulating film interposed therebetween and a floating gate electrode which is formed to cover up the stepped portion, capacitively coupled to the side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween, and opposed to the lower stage of the stepped portion with a third insulating film serving as a tunnel film interposed therebetween.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: January 3, 2006
    Assignee: Matsushita Electic Industrial Co., Ltd.
    Inventors: Nobuyo Sugiyama, Hiromasa Fujimoto, Shinji Odanaka, Seiki Ogura
  • Patent number: 6974739
    Abstract: A gate dielectric (150) for a gate (160) is formed by thermal oxidation simultaneously with as a dielectric on a surface of another gate (140). The dielectric thickness on the other gate is controlled by the dopant concentration in the other gate. The gates may be gates of different MOS transistors, or a select gate and a floating gate of a memory cell. Other features are also provided.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: December 13, 2005
    Assignee: ProMOS Technologies Inc.
    Inventor: Yi Ding
  • Patent number: 6972229
    Abstract: A method of forming a self-aligned non-volatile device, includes, in part: forming trench isolation regions, forming a well between the trench isolation, forming a second well above the first well, forming a first oxide layer above a first portion of the second well, forming a first dielectric, a first polysilicon gate, and a second dielectric layer, respectively, above the first polysilicon layer, forming a first spacer above the body region and adjacent the first polysilicon layer, forming a second oxide layer above a second portion of the second well not covered by the first spacer, forming a second polysilicon gate layer above the second oxide layer, the first spacer and a portion of the second dielectric layer, removing the second polysilicon layer and the layers below it that are exposed in a via formed using a mask, thereby forming self-aligned source/drain regions.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: December 6, 2005
    Assignee: 02IC, Inc.
    Inventor: Kyu Hyun Choi
  • Patent number: 6972226
    Abstract: In a memory cell array comprising charge-trapping memory cells, local interconnects along the direction of the wordlines for connecting source/drain regions of adjacent memory cells to bitlines are formed by selective deposition of silicon or polysilicon bridges at sidewalls of the semiconductor material within upper recesses in the dielectric material of shallow trench isolations running across the wordlines.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: December 6, 2005
    Assignee: Infineon Technologies AG
    Inventors: Joachim Deppe, Josef Willer
  • Patent number: 6972455
    Abstract: A flash memory structure having high coupling ratio and the manufacturing method thereof are provided.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: December 6, 2005
    Assignee: Winbond Electronics Corporation
    Inventor: Han-Hsing Liu
  • Patent number: 6971160
    Abstract: A hybrid integrated circuit fabrication method in which an insulating substrate member and its metallic substrate carrier are made to be mating with precision through use of computer controlled machining performed on each member. A combination of disclosed specifically tailored software and commercially available software are used in the method to generate code for controlling a precision milling machine during the fabrication of substrate and substrate carrier members. The method for precision mating of substrate and substrate carrier enable disposition of a precision recess in the substrate carrier and the location of recess pillars and pedestals (the latter being for integrated circuit die mounting use) at any carrier recess location desirable for electrical, thermal or physical strength reasons.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: December 6, 2005
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Ryan J. Welch, Tony K. Quach
  • Patent number: 6969645
    Abstract: A method of manufacturing a semiconductor device comprising a non-volatile memory with memory cells (Mij) including a select transistor (T1) with a select gate (1) and including a memory transistor (T2) with a floating gate (2) and a control gate (3). In a semiconductor body (10), active semiconductor regions are formed which are mutually insulated by field oxide regions (12). Next, the surface (11) is provided with a gate oxide layer (14) and a first layer of a conductive material wherein the select gate (1) is etched. Subsequently, the walls of the select gate extending perpendicularly to the surface are provided with an isolating material (17). The gate oxide next to the select gate is replaced by a layer of tunnel oxide (18). Next, a second layer of a conductive material (21), an interlayer dielectric (25) and a third layer of a conductive material (26) are deposited. The control gate (3) extending above and next to the select gate is formed in the third layer.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: November 29, 2005
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Jurriaan Schmitz, Franciscus Petrus Widdershoven, Michiel Slotboom
  • Patent number: 6965142
    Abstract: Hot-electron injection driven by hole impact ionization in the channel-to-drain junction of a p-channel MOSFET provides a new mechanism for writing a floating-gate memory. Various pFET floating-gate structures use a combination of this mechanism and electron tunneling to implement nonvolatile analog memory, nonvolatile digital memory, or on-line learning in silicon. The memory is nonvolatile because the devices use electrically isolated floating gates to store electronic charge. The devices enable on-line learning because the electron injection and tunneling mechanisms that write the memory can occur during normal device operation. The memory updates and learning are bidirectional because the injection and tunneling mechanisms add and remove electrons from the floating gate, respectively. Because the memory updates depend on both the stored memory and the pFETs terminal voltages, and because they are bidirectional, the devices can implement on-line learning functions.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: November 15, 2005
    Assignee: Impinj, Inc.
    Inventors: Christopher J. Diorio, Todd E. Humes
  • Patent number: 6960500
    Abstract: A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: November 1, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: You-Cheol Shin, Kyu-Charn Park, Won-Hong Lee, Jung-Dal Choi
  • Patent number: 6955968
    Abstract: Flash memory cells are provided that include a first source/drain region and a second source/drain region separated by a channel region. A first gate opposes. A first gate insulator separates the first gate from the channel. The first gate insulator includes a graded composition gate insulator. A second gate is separated from the first gate insulator by a second gate insulator. The above memory cells produce gate insulators with less charging at the interface between composite insulator layers and provide gate insulators with low surface state densities. The memory cells substantially reduce large barrier heights or energy problems by using dielectrics having suitably, adjustably lower barrier heights in contact with the polysilicon floating gate. Such adjustable barrier heights of controlled thicknesses can be formed using a silicon suboxide and a silicon oxycarbide dielectrics prepared according to the process as described herein.
    Type: Grant
    Filed: July 1, 2003
    Date of Patent: October 18, 2005
    Assignee: Micron Technology Inc.
    Inventors: Leonard Forbes, Jerome M. Eldridge
  • Patent number: 6952035
    Abstract: A non-volatile memory semiconductor device includes a first insulation layer, two diffusion regions, a memory gate oxide layer, a first control gate, a second insulation layer, a floating gate of polysilicon, a third insulation layer and a second control gate. The first insulation layer is formed on a semiconductor substrate. The two diffusion regions are formed on a surface of the substrate. The memory gate oxide layer is formed over the two diffusion regions on the substrate. The first control gate including a diffusion region is formed on the surface of the substrate. The second insulation layer is formed on the first control gate. The floating gate of polysilicon is formed over the memory gate oxide layer, the first insulation layer, and the second insulation layer. The third insulation layer is formed on the floating gate. The second control gate is disposed on the floating gate.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: October 4, 2005
    Assignee: Ricoh Company, Ltd.
    Inventors: Masaaki Yoshida, Hiroaki Nakanishi
  • Patent number: 6949788
    Abstract: A nonvolatile semiconductor memory device having MONOS type memory cells of increased efficiency by hot electron injection and improved scaling characteristics includes a channel forming region in the vicinity of a surface of a substrate, first and second impurity regions, acting as a source and a drain in operation, formed in the vicinity of the surface of the substrate sandwiching the channel forming region between them, a gate insulating film stacked on the channel forming region and having a plurality of films, and a charge storing means that is formed in the gate insulating film dispersed in the plane facing the channel forming region. A bottom insulating film includes a dielectric film that exhibits a FN type electroconductivity and makes the energy barrier between the bottom insulating film and the substrate lower than that between silicon dioxide and silicon.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: September 27, 2005
    Assignee: Sony Corporation
    Inventors: Ichiro Fujiwara, Toshio Kobayashi
  • Patent number: 6949423
    Abstract: With directly biasing drain to source in a floating-gate N-MOSFET, a new MOSFET-fused nonvolatile ROM cell (MOFROM) is provided by tunneling-induced punch through of the drain junction to the source. The MOFROM is completely compatible with the mainstream standard CMOS process. The standard MOSFET presents an ā€œOFFā€ state before the burning and an ā€œONā€ state with a stable low-resistance path after the burning.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: September 27, 2005
    Assignee: Oakvale Technology
    Inventors: Pingxi Ma, Daniel Fu
  • Patent number: 6943071
    Abstract: A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.
    Type: Grant
    Filed: June 3, 2002
    Date of Patent: September 13, 2005
    Assignee: Intel Corporation
    Inventors: Albert Fazio, Krishna Parat, Glen Wada, Neal Mielke, Rex Stone
  • Patent number: 6940121
    Abstract: A semiconductor memory cell includes a semiconductor substrate that defines a trench having trench walls. The semiconductor memory cell also includes a floating gate electrode positioned within the trench and insulated from the trench walls by a first insulation region; a control gate electrode surrounding the trench; and a second insulation layer on the surface of the semiconductor substrate. The semiconductor memory cell further includes a conductive layer positioned on the second insulation layer. The conductive layer includes a channel region positioned above the floating gate electrode. The semiconductor memory cell also includes a source region and a drain region. The source region and the drain region are each formed in the conductive layer. The source region and the drain region are also connected to the channel region.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: September 6, 2005
    Assignee: Infineon Technology AG
    Inventor: Oliver Gehring
  • Patent number: 6936883
    Abstract: A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. A control gate is connected to each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate.
    Type: Grant
    Filed: April 7, 2003
    Date of Patent: August 30, 2005
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Bomy Chen, Jack Frayer, Dana Lee
  • Patent number: 6933555
    Abstract: A multi-bit split-gate (MSG) flash cell with multi-shared source/drain, a method of making and a method of programming the same are disclosed. Furthermore, a method of bit-by-bit erasing, in addition to page erasing, of a plurality of cells of two or more is disclosed through the application of a positive voltage forced onto the control gate of the unselected cell. Thus, by providing the bit-by-bit erasing flexibility, the bit alterability is enhanced. The MSG is formed with N+1 stacked gates comprising floating gates and control gates, separated by N select gates, all sharing the same source/drain between a pair of bit lines. The programming, that is, writing of the plurality of N+1 bits is accomplished also bit by bit where the programmed bits are selected by word line, bit line and control gate. The read operation is similar to the write operation.
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: August 23, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chia-Ta Hsieh
  • Patent number: 6929993
    Abstract: Floating-gate memory cells having a trench source-line contact are suited for increased packing densities without a need for low-resistance ground straps placed at regular intervals across a memory array. Such floating-gate memory cells have their drain regions and source regions formed in a first semiconductor region having a first conductivity type. This first semiconductor region is separated from the underlying substrate by an interposing second semiconductor region having a second conductivity type different from the first conductivity type. The source regions of the memory cells are coupled to the second semiconductor region as a common source line. Such memory cells can be programmed, read and erased by applying various potential levels to their control gates, their drain regions, the first semiconductor region, and the second semiconductor region.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: August 16, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Ebrahim Abedifard
  • Patent number: 6924184
    Abstract: Via holes to the source/drains of a transistor are made to have very uniform depths so that photoresist thickness can be minimized to reduce the problems associated with small hole vias and vias that are at minimum pitches. This is achieved by polishing a dielectric over the gate stack to a polish stop present over the gate stack to result in having a top surface that is coplanar with the top surface of the polish stop layer over the gate stack. This establishes a top surface that is very uniform in height above the substrate across the wafer. A subsequent dielectric formed on this top surface is thus also very uniform in height over the wafer. The photoresist thickness then can be selected to the least thickness necessary based upon the expectation of maintaining a pattern for etching through a layer of very uniform thickness.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: August 2, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Nigel G. Cave, Anna M. Phillips, Terry G. Sparks
  • Patent number: 6917072
    Abstract: A semiconductor memory device comprises a first conductivity type semiconductor region, a second conductivity type source and drain regions provided in the semiconductor region, a gate insulating film structure provided on the semiconductor region between the source region and drain region and including a first insulating film, a charge accumulation layer and a second insulating film, the charge accumulation layer being selected from a silicon nitride film, a silicon oxynitride film, an alumina film and a stacked film of these films, a control gate electrode provided on the second insulating film, a gate sidewall provided on a side of the control gate electrode and having a thickness thinner than that of the second insulating film in the center of the control gate electrode, a third insulating film provided above the control gate electrode, and a fourth insulating film provided to cover the gate electrode sidewall and the third insulating film.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: July 12, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiro Noguchi, Akira Goda
  • Patent number: 6913974
    Abstract: A flash memory device structure is provided. The flash memory device consists of a P-type substrate with an opening, a deep N-well region in the P-type substrate, a first gate structure and a second gate structure on the respective sidewalls of the opening, an insulating layer in the space between the first gate structure and the second gate structure, a source region in the P-type substrate at the bottom section of the opening, a drain region in the P-type substrate at the top section of the opening, a P-well region in the deep N-well region such that the junction between the P-well and the deep N-well region is at a level higher than the bottom section of the opening and a P-type pocket doping region in the P-type substrate on the sidewalls of the opening such that the P-type pocket doping region connects the P-well region with the source region.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: July 5, 2005
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Chih-Wei Hung, Min-San Huang
  • Patent number: 6913976
    Abstract: Disclosed is a method of manufacturing the semiconductor devices. The method comprising the steps of forming a gate electrode on a semiconductor substrate, depositing an oxide film for a spacer on the gate electrode, implementing an anisotropic dry etch process for the oxide film for the spacer to form spacers at the sidewalls of the gate electrode, and implementing a rapid thermal annealing process for the spacers under an oxygen atmosphere in order to segregate hydrogen contained within the spacers toward the surface. Therefore, hydrogen contained within the spacer oxide film is not diffused into the tunnel oxide film and the film quality of the tunnel oxide film is thus improved. As a result, program or erase operation characteristics of the flash memory device and a retention characteristic of the flash memory device could be improved.
    Type: Grant
    Filed: September 11, 2003
    Date of Patent: July 5, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seung Cheol Lee, Sang Wook Park
  • Patent number: 6913984
    Abstract: A method of fabricating memory with nano dots includes sequentially depositing a first insulating layer, a charge storage layer, a sacrificial layer, and a metal layer on a substrate in which source and drain electrodes are formed, forming a plurality of holes on the resultant structure by anodizing the metal layer and oxidizing portions of the sacrificial layer that are exposed through the holes, patterning the charge storage layer to have nano dots by removing the oxidized metal layer, and etching the sacrificial layer and the charge storage layer using the oxidized sacrificial layer as a mask, and removing the oxidized sacrificial layer, depositing a second insulating layer and a gate electrode on the patterned charge storage layer, and patterning the first insulating layer, the patterned charge storage layer, the second insulating layer, and the gate electrode to a predetermined shape, for forming memory having uniformly distributed nano-scale storage nodes.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: July 5, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-sook Kim, Sun-ae Seo, In-kyeong Yoo, Soo-hwan Jeong